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Digital Alarm Clock by ttl

Catalog Datasheet MFG & Type PDF Document Tags

diagram of IC 74112

Abstract: pin diagram of ttl 74112 floating. 10 REFCLK I TTL Reference Clock: 12.800 MHz (refer to section headed Local , clock or to the XO clock. A soft alarm is raised if the drift is outside ±11.43 ppm and a hard alarm , ): 2.048 MHz 15 Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to , implemented so that a loss of activity of just a few reference clock cycles will raise an alarm and cause a , performance still maintains the advantage of consistent behavior provided by the digital approach
Semtech
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Abstract: INTREQ O TTL/ CMOS TCK I TTLD JTAG Clock: Boundary Scan clock input. If not used , I TTL Reference Clock: 12.8 MHz (refer to section headed Local Oscillator Clock). , : Composite clock, 64 kHz + 8 kHz positive pulse. 30 FrSync O TTL/ CMOS Output reference 10 , can be changed after power up by software. Note.I = Input, O = Output, P = Power, TTLU = TTL , acceptable frequency range measured with respect either to the output clock or to the XO clock. A soft alarm Semtech
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INTEL Core i5 760

Abstract: ACS8942 . INTREQ O TTL/CMOS 9 TCK I TTLD JTAG Clock: Boundary Scan clock input. If not used connect to GND or leave floating. 10 REFCLK I TTL Reference Clock: 12.800 MHz SRCSW I , TTL/CMOS ports are 3 V and 5 V compatible (with clamping if required by connecting the VDD5 pin). The , to the output clock or to the XO clock. A soft alarm is raised if the drift is outside ±11.43 ppm , system performance still maintains the advantage of consistent behavior provided by the digital
Semtech
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pin diagram of ttl 74112

Abstract: ttl 74112 clock cycles will raise an alarm and cause a reference switch. Free-run Locked Digital Holdover , the Master clock failure. The selection of the Master/Slave input can be forced by a Force Fast , Robust activity monitoring on all clock inputs Supports Free-run, Locked and Digital Holdover modes of , JTAG Chip Clock Generator Output Port Frequency Selection Digital Feedback E1/DS1 , : Analog grounds. Supply Voltage: Digital supply to logic, +3.3 Volts ±10%. INTREQ O TTL/CMOS
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ACS8515

Abstract: ACS8525 Master/Slave input can be forced by a Force Fast Switch pin. If both the Master and Slave input clock , . The ACS8525 generates two SEC clock outputs, via one PECL/LVDS and one TTL/CMOS port, with spot , 77.76 MHz via the TTL/CMOS port and up to 155.52/311.04 MHz via the PECL/LVDS port Selectable clock I , Priority Register Set Table TCXO or XO 02 (TTL) Output Port Frequency Selection Digital , 30 31 32 I/O Type INTREQ O TTL/ CMOS 6 REFCLK I TTL Reference Clock
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ACS8515 ACS8526 ACS8527 GR-1244-CORE GR-253-CORE GR-499-CORE ISO9001

GR-253-CORE

Abstract: GR-499-CORE switching against the Master clock failure. The selection of the Master/Slave input can be forced by a , 155.52 MHz clock for local line cards. Master and Slave SEC inputs to the device support TTL/CMOS and , clock outputs, via one PECL/LVDS and one TTL/CMOS port, with spot frequencies from 2 kHz up to 311.04 , TTL/CMOS port and up to 311.04 MHz via the PECL/LVDS port Selectable clock I/O port technologies , Chip Clock Generator APLL2 Priority Register Set Table TCXO or XO 02 (TTL) Output
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S8525

pin diagram of ic 74112

Abstract: G822 Digital Loop Filter PFD TCK TDI TMS TRST TDO IEEE 1149.1 JTAG Chip Clock Generator Priority , /LVDS, 2 x AMI). All the TTL/CMOS ports are 3 V and 5 V compatible (with clamping if required by , respect either to the output clock or to the XO clock. A soft alarm is raised if the drift is outside , /CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS Frequencies Supported 64/8 kHz (composite clock, 64 kHz + 8 , BRIEF Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz
Semtech
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pin diagram of ic 74112 G822 diagram of IC 74112 f8520 pin diagram of ttl 74112 ACS8520 1244-CORE GR-253

GMB HR168

Abstract: takamisawa RELAYS (generated by on board switching power supply), up to 5 TTL digital I/O signals and an analog input , automatic timed commands; 1 TTL output driven by optional on board RTC and visualized by its own LED , TTL PWM to generate a D/A-like signal by software; connection of all signals through Comfortable , . 47 DIGITAL TTL I/O , commands - 1 TTL output driven by optional RTC of Mini Module and visualized by its own LED - Serial line
Grifo
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DIN46277-3 GMB HR168 takamisawa RELAYS 18F4620 HP 4200 MODULBOX BASCOM SOFTWARE DOWNLOAD HR168

to4 88

Abstract: INTEL Core i5 760 REFCLK I TTL Reference Clock: 12.800 MHz SRCSW I TTLD Source Switching: Force Fast , All the TTL/CMOS ports are 3 V and 5 V compatible (with clamping if required by connecting the VDD5 , range measured with respect either to the output clock or to the XO clock. A soft alarm is raised if , ) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest , of activity of just a few reference clock cycles will raise an alarm and cause a reference switch
Semtech
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to4 88 INTEL Core i5 760 transistor to6 4d logic diagram of ic 74112 T010 T011

GR-1244-COR

Abstract: the Master clock failure. The selection of the Master/Slave input can be forced by a Force Fast Switch , SEC and three Sync inputs are TTL/CMOS only. The ACS8525 generates two SEC clock outputs, via one PECL , SEC Outputs: 01 (PECL/LVDS) 02 (TTL) Selector Digital Feedback E1/DS1 Synthesis APLL3 Sync , /CMOS TTL TTLD Description Interrupt Request: Active High/Low software Interrupt output. Reference Clock , against failure of the selected clock. The selection of the Master/Slave input can be forced by a Force
Semtech
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GR-1244-COR
Abstract: switching against the Master clock failure. The selection of the Master/Slave input can be forced by a Force , only. The ACS8525 generates two SEC clock outputs, via one PECL/LVDS and one TTL/CMOS port, with spot , Selection MUX 1 APLL 1 SEC Outputs: 01 (PECL/LVDS) 02 (TTL) Selector Digital Feedback E1/DS1 , of the selected clock. The selection of the Master/Slave input can be forced by a Force Fast Switch , ); Free-run, Locked, or Digital Holdover. In Free-Run mode, the ACS8525 generates a stable, low-noise clock Semtech
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Digital Alarm System Clock in Holdover Mode

Abstract: GR-253-CORE used is lost. 10 GND GND (Digital Ground). 0V 11 SYNC SYNC OUTPUT (TTL Output). This is the system clock output. 12 GND GND (Digital Ground). 0V 13 CLK CLK OUTPUT (TTL Output). This is a monitor output for the system clock. 14 GND GND (Digital Ground). 0V 15 , mode (mode 0) 5 GND 6 ALARM ALARM OUTPUT (TTL Output). This output goes high when the , is used in conjunction with CNTL A to select the device mode. 9 TAL TUNING ALARM (TTL Output
Zarlink Semiconductor
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MHM90401 MT90401 Digital Alarm System Clock in Holdover Mode simple block diagram for digital alarm clock with Digital Alarm Clock by ttl Digital Alarm Clock 40 pin DS5561 GR-1244CORE

mz 1532

Abstract: TDA 957 wavelength channel is selected. Laser Degrade Alarm: TTL compatible output. When provided a digital alarm , generation · Digital laser degraded alarm · Temperature Deviation Alarm · Monitoring for back facet PD , Digital output voltage Analog output voltage Alarm output voltage Alarm output current Storage , ° 24 23 3 4 5 6 Laser Degrade Alarm Shut Down Command Clock mode select Ground 22 21 , Deviation Alarm 18 Clock I²C bus 17 Data I²C bus 16 Wavelength Selection Command 15 Ground 14 No
Alcatel
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STM-16 mz 1532 TDA 957 mz 1540 STM-64 tda 1183 OC-48 F-91625 TR-EOP-000063

Digital Alarm Clock by ttl

Abstract: pcm ami in both modes by a time slot 16 channel pulse and the alarm output provides an indication that the , 16kHz [ 2 CLOCK [ 3 ALARM INHÖBIT [ 4 AMI OP [ 5 ÂMiO/P [ 6 AMBIATA INfOUT [ 7 GROUND [ B ]». >5 , All Inputs and Outputs are TTL Compatible. DIGITAL HIGHWAY A C CESS IN/OUT AMI DATA ÏS Î DATA , (fclo ck = 2.048MHz) Characteristic Propogation delay clock to data out to digital highway Propogation delay clock to 64 kHz out Input delay, clock to digital highway access Input delay, clock to time
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OCR Scan
MJ1446 pcm ami ami circuit diagram DS3131-1 048MH
Abstract: Built-In IEEE-488 and RS-232/422 Interfaces ß 32 TTL Digital Alarm Outputs and 8 TTL Digital Inputs ß , Input/Output (DB50) Connector: Provides easy access to 32 TTL digital alarm outputs and 8 digital , TTL signal, temperature level, IEEE GET, alarm condition, or absolute time of day â'" or upon , steady state. The OMB-MULTISCAN-1200 provides 32 digital alarm outputs that can be activated on a , for constant, per-channel monitoring by the controlling computer. REAL-TIME CLOCK The OMB-MULTISCAN Omega Engineering
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RS-232 OMB-EXP-10A OMB-EXP-11A OMB-MTC-24 OMB-MHV-24X OMB-MHV-24AH

2853S

Abstract: rx 3152 wave. Impedance 50 . CLOCK OUTPUT TTL via 50 . LINE CODES AMI (50% duty cycle), HDB3, B8ZS, B6ZS , (data and clock) TTL. Continuous sequence of 1111. Alternating Connector Alternating sequence , alternated by an external TTL input. The changeover occurs at the end of 8 bits. 1 kHz 0 dBm0 sine wave , selected 64 kbit/s channel is replaced by a test pattern or by an externally input digital signal. Audio , .36), V.35 (using DCE cable adaptor accessory) NRZ (TTL level). Frame or AIS alarm detected All 1
Aeroflex
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RS-449 2853S rx 3152 HDB3 eurocom iso 4903 eurocom d/1 2852/S 2853/S
Abstract: down to 8kHz if required by the DPLL. In addition to digital clock signals from system line cards, the , /CMOS/TTL Inputs Accept Nx8kHz Up to 125MHz Plus 155.52MHz - Two 64kHz Composite Clock Receivers - , CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz - Two LVDS Outputs Each Drive Any , . The T0 and T4 APLLs multiply the clock rates from the DPLLs by four and simulataneously attenuate , Ethernet rates plus 2kHz and 8kHz frame pulses. In addition to creating digital clock signals for use Maxim Integrated Products
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DS3101 GR-1244 125MH

DS3101GN

Abstract: GR378 /8kHz Frame Sync Input 11 Output Clocks - Five CMOS/TTL Outputs Drive Any Internally Produced Clock , . The ICSDM block can also divide the selected clock down to 8kHz if required by the DPLL. In addition to digital clock signals from system line cards, the DS3101 can also directly receive up to two 64kHz , logic, and additional output DFS blocks. The T0 and T4 APLLs multiply the clock rates from the DPLLs by , digital clock signals for use within the system, the DS3101 can also directly transmit one composite
Maxim Integrated Products
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ACS8530 DS3100 DS3101GN GR378 OCXO D14 MCR8 equivalent

SDC38

Abstract: CXB1575AQ interruption alarm output · No reference clock required · Single 3.3V power supply Applications · SONET/SDH , Equivalent circuit Description VCCG 36 CKSEL 3.3 Clock selector (TTL). When low, EXCK is , reallized by fully integrated phase locked loop (PLL), which needs no external reference clock. PLL accepts , CXB1575AQ 155Mbps Clock & Data Recovery with High Sensitivity Limiting Amplifier For the , IC also equipped with the signal interruption alarm output, which is used to discriminate the
Sony
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QFP040-P-0707 SDC38 PRBS23-1 40PIN QFP-40P-L01 42/COPPER

Ic 7423

Abstract: . The ICSDM block can also divide the selected clock down to 8kHz if required by the DPLL. In addition to digital clock signals from system line cards, the DS3101 can also directly receive up to two 64kHz , logic, and additional output DFS blocks. The T0 and T4 APLLs multiply the clock rates from the DPLLs by , digital clock signals for use within the system, the DS3101 can also directly transmit one composite clock , , double-oven OCXO, etc. The 12.8MHz clock from the external oscillator is multiplied by sixteen by the Master
Maxim Integrated Products
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Ic 7423
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