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Delta+I/O

Catalog Datasheet MFG & Type PDF Document Tags

AF27

Abstract: CCII APPLICATION fast edge rates coupled with large parallel I/O buses (DDR) can cause a variety of signal integrity , performance from your system. The following key terms are used in this document: Victim: Any I/O that has , . Aggressor: Any I/O that induces noise can be considered an aggressor. Quiet Low (QL): The quiet low voltage , Corporation AN-472-1.0 1 Preliminary Simultaneous Switching I/O Noise Quiet High Noise (QHN): The , . Simultaneous Switching I/O Noise Introduction Simultaneous switching noise is the inductive noise caused
Altera
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AF27 CCII APPLICATION

alan 100 plus

Abstract: Microwave PIN diode spice exceed 50 percent of the signal noise margin. This goal is achieved by controlling the signal I/O to , it is difficult to predetermine how the circuits will be used. I/O driver circuits may be required , involves an increase in the number of power and ground return paths for I/O, and improvement in power , represents the FPGA silicon and surrounding electronic package. There may be up to 100 drivers in an I/O , that supplies power to the I/O circuits on die may also be at any level of the PCB. SSTL class II is
Altera
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alan 100 plus Microwave PIN diode spice power supply diagram CP-01023-1

Switching power supplies Delta electronics

Abstract: design of Electrical Power Distribution transform DesignCon 2008 FPGA I/O Timing Variations Due to Simultaneous Switching Outputs Zhe Li , modern nano-technology devices. There is a lack of research of I/O timing variations due to SSO; the , , modeling, and correlation of FPGA high-speed I/O interfaces. Iliya Zamek has over 20 years of experience , SYSTEM AND I/O BUFFER CIRCUITS 1. FPGA SYSTEM 2. I/O BUFFER III. OUTPUT DRIVER SIGNAL TIMING , contrast, the research of timing variations due to I/O switching noise is just at the beginning
Altera
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CP-01041-1 Switching power supplies Delta electronics design of Electrical Power Distribution transform circuit diagram of mosfet based power supply Q-Tech 200w computer power supply Circuit diagram Altera DDR3 FPGA sampling oscilloscope

SIGNAL PATH designer

Abstract: SSTL-18 determine the pin placement and I/O settings to optimize performance. By following some simple guidelines , /O settings and selecting proper I/O standards, and provides guidelines on PCB design that are good , works for any individual I/O standard. However, FPGAs are programmable. It is difficult to predetermine how the circuits will be used. I/O drivers may be utilized in different I/O standards, such as , technology. For different I/O standards, an absolute voltage cannot indicate how much the noise impacts the
Altera
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SIGNAL PATH designer SSTL-18

BAT900

Abstract: PEEL programming technology going to nanometer feature dimension, I/O buffers are driven by ever lower supply voltages. The , interface types, I/O bus width, current drive strength, and multi-chip vertical migration. In the meantime , voltage dropped over PDN such that VCCIO at I/O buffer is v less supply voltage. Drawn by a piece-wise waveform close to PDN represents power sag caused by delta-I mechanism. A non-toggling I/O, often referred , through I/O trace to the outside of the package where it can be measured. On its way out of the package
Altera
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BAT900 PEEL programming T-950
Abstract: Singapore 368363 Taoyuan County 320 High-Tech Zone West Taiwan R. O. C. Nanshan District Shanghai Pulse Electronics
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PA3146 121HL 151HL 181HL 211HL 231HL

A54SX72A

Abstract: Actel A40MX04 and usually has a pulse width of approximately 500 ns. Table 1 on page 2 summarizes I/O behavior , device. They give an estimate of source and sink currents per I/O basis. IOH and IOL are specified in , placement of the driving source cells and the I/O cells. Table 1 · Power-Up/Down Behavior of Actel Devices I/O Behavior during Power-Up Slow Power-Up (0.2 V/ms) Fast Power-Up (0.5 V/us) Power-Up , Board-Level Considerations Unused I/O Configuration For all of Actel's antifuse-based FPGAs, I/O modules
Actel
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A54SX72A Actel A40MX04 A40MX04 A42MX09 actel a40mx02 AC276

PA3146

Abstract: Singapore 368363 Taoyuan County 320 High-Tech Zone West Taiwan R. O. C. Nanshan District Shanghai 200336 Tel
Pulse Electronics
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271HL 301HL D-71083
Abstract: DesignCon 2008 A Fast Algorithm to Instantly Predict FPGA SSN for Various I/O Pin Assignments , switching noise (SSN) for FPGA I/O pin assignments. In this algorithm, SSN has two distinct components , device-level characterization and system-level verification infrastructure development, high-speed I/O, memory , element and I/O densities. Meanwhile, lower power supply and higher speed have emerged as principal , return-current pins) to I/O pins, this approach sacrifices I/O densities. Engineers can improve PDN performance Avago Technologies
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AFBR-1012/AFBR-2012 AFBR-1012 AFBR-2012 152MB AFBR-2013S AFBR-2013L

9524 pc

Abstract: 90 nm hspice arena. It is designed to enable very high performance, high I/O, and the use of large, high density , speed, both on and off chip, more I/O, greater I/O density, and higher power. In addition, the , with BGA I/O count to over 1600 on either 1.0 or 1.27 mm centers, and will accomodate over 18mm die with signal I/O count in excess of 1100 on 225 um centers. Package design characteristics are , Pitch 1.27m m total I/O 624 728 840 960 1,088 Pitch 1.27mm Pitch 1.00mm Pitch
Altera
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9524 pc 90 nm hspice cp-01035 IC K140 CP-01035-1
Abstract: circuit design. In June 2007, he joined Altera's Toronto Technology Office where he works in the I/O , University of Toronto. His areas of expertise include I/O modeling, circuit simulation, and SSN. He currently manages Altera's I/O modeling group and is responsible for I/O timing, power and signal integrity , defined as a noise voltage induced onto a single victim I/O pin of an electronic component due to the switching behavior of other aggressor I/O pins in the device. SSN often leads to the degradation of signal Staco Energy Products
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501-C M501C 5M501C

"0.4mm" bga "ball collapse" height

Abstract: cga 624 _2 VDD_2 VDEC_2 VSS_2 OUT_2 N/C TESTANA_1 MUST1_1 MUST0_1 VDD_1 VDEC_1 I/O G O O I I S S G O O I I S S , during which the correct process ability is guaranteed. Exceeding t h e a b s o l u t e m a x i m u m r a t i n g s m a y c a u s e p e r m a n e n t d a m a g e . Exposure t o a b s o l u t e maximum , LSB12 % % mT o o o Field Range C C C Rev. 2 Page 10 of 27 Mar/12 MLX90292 SMD , S1 0 N1 2 D0 C0 S0 0 N0 1 P0 o o o o 0 W2 1 1 0 0 10 W1 1 0 1 0 9 D7 0 D205B MSB D205A
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cga 624 ibm semi reflow temperature bga
Abstract: _1 I/O G O O I I S S G O O I I S S Description Ground Not used Digital output, open drain For Test For , 155 +10 LSB12 % % mT o o o Field Range C C C Rev. 1.0 Page 10 of 27 June, 3rd 2011 , S0 0 N0 1 P0 o o o o 0 W2 1 1 0 0 10 W1 1 0 1 0 9 D7 0 D205B MSB D205A MSB D2059 MSB 8 , D2059 LSB 1 P0 o o o o 0 Last Manufacturing Data Package St2 St1 W2 W1 1 0 0 1 1 2 0 0 1 0 3 4 0 0 , o o o o 0 St2,St1 = W = Two consecutive start bits, always zero Label for frame identification Xilinx
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Q1-02
Abstract: engineering manager overseeing the characterization of I/O, external memory interfaces, and signal/power , . It becomes ever challenging to meet I/O jitter specifications and the core-logic timing closure with , edge of the clock signal. Customer Random I/O I/O Core Logic clock Random toggling , at 533 MHz 17 Jitter and Timing Implications On-chip PDN noise can dramatically increase I/O , , "Broadband Methodology for Power Distribution System Analysis of Chip, Package, and Board for High-Speed I/O Staco Energy Products
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1010B 1020B 1010BCT M1010B M1010BCT 1010B-2
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