500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
TP3070V-G/63 Texas Instruments IC PROGRAMMABLE CODEC, Codec visit Texas Instruments
TLC32044IFN Texas Instruments PCM CODEC, PQCC28 visit Texas Instruments
TLC32040MFK Texas Instruments PCM CODEC, CQCC28 visit Texas Instruments
TLC32041IFN Texas Instruments PCM CODEC, PQCC28 visit Texas Instruments
TLC32041CFNR Texas Instruments PCM CODEC, PQCC28 visit Texas Instruments
TLC32044IFNR Texas Instruments PCM CODEC, PQCC28 visit Texas Instruments

Decoder 5 to 32

Catalog Datasheet MFG & Type PDF Document Tags

return to zero decoder

Abstract: psoc example projects the cyfitter.h file. Document Number: 001-69402 Rev. *A Page 5 of 32 Quadrature Decoder , General Description The Quadrature Decoder (QuadDec) Component gives you the ability to count transitions , per rotation. When to Use a Quadrature Decoder A quadrature decoder is used to decode the output , ISR is used. To work properly with the 32-bit counter, interrupts must be enabled. You can add ISR , Number: 001-69402 Rev. *A Page 3 of 32 Quadrature Decoder (QuadDec) PSoC® CreatorTM Component
Cypress Semiconductor
Original

downmix 5.1 to 2 channel

Abstract: dolby digital decoder 0 through AB 5 in Figure 2) contains various pieces of information that tell the decoder how to , compares favorably with floating-point based implementations. Typically Intel's decoder has about 5 to 10 , Laboratories has developed a stringent test suite to ensure that a certified decoder indeed provides high , uniformly through a Dolby Digital decoder is insufficient to pass the test suite. The challenge was to , implementer to increase the audio quality of the decoder while still providing a significant speedup over
Intel
Original

27mhz remote control transmitter circuit

Abstract: PAL to ITU-R BT.601/656 Decoder Plane 5th still picture plane available in MPEG video decoder OSD, used for MHP or MHEG-5 , Letterbox and 4:3 to 16:9 format conversion with programmable 5-segment Panoramic mode Picture Structure , product now in development or undergoing evaluation. Details are subject to change without notice. 1/32 , Diagnostic Controller Interrupt Controller MPEG 2 Video Decoder Slave Controller ST20 32-bit CPU , . 5 1.2.1 MPEG Video Decoder
STMicroelectronics
Original

r02101

Abstract: 433MHz saw Based Transmitter Schematic and PCB comprising the system. The software can be used to implement a stand alone decoder or integrate with full , the transmission, principally containing the encoder's serial number identifying it to a decoder , to identify the encoder to the decoder. Hopping Code The hopping code contains function , , this information can be used to check integrity of decryption operation by a decoder. If known , the decoder to check whether the information has been decrypted correctly. 12 bits (including
Microchip Technology
Original

HCS500

Abstract: 5 to 32 line decoder controller device. The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes , input to the encryption algorithm and the output is 32 bits of encrypted information. This data will , referred to as the hopping portion of the code word. The 32-bit hopping code is combined with the button , that allows the decoder to operate in conjunction with an HCS500 based transmitter. Section 3.0
Microchip Technology
Original
5 to 32 line decoder HCS301 transmitter 24LC02 B416 C316 D216 11F-3 DK-2750 D-81739 DS40153C-

8 bit wide 2 to 1 multiplexer

Abstract: demultiplexer VHCT 3-to-8 Decoder/Demultiplexer DIP SOIC SOP TSSOP 5 74ACT139 FACT (ACT) Dual 1-of-4 Decoder/Demultiplexer DIP SOIC SOP TSSOP 5 DM74ALS137 Bipolar-ALS 3-Line to 8 , 3-to-8 Decoder/Demultiplexer DIP SOIC SOP TSSOP 3.3 5 DM74ALS138 Bipolar-ALS 3 to 8 Line Decoder/Demultiplexer DIP SOIC SOP 5 DM74LS138 Bipolar-LS 3-to-8 Line Decoder/Demultiplexer DIP SOIC SOP 5 DM74S138 Bipolar-Schottky 3-to-8 Line Decoder
Fairchild Semiconductor
Original
NC7SZ18 NC7SZ19 74ACT138 74VHCT138A 74AC138 74F138 8 bit wide 2 to 1 multiplexer demultiplexer Decoder 5 to 32 of 8 bit dip switch 8 bit dip switch

timing diagram for 8 to 3 decoder

Abstract: timing DIAGRAM OF ROM :32] MCE ROM (64K x 16) MA[8:0] MA[21:9] MD[15:0] CE OE Figure 9-1 ZiVA Decoder to Memory , all of the information necessary to connect the ZiVA decoder to an extended data out (EDO) DRAM array , control signals required to access external EDO DRAMs and ROMs. 9.1.1 DRAM The ZiVA decoder's DRAM , , with one additional 256K x 16 DRAM, the ZiVA decoder can interface to 20 Mbits. The decoder's DRAM controller can support up to 32 Mbits of local DRAM; however, only 16 Mbits of DRAM are needed to read
-
Original
timing diagram for 8 to 3 decoder timing DIAGRAM OF ROM 4 Signal s ZiVA

32LQD

Abstract: 1024-pulse Freescale Semiconductor, Inc. AN2511/D Rev. 0, 5/2003 32-bit Linear Quadrature Decoder TPU , initialization, the PC is set to a 32-bit PC_init value entered by the CPU. 32-bit Linear Quadrature Decoder , 32-bit Linear Quadrature Decoder (32LQD) TPU Function Set is useful for decoding position, direction , : · 32-bit Linear Quadrature Decoder (32LQD) · Home Channel for 32-bit Linear Quadrature Decoder (32LQD_Home) · Velocity Support for 32-bit Linear Quadrature Decoder (32LQD_VS) The 32
Freescale Semiconductor
Original
1024-pulse 5 to 32 decoder Quadrature Decoder Interface ICs MPC500 quadrature decoder

E1 HDB3

Abstract: 16 line to 4 line coder multiplexer = ±5%, GND = 0V. Figure 5: HDB3 Encoder and Decoder Timing (Refer to Table 5) t cyc t pwh , input clocked on the rising edge of MHHDB3C. 45 MHHDB3C 48 DHDPI HDB3 Decoder #5 Positive Data Input. HDB3 Decoder #5 (High Speed) positive rail input clocked on the ri sing edge of DHHDB3C. 49 DHDNI HDB3 Decoder #5 Negative Data Input. HDB3 Decoder #5 (High Speed) positi ve rail input clocked on the ri sing edge of DHHDB3C. 50 DHHDB3C HDB3 Decoder #5 Clock Input
-
Original
SXT6234 E1 HDB3 16 line to 4 line coder multiplexer HDB3 AMI ENCODER DECODER HDB3 to nrz Frame structure for Multiplexing of four E2 streams into E3 stream circuit diagram of 64-1 multiplexer LXT305/332

5 to 32 decoder

Abstract: 1024-pulse 6 5 0 1 2 3 4 5 6 PC_VS_ADDR 7 32-bit Linear Quadrature Decoder TPU Function Set (32LQD , Freescale Semiconductor, Inc. Application Note AN2511/D Rev. 0, 5/2003 32-bit Linear Quadrature , . Functional Overview 32-bit Linear Quadrature Decoder (32LQD) TPU Function Set is useful for decoding , functions: · 32-bit Linear Quadrature Decoder (32LQD) · Home Channel for 32-bit Linear Quadrature Decoder (32LQD_Home) · Velocity Support for 32-bit Linear Quadrature Decoder (32LQD_VS) The 32
Motorola
Original
5 to 32 decoder circuit decoder and encoder AN2511

psoc full projects

Abstract: control of motor using psoc ) General Description The Quadrature Decoder (QuadDec) component provides the ability to count transitions , rotation. When to Use a Quadrature Decoder A Quadrature Decoder is used to decode the output of a , Setup Drag a Quadrature Decoder component onto your design and double-click it to open the Configure , resource usage. For this target, an additional ISR is used. To work properly with the 32-bit counter , Quadrature Decoder (QuadDec) Enable Glitch Filtering Tab This tab contains a field to enable/disable
Cypress Semiconductor
Original
psoc full projects control of motor using psoc quadrature encoder 4X psoc projects

24LC02

Abstract: HCS200 detection 7 RFIN 6 S_CLK 5 RFIN Stand-alone decoder chipset External EEPROM for , . Compatible Encoders The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes , serial number to form the code word transmitted to the receiver. FIGURE 1-2: HCS Decoder Overview , Microchip Technology Inc. HCS500 3.0 DECODER OPERATION 3.1 Learning a Transmitter to a
Microchip Technology
Original
HCS200 HCS300 HCS301 HCS360 HCS410 circuit diagram of Garage Door Openers HCS301 QS-9000

32 line to 5 encoder IC

Abstract: hcs500 5.5 volts. The decoder employs automatic bit-rate detection, which allows it to compensate for wide variations in transmitter data rate. The decoder contains sophisticated error checking algorithms to ensure , â'˜scanningâ'™. FIGURE 1-1 : D S 4 0 1 5 3 B -p a g e 2 â'¢ A 28-bit serial number which is meant to , referred to as the code hopping portion of the code word. The 32-bit code hop­ ping portion is combined , . HCS500 3.0 DECODER OPERATION 3.1 Learning a Transmitter to a Receiver (Normal or Secure Learn
-
OCR Scan
32 line to 5 encoder IC HCS500T

hcs500

Abstract: controller device. The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes are , with every button press, hence, it is referred to as the code hopping portion of the code word. The 32 , word transmitted to the receiver. 1.3 HCS Decoder Overview Before a transmitter and receiver , Microchip Technology Inc. HCS500 3.0 3.1 DECODER OPERATION Learning a Transmitter to a Receiver
Microchip Technology
Original
D-82152 DS40153B-

avia

Abstract: Decoder 5 to 32 decoder's DRAM controller can support up to 32 Mbits of local DRAM; however, only 16 Mbits of DRAM are , [8:0] MDATA[60:48] MDATA[47:32] MCE Figure 9-1 AViA Decoder to Memory Connection (16- and 20 , decoder outputs the column address of the first word to be read on MADDR. 5. The decoder latches the , all of the information necessary to connect the AViA decoder to an extended data out (EDO) DRAM array , the control signals required to access external EDO DRAMs and SRAMs. 9.1.1 DRAM The AViA decoder
-
Original
avia

AHA4524A-031

Abstract: AHA4524A-031PTI deinterleaved before decoding. The decoder output is descrambled, and the CRC is computed to verify data , option to accept 4 bit parallel soft metric data symbols. The parallel decoder input is used to support , Programmable decoder input quantization for up to 4 bit wide soft metrics · Programmable iterations up to 255 , ASIC/DSP to block and prepare the Figure 2: data for the AHA4524 decoder. Data blocks are then , ENCODER/DECODER The AHA4524 device is a single-chip Turbo Product Code (TPC) Forward Error Correction
Comtech AHA
Original
AHA4524A-031 PB4524 AHA4524A-031PTI R793 Comtech Aha Corporation 8 TO 64 DECODER

datasheet tca 786

Abstract: HCS500 . Compatible Encoders The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes , serial number to form the code word transmitted to the receiver. FIGURE 1-2: HCS Decoder Overview , Microchip Technology Inc. HCS500 3.0 DECODER OPERATION 3.1 Learning a Transmitter to a , , consequently, can store up to seven transmitters. During the learn procedure, the decoder searches for an
Microchip Technology
Original
datasheet tca 786 rf encoder and decoder F016 24LC02B HCS200 transmitter

quadrature decoder

Abstract: quadrature decoder 4X General Description The Quadrature Decoder (QuadDec) Component gives you the ability to count transitions , per rotation. When to Use a Quadrature Decoder A quadrature decoder is used to decode the output , ISR is used. To work properly with the 32-bit counter, interrupts must be enabled. You can add ISR , violations when the target device is a PSoC 5. It is recommended to limit the BUS_CLK frequency to 36 MHz for PSoC 5 projects. Document Number: 001-79365 Rev. * Page 5 of 17 Quadrature Decoder (QuadDec
Cypress Semiconductor
Original
quadrature decoder 4X

AHA4524A-031

Abstract: code of encoder and decoder in rs(255,239) deinterleaved before decoding. The decoder output is descrambled, and the CRC is computed to verify data , option to accept 4 bit parallel soft metric data symbols. The parallel decoder input is used to support , Figure 2: data for the AHA4524 decoder. Data blocks are then transferred to the AHA4524 for TPC , iter 1.E-08 TPC(64,57)^2, 32 iter 1.E-09 1.E-10 0 1 2 3 4 5 6 Eb/No (dB , /DECODER The AHA4524 device is a single-chip Turbo Product Code (TPC) Forward Error Correction (FEC
Advanced Hardware Architectures
Original
code of encoder and decoder in rs(255,239) serial parallel decoder block diagram of 2 to 4 decoder

HCTL-2022

Abstract: Decoder 5 to 32 single ic intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2032 consists of 4x , to 100oC 32-Pin PDIP, 32-Pin SOIC Applications Interface Quadrature Incremental Encoders to , functions to a cost effective hardware solution. The HCTL-20XX-XX consists of a quadrature decoder logic, a , . The HCTL-2022 doesn't provide decoder output and cascade signals. Interfaces Encoder to , : -40°C to 100°C 32-Pin PDIP, 32-Pin SOIC, 20-Pin PDIP Applications · Interface Quadrature
-
Original
Decoder 5 to 32 single ic HCTL-2032-SC HCTL-2032-SCT hctl 2032 counter quadrature decoder ic hctl 2032 encoder counter HCTL2032
Showing first 20 results.