DVME-611/612 DVME-611 SE/16 DVME-612 DVME-641 DVME-643 DVME-645 DVME-611D

DVME-611/612 ® 32S/16D-Channel VME A/D-D/A Boards FEATURES · Two models of VMEbus-based boards DVME-611: 32 SE/16 D

® DVME-611/612 DVME-611/612 ® 32S/16D-Channel VME A/D-D/A Boards FEATURES · Two models of VMEbus-based boards DVME-611 DVME-611: 32 SE/16 SE/16 D A/D channels DVME-612 DVME-612: 32 SE/16 SE/16 D A/D channels and 2 D/A channels · Choice of A/D bits/speed 12 bits/2, 4, or 20 µSec. 14 bits/4 µSec. 16 bits/ 35 µSec. · Four input voltage ranges available: ±10 V, ±5 V, 0 to +5 V, and 0 to +10 VDC · Three types of output coding: Bipolar 2's complement Bipolar offset binary Unipolar straight binary · Up to 400 KHz throughput with a fast throughput mode for high-speed data transfers · On-board interrupt vector register for host system's service routines · Up to 0.0063% full-scale range accuracy and ±1/2 LSB linearity error · 80 dB CMRR at gain of 128 The host-programmable command register controls the A/D conversion process. Depending upon the contents of the command register, an external trigger may also initiate the A/D conversion process. The host system may obtain information pertaining to the A/D conversion and control selections by reading the status register. · Eight-stage programmable gain amplifier (PGA) · ±0.05% full-scale range accuracy for D/A channels · Channel expansion boards for up to 256 channels DVME-641 DVME-641: Non-isolated, high-level inputs DVME-643 DVME-643: Isolated, thermocouple, RTD, high-level, 4-to-20 mA inputs DVME-645 DVME-645: Simultaneous sample/hold inputs The channel and control information from the channel select logic section is brought out to the J4 expansion connector. The control lines include End of Conversion (EOC), End of Scan (EOS), settling time delay, and external trigger signals. These control signals on the expansion connector are also usable with externally multiplexed input channels. The host system selects the start and final channels for the A/D scanning process. · Two TTL digital outputs The DVME-611/612 DVME-611/612 are DATEL's VMEbus based high-end A/D conversion boards. The A/D boards provide up to 16-bit binary data from up to 32 single-ended or 16 differential analog input channels. DATEL also offers optional expansion boards for up to 256 single-ended or differential analog input channels. The DVME-612 DVME-612 is also equipped with two D/A channels, operable in four output voltage ranges. The analog output section on the DVME-612 DVME-612 offers ±1/2 LSB differential non-linearity and operates at ±0.05% of full-scale range accuracy. Functionally, the analog signal from the input channel is amplified and converted into binary data. The resolution depends on the A/D converter module used. Figure 1 is a functional block diagram of the DVME-611/612 DVME-611/612 A/D boards. Data from the A/D converter module is coded via jumpers into straight binary, offset binary, or 2's complement coding. The binary A/D data is transferred to the host system through the VMEbus transceivers. The on-board hardware essentially consists of multiplexers, a PGA, an A/D converter, and registers. The PGA is programmable for gains from 1 to 128 in binary increments. Both the DVME-611 DVME-611 and the DVME-612 DVME-612 are available in several models depending upon the A/D converter module used. The A/D converter modules are easily field-replaceable. All models except the DVME-611D DVME-611D and the DVME-612D DVME-612D contain a sample/hold amplifier. DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 149 Email: sales@datel.com · Internet: www.datel.com ® ® DVME-611/612 DVME-611/612 The DVME-611/612 DVME-611/612 A/D boards can operate in a fast throughput mode for applications requiring fast data transfers. This mode is selectable using the command register. The fast throughput mode guarantees transfer of A/D data on to the VMEbus without having to test the conversion status. When A/D data is read, this mode delays the host CPU DTACK* while EOC = 0. The DVME-611/612 DVME-611/612 generates the data acknowledge (DTACK*) signal to notify acceptance of data from the VME data lines, D00 through D15. The DTACK* signal is jumperselectable for delay times from 125 nanoseconds to 1000 nanoseconds, accommodating different host systems. The interface logic decodes VMEbus control lines (WRITE*, DS0*, DS1*, and AS*) to provide the interface control signals. These signals control the board select and the VMEbus transfer functions. The DVME-611/612 DVME-611/612 uses programmable array logic (PAL) devices for interface and control, guaranteeing true asynchronous operation. The DVME-611/612 DVME-611/612 A/D boards come with a user's manual. The user's manual describes the installation and calibration procedures for different applications and explains the theory of operation of the A/D boards. The user's manual also contains information on troubleshooting the boards. The boards are shipped with an MS-DOS disk containing an example source program. Consult the factory regarding the availability of the diagnostic program's source code in other disk formats. VMEbus Interrupt Logic The interrupt logic section senses an EOC or EOS condition and generates an interrupt request on one of the VMEbus interrupt lines (IRQ1* through IRQ7*). The interrupt lines are jumper-selectable. The interrupt logic accepts IACK* and IACKIN* signals from the host system as interrupt acknowledge and daisy chain input signals. Depending upon the interrupt level, the on-board logic loads the interrupt ID number on to the VMEbus or generates the daisy chain IACKOUT* signal. VME Interface The DVME-611/612 DVME-611/612 interfaces to the host system using the P1 connector. The board uses short I/O space address lines and 16 data lines. On-board switches select the base address of the board. The board responds to address modifier codes 29H, 2DH, 39H, and 3DH for data output purposes. ANALOG IN P U T CH AN NELS 3 2 S E /1 6 D D IG IT A L OUTPUTS GP0 GP1 ADDRESS AND CONTROL FOR E X P A N S IO N CH AN NELS VOUT 0 AGND VOUT 1 AGND M U L T IP L E X E R S S & H + A /D CONVERTER PGA COMMAND R E G IS T E R C O N V E R S IO N C O N TR O L L O G IC IN T E R R U P T ID R E G IS T E R EOS STATUS R E G IS T E R CHANNEL SELECT L O G IC EOC IN T E R R U P T L O G IC D /A CONVERTER D /A CONVERTER N O TE : The VM E bus SY SCLK signal is required. Figure 1. DVME-611/612 DVME-611/612 Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 150 Email: sales@datel.com · Internet: www.datel.com ® ® DVME-611/612 DVME-611/612 Min. conversion time (for step input at rated accuracy, typical) DVME-611A/612A DVME-611A/612A 20 µS at a gain of 1 110 µS at a gain of 128 DVME-611B DVME-611B,E/612B E/612B,E 8 µS at a gain of 1 102 µS at a gain of 128 DVME-611C/612C DVME-611C/612C 35 µS at a gain of 1 110 µS at a gain of 128 DVME-611D/612D DVME-611D/612D 400 mS at a gain of 1 400 mS at a gain of 128 Note: Allow 20 minutes warm-up for DVME-611F/612F DVME-611F/612F FUNCTIONAL SPECIFICATIONS (Typical at 25 °C, unless otherwise noted) VMEbus INTERFACE Data Bus 16 Bits. (A16:D16 slave) Address Bus Short I/O Space 16 address lines Address Mod. Codes 29h, 2Dh, 39h, and 3Dh Interrupts 1 line, jumper-selectable 2 interrupt ID's for EOC and EOS Software programmable Memory Mapping Short I/O space, user or supervisor 256 words allocated per board Data Transfer DTACK* signal line Acknowledges the VMEbus host that data has been placed or accepted from the VMEbus data lines ANALOG INPUT Number of Channels 32 SE or 16 Diff. Channel Expansion 256 single-ended or differential; requires external multiplexing. Use DATEL's DVME-641 DVME-641, DVME-643 DVME-643, or DVME-645 DVME-645 mux boards. Input Configuration Single-ended or differential Input Ranges ±10 V, ±5 V, 0 to +5 V, or 0 to +10 V, jumper-selectable Digital Outputs Standard Offset binary Jumperable Straight binary or 2's comp. External Start Trigger TTL comp., negative-going edge. Minimum pulse width = 100 nS Maximum pulse width = 2 µS Common Mode Voltage ±10 VDC, max., non-isolated Input Bias Current 8 nA, maximum Over Voltage Protection ±35 VDC, maximum Input Impedance Differential to ground 10 M, minimum PERFORMANCE Programmable Gain Uses an AM-543MC AM-543MC for gains of X1, X2, X4, X8, X16, X32, X64, X128 Common Mode Rejection for ±10 V input signal 75 dB at a gain of 2 at 60 Hz, minimum 80 dB at a gain of 128 Full-Scale Range Accuracy, minimum DVME-611A/612A DVME-611A/612A 0.025% at a gain of 1 DVME-611E/612E DVME-611E/612E 0.20% at a gain of 128 DVME-611B/612B DVME-611B/612B 0.05% at a gain of 1 0.20% at a gain of 128 DVME-611C/612C DVME-611C/612C 0.010% at a gain of 1 0.20% at a gain of 128 DVME-611D/612D DVME-611D/612D 0.0063% at a gain of 1 0.20% at a gain of 128 DVME-611F/612F DVME-611F/612F 0.01% at a gain of 1 PGA plus MUX Settling Time, maximum 8 µS at a gain of 1 12 µS at a gain of 16 40 µS at a gain of 64 100 µS at a gain of 128 Resolution and Throughput (Scan Mode) Resolution Conversion in bits time DVME-611A/612A DVME-611A/612A DVME-611B/612B DVME-611B/612B DVME-611C/612C DVME-611C/612C DVME-611D/612D DVME-611D/612D DVME-611E/612E DVME-611E/612E DVME-611F/612F DVME-611F/612F 12 12 16 16 12 14 20 µS 4µS 35 µS 400mS 2 µS 4 µS Throughput conversions/ sec. 40320 160,000 18,667 2.5 see notes 100,000 Temperature Drift and Linearity Gain Zero Temperature Temperature Linearity Coefficient Drift Error, (ppm/ °C) (ppm/ °C) maximum Model DVME-611A/612A DVME-611A/612A DVME-611B/612B DVME-611B/612B DVME-611C/612C DVME-611C/612C DVME-611D/612D DVME-611D/612D DVME-611E/612E DVME-611E/612E DVME-611F/612F DVME-611F/612F ±20 ±20 ±20 ±10 ±20 ±15 20 20 20 10 ±20 ±15 1/2 LSB 1/2 LSB 2 LSB 2 LSB 1/2 LSB 2 LSB Optional Multiplexer Expansion Boards Model Number of expansion channels Single-ended Differential Input type DVME-641 DVME-641 32 16 High-level, non-isolated DVME-643T DVME-643T - 8 Thermo couple Isolated DVME-643H DVME-643H - 8 High-level Isolated DVME-645 DVME-645 16 8 Simultaneous Sample/Hold high-level non-isolated DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 151 Email: sales@datel.com · Internet: www.datel.com ® ® DVME-611/612 DVME-611/612 Table 1. DVME-611/612 DVME-611/612 Hardware Register Functions ANALOG OUTPUT (For DVME-612 DVME-612 models only) Number of Channels Output Range Digital Input Coding Resolution Reset Full-Scale Range Accuracy Diff. Non-Linearity Zero Temperature Drift Offset Temperature Drift Gain Temperature Drift Settling Time Output Current Output Impedance Address 2 ±10V, ±5V, 0 to +5V, or 0 to +10V Bipolar 2's complement, bipolar offset binary or unipolar straight binary 12 Bits, bits D0 through D3 not used Minus, full-scale, -10V for 2's complement and offset binary 0V for Unipolar 05%, minimum 0.5 LSB, minimum 5 ppm/ °C, maximum 20 ppm/ °C, maximum 20 ppm/ °C, maximum 10 µS, maximum 5 milliamps, maximum 50 milliohms, typical Read Write Read Write Write Write Write Read Write Write Read Write Write Command register (80h) Status register Interrupt ID register (82h) EOC/EOS F/F Reset (84h) Gain register (86h) Start channel register (88h) Current channel register Final channel register (8Ah) Start conversion register (8Ch) Status register (8Eh) D/A channel 0 (A0h) D/A channel 1 (A2h) The DVME-611/612 DVME-611/612 boards scan their selected channels under control of the 16-bit command register. Programming the command register selects the modes for starting conversion, calibration, and fast throughput. This register also enables the interrupt, channel address auto-increment, and channel re-scan capabilities. Figure 2 shows the command register format. +5V dc ±5% at 2.5 Amperes Note: On-board dc-to-dc converter generates ±15V dc for the DVME-611/612 DVME-611/612 logic circuits CONNECTORS VMEbus P1 connector 96-pin male DIN connector J1 and J2 Analog Input Connectors 25-pin D-type female connectors J3 Analog Output Connector 9-pin D-type female connector J4 Analog Expansion Connector 25-pin D-type female connector Status Register The DVME-611/612 DVME-611/612 status register indicates conditions relating to conversion status, channel scanning information, and modes selected. Figure 3 shows the status register format. Total System Throughput PHYSICAL/ENVIRONMENTAL Weight Operating Temp. Range Storage Temp. Range Relative Humidity Contents Manufacturer's/Board's identification Command Register POWER SUPPLY REQUIREMENTS Outline Dimensions Function Base + 0 through Base + 63 Base + 128 Base + 128 Base + 130 Base + 132 Base + 134 Base + 136 Base + 136 Base + 138 Base + 140 Base + 142 Base + 160 Base + 162 Total sample-to-sample throughput rate depends on the A/DS/H settling and conversion period and the user's software period. During the software interval, data is transferred to the host and the next A/D conversion is started. By combining fast throughput mode (DTACK* EOC holdoff) with convert-onread-data, throughput over 400 KHz may be achieved for gain = 1 in single channel mode for model DVME-611E DVME-611E. Data transfer and host memory pointer management may partially overlap A/D Conversion by using the convert-on-read mode. 9.19"W x 6.3"D x 0.6"H (233.5 x 160 x 15.24 mm) 1 lb. 0.5 oz. (467.8 grams) 0 to +60 °C -20 to +80 °C 0 to 90%, non-condensing DVME-611/612 DVME-611/612 Programming Information The DVME-611/612 DVME-611/612 A/D boards use ten registers for data acquisition and control purposes. Table 1 lists the DVME-611/612 DVME-611/612 registers and their base address offsets. These registers are addressable locations in the host system's address space. Fast Throughput Mode This mode holds off response of the DTACK* VMEbus signal with the simultaneous ANDing of three conditions: command register bit 5 = 1, EOC = 0, and a host read of the A/D data register. While DTACK* is held off, the host CPU executes wait states. When A/D conversion finishes, EOC = 1 and DTACK* is released. Normally the attempted A/D data read now completes, and data is transferred without any EOC polling. Fast throughput should be used with caution since the host must be completely dedicated to A/D data acquisition. Table 2. A/D Full Scale Input Ranges (PGA gain = 1) Input Range 611/612A 611/612A 611/612B 611/612B,E 0 to +5 0 to + 10V ±5V ±10V X X X X NA X NA X Model 611/612C 611/612C 611/612D 611/612D 611/612F 611/612F 611C-U 611C-U 611C-U 611C-U X X NA NA NA X NA S S X X = supplied, NA = not available, S = solderable on module, -U = special order DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 152 Email: sales@datel.com · Internet: www.datel.com ® ® DVME-611/612 DVME-611/612 Location: Base +128 (Word address) 15 14 13 12 11 10 9 8 x x x x x x x x 7 6 5 4 3 2 1 0 A/D Conversion Start Source: 0 0 Conversion begins when the host system writes to the Start Conversion register. 0 1 Conversion begins when the host system writes to the Start Conversion register or on an A/D read operation. 1 0 Conversion begins on an external trigger. 1 1 Conversion begins on external trigger or A/D data read. 0 Disable A/D converter. 1 Enable A/D converter. 0 Disable channel increment. 1 Enable channel increment. 0 Note: "x" bits = don't care. Disable convert-on-read at EOS. 1 Enable convert-on-read at EOS. 0 Disable fast throughput mode. 1 Enable fast throughput mode (hold off DTACK* until EOC = 1). 0 Disable calibration mode (except external inputs). 1 Enable calibration mode (local reference channel). 0 Disable EOS and EOC interrupts. 1 Enable EOC and EOS interrupts. Figure 2. DVME-611/612 DVME-611/612 Command Register Format (WRITE) Location: Base +128 (Word address) 15 14 13 12 11 10 9 x x x x 8 x 7 6 5 4 3 x x 2 1 0 x 0 0 Conversion begins when the host system writes to the Start Conversion register. 0 1 Conversion begins when the host system writes to the Start Conversion register or on an A/D read operation. 1 0 Conversion begins on an external trigger. 1 1 Conversion begins on external trigger or A/D data read. 0 Disable A/D converter. 1 Enable A/D converter. 0 Disable calibration mode (except external inputs). 1 Enable calibration mode (local reference channel). 0 Disable interrupts. 1 Enable interrupts. 0 EOS flag is reset. 1 EOS set at EOC. 0 Current < > final channel. 1 Current = final channel (comparator output). 0 Busy converting; data invalid. 1 End of A/D conversion, data ready. Note: "x" bits = don't care. Figure 3. DVME-611/612 DVME-611/612 Status Register Format (READ) DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 153 Email: sales@datel.com · Internet: www.datel.com ® ® DVME-611/612 DVME-611/612 Interrupt ID Register Word address: Base +138 This register contains the user-loaded interrupt ID number. On receiving the interrupt request, the host system tests the interrupt level using address lines A01 through A03. The host system must then acknowledge using the IACK* and the daisy chain IACKIN* signal lines. If the DVME-611/612 DVME-611/612 interrupt level matches the level code on the address lines, the interrupt logic loads the interrupt ID number on to the VMEbus (low byte). If the EOC/EOS interrupts and the multiple channel scan option are enabled, the board loads the ID number plus one on to the VMEbus data lines. The host system may use these ID's to differentiate the EOC and EOS interrupts. Figure 4 shows the register format of the interrupt ID register. Word address: Base +130 (Write) 8 x x CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 x x x x x x 7 6 5 4 3 2 1 0 Figure 7. Final Channel Register Format Start Conversion Register Writing any value to this register starts an A/D conversion on the channel indicated by the current channel register. Figure 8 shows the format of this register. Word address: Base +140 (Write) 7 6 5 4 3 2 1 0 3 x x x x x x x x x x x ID7 ID6 ID5 ID4 ID3 ID2 ID1 0 x x x 4 8 8 x 5 15 14 13 12 11 10 9 x x 6 15 14 13 12 11 10 9 X = Don't care 15 14 13 12 11 10 9 x 7 (Write) 2 1 0 x x x x x x Figure 8. Start Conversion Register Format Figure 4. Interrupt ID Register Format A/D Data Register Gain Register and Digital Outputs The 16 bits of the A/D data register are connected to 16 VMEbus data lines. The host system may read this register to obtain the binary data of the analog input from the channel selected. Models DVME-611/612 DVME-611/612 A and B do not use the four least significant data bits. The value of these bits defaults to zero for these models. Figure 9 shows the format of this register. The least three significant bits of this register, when programmed, assign the gain to the differential amplifier in the PGA section. This register is programmable for gains from 1 to 128 in binary increments. Bits 6 and 7 of this register provide a general purpose digital output. The output signal lines from these two bits are available on pins 18 and 6 of the J4 connector. Figure 5 shows the gain register format. Word address: Base +140 Word address: Base +134 (Write) 8 5 4 3 x x GP1 GP0 x x x x x x x 6 2 1 0 8 7 6 5 4 3 2 1 0 x G2 G1 G0 x 7 15 14 13 12 11 10 9 15 14 13 12 11 10 9 (Read) AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 Figure 9. A/D Register Format Figure 5. Gain Register Format D/A Channel Registers Start Channel/Current Channel Register User must load this register with the starting channel address when scanning a group of channels. This register contains the address of the channel being scanned. Figure 6 shows the format of this register. The DVME-612 DVME-612 boards have two D/A channel registers. These registers form the input to the 12-bit hybrid D/A converters. These registers are programmable by the most significant 12 bits from the VMEbus data lines. Figure 10 shows the format of these registers. Word address: Base +136 Word address: Base +160 (Read/Write) 15 14 13 12 11 10 9 8 x x x x x x 6 5 4 3 2 1 15 14 13 12 11 10 9 0 Figure 6. Start Channel/Current Channel Register 3 2 1 0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 x x CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 x 7 (Write) 8 7 6 5 4 x x x Figure 10a. D/A Channel 0 Register Format Final Channel Register Word address: Base +162 User must load this register with the final channel address when scanning a group of channels. The on-board comparator compares this register contents with the current channel register and generates the end of scan (EOS) signal. Figure 7 shows the format of this register. 15 14 13 12 11 10 9 (Write) 3 2 1 0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 x 8 7 6 5 4 x x x Figure 10b. D/A Channel 1 Register Format DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 154 Email: sales@datel.com · Internet: www.datel.com ® ® DVME-611/612 DVME-611/612 EOC/EOS F/F Register Table 5. DVME-611/612 DVME-611/612 Analog Input Connector - J2 Writing any value to this register resets the EOC/EOS flipflops. Figure 11 shows the format of this register. Pin # Configuration Single-Ended Differential 24 12 25 CHANNEL 8 CHANNEL 24 ANALOG RETURN CHANNEL 8 HIGH CHANNEL 8 LOW ANALOG RETURN 10 23 11 CHANNEL 9 CHANNEL 25 ANALOG RETURN CHANNEL 9 HIGH CHANNEL 9 LOW ANALOG RETURN (These F/F's are also reset by the next start of conversion or by reading A/D data.) 21 9 22 CHANNEL 10 CHANNEL 26 ANALOG RETURN CHANNEL 10 HIGH CHANNEL 10 LOW ANALOG RETURN I/O Connections 7 20 8 CHANNEL 11 CHANNEL 27 ANALOG RETURN CHANNEL 11 HIGH CHANNEL 11 LOW ANALOG RETURN 18 6 19 CHANNEL 12 CHANNEL 28 ANALOG RETURN CHANNEL 12 HIGH CHANNEL 12 LOW ANALOG RETURN 4 17 5 CHANNEL 13 CHANNEL 29 ANALOG RETURN CHANNEL 13 HIGH CHANNEL 13 LOW ANALOG RETURN 15 3 16 CHANNEL 14 CHANNEL 30 ANALOG RETURN CHANNEL 14 HIGH CHANNEL 14 LOW ANALOG RETURN 1 14 2 CHANNEL 15 CHANNEL 31 ANALOG RETURN CHANNEL 15 HIGH CHANNEL 15 LOW ANALOG RETURN Word address: Base +132 (Write) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x Figure 11. EOC/EOS F/F Register Format The DVME-611/612 DVME-611/612 A/D boards use the J1 and J2 connectors for analog input connections and the J4 connector for channel expansion. The DVME-612 DVME-612 uses the J3 connector for analog output connections. The following tables list the I/O signals of the J1, J2, J3, and J4 connector respectively. Table 3. DVME-611/612 DVME-611/612 Analog Input Connector - J1 Configuration Pin # Single-Ended Differential 24 12 25 CHANNEL 0 IN CHANNEL 16 IN ANALOG RETURN CHANNEL 0 HIGH CHANNEL 0 LOW ANALOG RETURN 10 23 11 CHANNEL 1 IN CHANNEL 17 IN ANALOG RETURN CHANNEL 1 HIGH CHANNEL 1 LOW ANALOG RETURN 21 9 22 CHANNEL 2 IN CHANNEL 18 IN ANALOG RETURN CHANNEL 2 HIGH CHANNEL 2 LOW ANALOG RETURN 7 20 8 CHANNEL 3 IN CHANNEL 19 IN ANALOG RETURN CHANNEL 3 HIGH CHANNEL 3 LOW ANALOG RETURN 18 6 19 CHANNEL 4 IN CHANNEL 20 IN ANALOG RETURN CHANNEL 4 HIGH CHANNEL 4 LOW ANALOG RETURN 4 17 5 CHANNEL 5 IN CHANNEL 21 IN ANALOG RETURN CHANNEL 5 HIGH CHANNEL 5 LOW ANALOG RETURN 15 3 16 CHANNEL 6 IN CHANNEL 22 IN ANALOG RETURN CHANNEL 6 HIGH CHANNEL 6 LOW ANALOG RETURN 1 14 2 CHANNEL 7 IN CHANNEL 23 IN ANALOG RETURN CHANNEL 7 HIGH CHANNEL 7 LOW ANALOG RETURN Table 6. DVME-611/612 DVME-611/612 Expansion Connector - J4 Pin # 13 25 12 24 11 23 10 22 16 9 8 20 7 19 17 18 6 4 21 5 1 14 2,15 3 Table 4. DVME-612 DVME-612 Analog Output Connector - J3 Pin # 1 6 4 9 Signal Line CHANNEL 0 VOUT ANALOG RETURN CHANNEL 1 VOUT ANALOG RETURN Signal Line EXTERNAL CHANNEL ADDRESS 0 OUT EXTERNAL CHANNEL ADDRESS 1 OUT EXTERNAL CHANNEL ADDRESS 2 OUT EXTERNAL CHANNEL ADDRESS 3 OUT EXTERNAL CHANNEL ADDRESS 4 OUT EXTERNAL CHANNEL ADDRESS 5 OUT EXTERNAL CHANNEL ADDRESS 6 OUT EXTERNAL CHANNEL ADDRESS 7 OUT DIGITAL GROUND EXTERNAL CHANNEL ADDRESS VALID OUT START CONVERSION STROBE OUT SETTLING DELAY* IN END OF CONVERSION OUT END OF SCAN OUT EXTERNAL TRIGGER IN* GENERAL PURPOSE OUTPUT 0 GENERAL PURPOSE OUTPUT 1 DIGITAL GROUND RESERVED RESERVED EXTERNAL ANALOG LOW IN EXTERNAL ANALOG HIGH IN ANALOG COMMON +5V dc REFERENCE OUT (5mA) DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 155 Email: sales@datel.com · Internet: www.datel.com ® ® DVME-611/612 DVME-611/612 DVME-611/612 DVME-611/612 Board Identification Code Byte Address Base + 1 +3 +5 +7 +9 + 0B + 0D + 0F + + + + + + + + 11 13 15 17 19 1B 1D 1F DATEL VMEbus Short I/O Memory Organization ASCII Code Function V M E I D Identifier This ASCII code is present for all DATEL VMEbus boards D A T d V M E - 6 1 1 or 2 Base Address Board Model Number Function Base + 0 through Base + 63 ALL DATEL VMEbus boards Manufacturer's and Board's identification code Manufacturer ID DAT is the ID for DATEL Base + 64 through Base + 77 DVME-660 DVME-660 48 line digital I/O board Board model number Base + 78 through Not used Base + 127 Base + 128 DVME-611 DVME-611 through DVME-612 DVME-612 Base + 143 DVME-612 DVME-612: 32 single-ended; 16 differential channel A/D board with 2 D/A channels Base + 144 DVME-602 DVME-602 through Base + 151 Ordering Information A - 12-bit/20 µS ADC B - 12-bit/4 µS ADC C - 16-bit/35 µS ADC D - 16-bit/400 mS E - 12-bit/2 µS ADC F - 14-bit/4 µS DVME-611 DVME-611 (A/D only) DVME-612 DVME-612 (A/D + D/A) Base + 160 DVME-612 DVME-612 through DVME-624 DVME-624 Base + 175 DVME-628 DVME-628 DVME-641 DVME-641 - 32S/16D 32S/16D Channel high-level non-isolated inputs. Accessories DVME-C-02 DVME-C-02 DVME-612 DVME-612: 32 single-ended/ 16 differential channel A/D board with 2 D/A channels DVME-624 DVME-624: 4-channel isolated D/A board DVME-643 DVME-643 - 8D Channel isolated inputs. DVME-C-01 DVME-C-01 DVME-602 DVME-602: 4-channel isolated board for measuring thermocouples, RTD's, strain gages, high-level, low-level, and 4-to-20 mA current loop inputs Base + 152 through Not used Base + 159 Optional Multiplexer Expansion Boards Part Number DVME-611 DVME-611: 32 single-ended/ 16 differential channel A/D board Base + 176 through Not used Base + 191 Description Two-connector expansion cable (for use with one multiplexer) Base + 192 through Not used Base + 255 Three-connector expansion cable (for use with two multiplexer boards) Contact DATEL for unipolar models 611/612C-U 611/612C-U under special order. Each board includes a disk and manual. DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · 156 Email: sales@datel.com · Internet: www.datel.com