DV2005L1 RL0703-5744-103-S1 197-103LA6-A01 R14/R18 1N5400 1000UF 1N4148 - Datasheet Archive

 

Fast Charge Development System Control of PNP Power Transistor Features bq2005 fast-charge control evaluation and development

 

DV2005L1 DV2005L1 Fast Charge Development System Control of PNP Power Transistor Features bq2005 fast-charge control evaluation and development Charge current sourced from two on-board frequency-modulated linear regulators (up to 3.0 A) Fast charge control and conditioning for one or two NiMH and/or NiCd batteries containing 4 to 10 NiCd or NiMH cells; user-configurable for applications that use other numbers of cells Sequential charging of two battery packs Fast-charge termination by delta temperature/delta time (T/t), negative delta voltage (-V), maximum temperature, maximum time, and maximum voltage -V enable, hold-off, top-off,trickle rate, maximum charge time, and number of cells are jumper-configurable Charging status displayed on LEDs (two for each battery) Discharge-before-charge control with push-button switch for battery A Selectable pulsed "top-off" charge and trickle charge General Description Connection Descriptions The DV2005L1 DV2005L1 Linear Development System provides a development environment for the bq2005 Dual-Battery Fast-Charge IC. The DV2005L1 DV2005L1 incorporates a bq2005 and two frequency-modulated linear regulators to provide fast charge control for 4 to 10 NiCd or NiMH cells. J1 DC GND Ground from charger supply TSA,B Thermistor connection, battery A and B BATA,B Positive battery terminal and high side of discharge load, battery A and B SNSA,B tor Review the bq2005 data sheet and the application note, "Using the bq2005 to Control Fast Charge," before using the DV2005L1 DV2005L1 board. DC input from charger supply Negative battery terminal and thermis- J2 The fast charge is terminated by any of the following: T/t, -V, maximum temperature, maximum time, and maximum voltage. Jumper settings select the -V enabled state, and the hold-off, top-off, trickle, and maximum time limits. connection, battery A and B The user provides a power supply and batteries. The user configures the DV2005L1 DV2005L1 for the number of cells, charge termination, and maximum charge time (with or without top-off), and commands the discharge-beforecharge option with the push-button switch SW1. J3 DISLOAD Discharge load JP1 DVEN JP2 TM1 3/98 Negative delta voltage termination enable TM1 setting Rev. A Board 1 DV2005L1 DV2005L1 Identifier Thermistor Select number of cells, battery A K1 Keystone RL0703-5744-103-S1 RL0703-5744-103-S1 JP5 Select number of cells, battery B (blank) Philips 2322-640-63103 JP6 Automatic discharge select F1 Fenwal Type 16, 197-103LA6-A01 197-103LA6-A01 JP3 TM2 TM2 setting JP4 Fixed Configuration The DV2005L1 DV2005L1 board has the following fixed characteristics: Jumper-Selectable Configuration VCC (4.75­5.25V) is regulated on-board from the supply at connector J1 (DC:GND). The DV2005L1 DV2005L1 must be configured as described below. LEDs indicate charge status of both battery A and battery B. Jumper Setting Disabled (low) DVEN (JP1): Enables/disables -V termination (see bq2005 data sheet). Pin DCMDA is connected to switch SW1. A toggle of switch SW1 momentarily pulls DCMDA to GND and initiates a discharge-before-charge. Automatic dischargebefore-charge can also be achieved by connecting DCMDA directly to GND at JP6. The bq2005 output activates FET Q1, allowing current to flow through an external current-limiting load between battery A and SNSA at J3 (DISLOAD). Jumper Setting Pin State [12]3 High 1[23] Low 123 As shipped from Benchmarq, the DV2005L1 DV2005L1 linear regulators are configured to a charging current of 1.13A. This current level is controlled by the value of sense resistors RSA and RSB by the relationship: I CHG = Enabled (high) 1[23] Charge initiation is provided on application of DC, which provides VCC to the bq2005, or on installation of the battery following power application. Pin State [12]3 Float TM1 and TM2 (JP2 and JP3): Select fast charge safety time/hold-off/top-off (see bq2005 data sheet). Number of Cells (JP4/JP5): A resistor-divider network is provided to select 4 to 10 cells (the resulting resistor value equals N 2 .375 ­ 1 cells). RBA1 and RBB1 are 150K resistors, and RBA2 and RBB2 (R21­R26) are jumper-selected. 0.225V RSA, B The value of RSA and RSB at shipment is 0.200. This resistor can be changed depending on the application. Closed Jumper 10 24 8 23 6 22 5 21 Resistors R14/R18 R14/R18 should be selected to divert power dissipation from transistors Q2 and Q4. They are shipped at values of 100 1 2W. Select appropriate values based on voltage source and fast charge current from Table 1. user-defined 25 The suggested maximum ICHG for the DV2005L1 DV2005L1 board is 3A for each battery due to the power-dissipation limits of Q2 and Q4. Q3 and Q5 must be mounted to an appropriate heat sink. Number of Cells RBA/RBB 26 4 Temperature Disable: Connecting a 10K resistor between TSA,B and SNSA,B disables temperature control. With the provided NTC thermistor connected between TSA,B and SNSA,B, values are: LTF = 10°C, HTF = 49°C, and TCO = 50°C. The T/t settings at 30°C (TT) are: minimum = 0.82°C/minute, typical = 1.10°C/minute. The thermistor is identified by the serial number suffix on the board as follows: Rev. A Board 2 DV2005L1 DV2005L1 Table 1. Lookup Table for R14/R18 R14/R18 Selection Input Voltage 1. 1 2A 100 1 62 360 1 2A 150 87.5 510 1 2A 200 2W 3A 120 5W 1A 680 1W 2A 240 3W 3A Wattage W 2 W Note: RTA1,B1 and RTA2,B2 match the thermistor provided and must be changed if a different thermistor type is used (see Appendix A in the application note, "Using the bq2005 to Control Fast Charge"). 2 3W W 2 3. 4. Attach the battery pack (+) to BATA,B and (­) to SNSA,B. For temperature control, the thermistor must contact the cells. 5. W 2 If using the discharge-before-charge option, connect a current-limiting discharge load between DIS and LOAD. Attach DC current source to DC+ (+) and GND (­) connections in J1. Not recommended 1.5A 30­35V Connect the provided thermistor or a 10K resistor between TSA,B and SNSA,B. 5W 1A Configure DVEN, TM1, TM2, and number-of-cells jumpers. 2. 2W 3A 25­30V 100 1A 20­25V Resistance 3A 15­20V Current 1A to 15V Setup Procedure 910 1W 2A Not recommended 3A Not recommended Note: Capacitors C2 and C3 must be changed from those shipped with the board for input voltage in excess of 25V. Recommended DC Operating Conditions Symbol Description Minimum Typical Maximum Unit - - 3 A IDC+ Maximum input current VDC+ Input voltage VBATA/B BAT+ input voltage - - 30 V VTHERM TSA,B input voltage 0 - 5 V IDSCHG Discharge load current - - 2 Notes A Note: 2.0 + VBAT+ or 8.5 18 + VBAT+ V or 35 - Note 1 1. The voltage at R14/R18 R14/R18 is application-specific and limits the dissipation of Q2/Q4 to a safe limit during Q3/Q5 conduction. See Table 1 for recommended R14, R18 selections per VDC+ and ICHARGE. Rev. A Board 3 DV2005L1 DV2005L1 DV2005L1 DV2005L1 Board Schematic D1 1N5400 1N5400 C1 1000UF 1000UF 35V OPTIONAL C2 1000UF 1000UF 35V VCC U2 2 1 DC GND D2 1N4148 1N4148 J1 78L05ACZ 78L05ACZ R16 BATB VCC IN OUT GND GREEN JP1 DVEN 1 2 3 JP2 TM1 1 2 3 JP3 TM2 RED D6 C5 100UF 100UF 6.3V VCC C3 100UF 100UF 25V D5 GREEN D4 2K Q5 RED TIP42 TIP42 D3 R19 SW1 R12 2K JP6 1 2 3 DISCHARGE VCC AUTO_DIS R5 73.2K 1% R2 1M R1 VCC R9 2K R8 1K DCMDA FCCB DVEN CHB TM1 MODB TM2 MODA TCO VCC TSA VSS TSB FCCA BATA CHA BATB DISA SNSA SNSB TIP42 TIP42 R15 R17 2K 20 19 18 17 16 15 14 13 12 11 BATA 2K Q3 R18 100 1/2W R7 2K 0.1UF U1 1 2 3 4 5 6 7 8 9 10 1M R4 C4 R10 1K Q4 2N3904 2N3904 2K R14 100 1/2W C12 0.1UF R13 2N3904 2N3904 Q2 2K BQ2005 BQ2005 C10 0.1UF 1M R3 C11 0.1UF R6 27.4K 1% J3 1M C7 0.1UF C9 0.1UF C6 0.1UF C8 0.1UF 1 2 LOAD R11 2K Q1 MTP3055VL MTP3055VL SNSA SNSB BBAT ABAT TSB TSA DV2005L1 DV2005L1, Rev A, 5-12-97, Sheet 1 of 2 Rev. A Board 4 DV2005L1 DV2005L1 DV2005L1 DV2005L1 Board Schematic Continued BATA RBA1 150K 1% ABAT VCC JP4 TSA SNSA A NUMBER OF CELLS RTA1 4.53K 1% RTA2 3.57K 1% 4 RBA21 RBA21 221K 1% 5 RBA22 RBA22 137K 1% 6 RBA23 RBA23 97.6K 1% 8 RBA24 RBA24 63.4K 1% 10 RBA25 RBA25 46.4K 1% RBA26 RBA26 USER_DEF. 1% BATA BATB SNSA TSA RSA 0.2 1% RBB1 150K 1% BBAT VCC BATB SNSB TSB 6 5 4 3 2 1 J2 JP5 TSB SNSB B NUMBER OF CELLS RTB1 4.53K 1% RTB2 3.57K 1% 4 RBB21 RBB21 221K 1% 5 RBB22 RBB22 137K 1% 6 RBB23 RBB23 97.6K 1% 8 RBB24 RBB24 63.4K 1% 10 RBB25 RBB25 46.4K 1% RBB26 RBB26 USER_DEF. 1% RSB 0.2 1% DV2005L1 DV2005L1, Rev A, 5-12-97, Sheet 2 of 2 Rev. A Board 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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