DSP56364 1J25D 364CE1J25D DSP56300 DSP56302 DSP56309 DSP56303 DSP56304 DSP56362 - Datasheet Archive

 

DSP56364 Digital Signal Processor Mask: 1J25D General remark: In order to prevent the use of instructions or sequences of

 

Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask: 1J25D 1J25D General remark: In order to prevent the use of instructions or sequences of instructions that do not operate correctly, we encourage you to use the "lint563" program to identify such cases and use alternative sequences of instructions. This program is available as part of the Motorola DSP Tools CLAS package. Silicon Errata Errata Number Applies to Mask Errata Description Description (added 5/28/98): ES42 1J25D 1J25D When a Direct Memory Access (DMA) channel is in Line mode (i.e., the DMA Transfer Mode is DTM = 010) with address modes defined by DMA Three Dimensional mode D3D = 0 and DMA = 10010x (i.e., the DMA Counter (DCO) is in mode A), and the DCO value is greater than $FFF, then the DMA does not function properly. This address mode implies "no update" at the destination and "no update" or "post increment by 1" mode at the source. Workaround: Use Block Transfer mode (i.e., DTM = 000). For the DCO and DMA Address Mode (DAM) settings described in this erratum, the Line Transfer mode of DMA is identical to its Block Transfer mode, so this combination is redundant. In fact, a block containing only one line is still a block. Motorola, SPS, Wireless Division 364CE1J25D 364CE1J25D_1_3 6501 William Cannon Drive West, Austin, Texas 78735-8598 NG 4/13/00 pg. 1 of 24 © 1997 - 2000 Motorola Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description Description (added 10/13/1997): 1J25D 1J25D Using the JTAG instruction code 1111 ($F) or 1101 ($D) for the BYPASS instruction may cause the chip to enter Debug mode (which then correctly sets the Status bits (OS[1:0]) in the OnCE Status and Control Register (OSCR[7:6]) and asserts the DE output to acknowledge the Debug mode status). Workaround: Use one of the following alternatives: ES53 a. If possible, do not use instruction code 1111 ($F) or 1101 ($D) for the BYPASS instruction. Use one of the other defined BYPASS instruction codes (i.e., any code from 1000­1100 ($8­$C) or 1110 ($E). b. If you must use instruction code 1111 ($F) or 1101 ($D), use the following procedure: - While the $F or $D instruction code is in the Instruction Register, ensure that the JTAG Test Access Port (TAP) state machine does not pass through the JTAG Test-Logic-Reset state while accessing any JTAG registers (i.e., Instruction Register, Boundary Scan Register, or ID Register). - Before using any other JTAG instruction, load one of the other BYPASS instruction codes (i.e., any code from 1000­1100 ($8­$C) or 1110 ($E) into the instruction register. Then, any other JTAG instruction may be used. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 2 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description Description (added 1/27/98): 1J25D 1J25D When a DMA channel is configured using its DMA Control Register (DCR) in the following manner: ES54 · Line Transfer mode is selected (DTM[2:0] = 010) · Non-Three-Dimensional Address mode is selected (D3D = 0) · Destination Address Offset Register DOR1 or DOR3 is selected (DAM[5:3] = 001 or 011) · No Source Address Offset is selected (DAM[2:0] = 100 or 101) The DMA transfer does not function as intended. Workaround: Select Destination Address Offset Register DOR0 or DOR2 by setting DAM[5:3] = 000 or 010. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 3 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description Description (added 5/13/98): 1J25D 1J25D When software disables a DMA channel (by clearing the DE bit of the DCR) , the DTD status bit of the channel may not be set if any of the following events occur: a. Software disables the DMA channel just before a conditional transfer stall (Described by App B-3.5.1,UM). b. Software disables the DMA channel at the end of the block transfer (that is after the counter is loaded with its initial value and transfer of the last word of the block is completed). As a result, the Transfer Done interrupt might not be generated. Workaround: Avoid using the instruction sequence causing the conditional transfer stall (See DSP56300 DSP56300 UM, App B-3.5.1 for description) in fast interrupt service routines. Every time the DMA channel needs to be disabled by software, the following sequence must be used : ES84 bclr #DIE,x:M_DCR ; not needed if DIE is cleared bclr #DE,x:M_DCR ; instead of two instructions above, one 'movep' instruction may be used ; to clear DIE and DE bits movep #DCR_Dummy_Value,x:M_DCR bclr #DE,x:M_DCR nop nop Here, the DCR_Dummy_value is any value of the DCR register that complies with the following requirements: · · · DE is set; DIE is set if Transfer Done interrupt request should be generated and cleared otherwise; DRS[4:0] bits must encode a reserved DMA request source (see the following list of reserved DRS values); List of reserved DRS[4:0] values (per device): · DSP56302 DSP56302, DSP56309 DSP56309, DSP56303 DSP56303, DSP56304 DSP56304, DSP56362 DSP56362 - 10101-11111 · · · DSP56364 DSP56364 Errata © 1997 - 2000, Motorola DSP56305 DSP56305 - 11011 DSP56301 DSP56301 - 10011-11011 DSP56307 DSP56307 - 10111-11111 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 4 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description Description (added 7/21/98): ES92 1J25D 1J25D Due to a circuit race in the DMA block, enabling any DMA channel by software (by setting DE) for transferring a block of data (TM=011) might not work properly. Workaround: This mode of a channel trigger by software can be exactly emulated by enabling the DMA channel for block transfer triggered by a peripheral request (TM=000). Description (added 8/15/98): ES95 1J25D 1J25D If more than a single DMA channel is enabled while the DSP stays in the WAIT processing state, and triggering one of the DMA channels causes an exit from the WAIT state (See A-6.115, UM), triggering another DMA channel might cause improper DMA operation. Workaround: Assure that only a single DMA channel can be triggered during DSP WAIT state. If the application cannot guarantee this, other DMA channels should be disabled before the WAIT processing state is entered and then reenabled after WAIT state is exited. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 5 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description Description (added 11/20/98): 1J25D 1J25D An improper operation may occur when a DMA channel uses the following transfer modes: · DTM(2:0) = 100 · DTM(2:0) = 101 where the DE bit is not automatically cleared at the end of block and the DMA channel is disabled by software (DE bit is cleared) while it is triggered for a new transfer. ES104 ES104 Workaround: The DMA channel should be disabled only when it cannot be triggered by a new transfer. Use one of the following alternatives: 1. The system configuration must guarantee that no DMA trigger can occur while the DE bit is cleared. 2.The following sequence disables the DMA channel: a/ b/ c/ Wait until the DTD bit is cleared Clear the DE bit Wait until the DTD bit is set Description (added 4/19/99, revised 4/30/99): ES114 ES114 1J25D 1J25D A DMA channel may operate improperly when the address mode of this channel is defined as three-dimensional (D3D=1) and DAM[5:0] = 1xx 1 10 or DAM[5:0] = 01xx 10 (i.e., triple counter mode is E). Workaround: Use the triple counter modes C(DAM[1:0]=00) or D(DAM[1:0]=01) instead of the E(DAM[1:0]=10) mode. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 6 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description Description (added 4/19/99): 1J25D 1J25D When a DMA channel (called channel A) is disabled by software clearing the channel's DCR[DE] bit, the DTD bit may not get set, and the DMA end of the block interrupt may not happen if one of the following occurs: 1. There is another channel (channel B) executing EXTERNAL accesses, and the DE bit of channel A is being cleared by software at the end of the channel B word transfer - if channel B is in Word transfer mode, or at the end of the channel B line transfer - if channel B is in Line Transfer mode, or at the end of the channel B block transfer - if channel B is in Block transfer mode. ES115 ES115 2. This channel (A) is executing EXTERNAL accesses, and the DE bit of this channel (A) is being cleared by software at the end of the channel B word transfer - if channel B is in Word transfer mode, or at the end of the channel B line transfer - if channel B is in Line transfer mode. Workaround: Avoid executing a DMA external access when any DMA channel should be disabled. This can be done as follows. Every time the DMA channel needs to be disabled by software, the following sequence must be used: ; initialize an unused DMA channel "C" movep #DSR_swflag, x:M_DSRC ; here DSR_swflag is an ; unused X, Y or P memory ; location, should ; be initialized to ; $800000 ; M_DSRC - address of the ; channel C DSR register. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 7 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description movep #DDR_swflag, x:M_DDRC movep ES115 ES115 cont. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola DDR_swflag is an unused X, Y or P memory location, should be initialized to $000000 M_DDRC address of the channel C DDR register . 1J25D 1J25D #TR_LENGTH, x:M_DCOC register .movep ; ; ; ; ; ; ; ; see below the definition ; of the TR_LENGTH value, ; M_DCOC - address ; of the channel C DCO #1f0240, x:M_DCRC ; M_DCRB - address of the ; channel C DCR register. ; Set transfer mode ; block transfer, ; triggered by ; software highest ; priority, continuous ; mode on no-update ; source and destination ; address mode X memory ; location for source ; and destination (can be ; chosen by ; user accordingly to ; DSR_swflag/DDR_swflag) 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 8 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description 1J25D 1J25D ; disable DMA channel "A" ori bset bclr ES115 ES115 cont. bclr nop nop jclr #3, mr ; mask all interrupts #23, x:M_DCRC ; enable DMA channel C #23,x:DDR_swflag,* ; wait until DMA channel C ; begin transfer #23, x:M_DCRA #M_DTDA, x:M_DSTR,* ; disable DMA channel A ; polling DTD bit of the DMA ; channel A, The TR_LENGTH value can be defined as the maximum length of the external DMA transfer-from the length of the read DMA cycle and from the length of the write DMA cycle. The length of the external read/write DMA cycle can be defined as the length of the PORTA external access. The length of the internal read/write DMA cycle can be defined in the errata case as 2 DSP clock cycles. The TR_LENGTH can be found as sum of the lengths of the DMA read and DMA write cycles. Description (added 11/17/99): 1J25D 1J25D When the core and the DMA are simultaneously accessing the same ROM memory module, the contention is not detected and the DMA transfers erroneous data. Workaround: ES126 ES126 The programmer must ensure that the core and DMA never access the same ROM memory module simultaneously. The 56364 has three ROM memory modules in the program space: 4K module - from $FF1000 FF1000 to $FF1FFF 2K module - from $FF2000 FF2000 to $FF27FF FF27FF 2K module - from $FF2800 FF2800 to $FF2FFF DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 9 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Errata Number Applies to Mask Errata Description Description (added 4/12/2000) ES128 ES128 1J25D 1J25D When the ESAI is operating in the asynchronous mode (SYN=0) and both SCKR and SCKT bit clock signals are defined as inputs from an external clock source (TCKD=0 in the TCCR register and RCKD=0 in the RCCR register), the internal clock dividers will be disabled. The result is that the HCKT and HCKR signals will not operate as ouputs even if so defined in the control register. If the ESAI is operating in the synchronous mode (SYN=1), then the HCKT signal will be disabled when SCKT is defined as an input. Workaround: To enable the operation of HCKT and HCKR signals as outputs, at least one of the SCKR or SCKT signals must be defined as output. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 10 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Documentation Errata Applies to Mask Errata Description Description (revised 11/9/98): 1J25D 1J25D XY memory data move does not work properly under one of the following two situations: 1. The X-memory move destination is internal I/O and the Ymemory move source is a register used as destination in the previous adjacent move from non Y-memory 2. The Y-memory move destination is a register used as source in the next adjacent move to non Y-memory. Here are examples of the two cases (where x:(r1) is a peripheral): Example 1: ED1 move #$12,y0 move x0,x:(r7) y0,y:(r3) (while x:(r7) is a peripheral). Example 2: mac move x1,y0,a x1,x:(r1)+ y0,y1 y:(r6)+,y0 Any of the following alternatives can be used: a. Separate these two consecutive moves by any other instruction. b. Split XY Data Move to two moves. Pertains to: DSP56300 DSP56300 Family Manual, Section B-5 "Peripheral pipeline restrictions. Description (added 5/7/1996): ED3 1J25D 1J25D A one-word conditional branch instruction at LA-1 is not allowed. Pertains to: DSP56300 DSP56300 Family Manual, Appendix B, Section B.4.1.3 DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 11 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Applies to Mask Errata Description Description (added 10/13/1997): 1J25D 1J25D The following instructions should not start at address LA: ED4 MOVE to/from Program space {MOVEM, MOVEP (only the P space options)} This is a documentation update to the Appendix B, DSP56300 DSP56300 Family Manual. Description (added 1/27/98): ED7 1J25D 1J25D When activity passes from one DMA channel to another and the DMA interface accesses external memory (which requires one or more wait states), the DACT and DCH status bits in the DMA Status Register (DSTR) may indicate improper activity status for DMA Channel 0 (DACT = 1 and DCH[2:0] = 000). Workaround: None. Description (added 7/21/98): ED15 1J25D 1J25D The DRAM Control Register (DCR) should not be changed while refresh is enabled. If refresh is enabled only a write operation that disables refresh is allowed. Workaround: First disable refresh by clearing the BREN bit, than change other bits in the DCR register, and finally enable refresh by setting the BREN bit. DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 12 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Applies to Mask Errata Description Description (added 1/7/1997; identified as Documentation Errata 1J25D 1J25D 2/1/99): When two consecutive LAs have a conditional branch instruction at LA-1 of the internal loop, the part does not operate properly. For example, the following sequence may generate incorrect results: ED28 DO #5, LABEL1 NOP DO #4, LABEL2 NOP MOVE (R0) + BSCC _DEST internal loop NOP LABEL2 NOP LABEL1 NOP NOP _DEST NOP NOP RTS ; conditional branch at LA-1 of ; internal LA ; external LA Workaround: Put an additional NOP between LABEL2 and LABEL1. Pertains to: DSP56300 DSP56300 Family Manual, Appendix B, Section B-4.1.3, "At LA-1." DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 13 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Applies to Mask Errata Description Description (added 11/9/98; identified as a Documentation errata 1J25D 1J25D 2/1/99): When returning from a long interrupt (by RTI instruction), and the first instruction after the RTI is a move to a DALU register (A, B, X, Y), the move may not be correct, if the 16-bit arithmetic mode bit (bit 17 of SR) is changed due to the restoring of SR after RTI. ED32 Workaround: Replace the RTI with the following sequence: movec nop rti ssl,sr Pertains to: DSP56300 DSP56300 Family Manual. Add a new section to Appendix B that is entitled "Sixteen-Bit Compatibility Mode Restrictions." DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 14 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Applies to Mask Errata Description Description (added 12/16/98; identified as a Documentation errata 1J25D 1J25D 2/1/99): When Stack Extension mode is enabled, a use of the instructions BRKcc or ENDDO inside do loops might cause an improper operation. If the loop is non nested and has no nested loop inside it, the erratais relevant only if LA or LC values are being used outside the loop. Workaround: If Stack Extension is used, emulate the BRKcc or ENDDO as in the following examples. We split between two cases, finite loops and do forever loops. 1) Finite DO loops (i.e. not DO FOREVER loops) = BRKcc Original code: ED33 do #N,label1 . . do #M,label2 . . BRKcc . . label2 . . label1 Will be replaced by: do #N, label1 . . do #M, label2 . . Jcc fix_brk_routine . . DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 15 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Applies to Mask Errata Description nop_before_label2 nop label2 . . label1 . . 1J25D 1J25D ; This instruction must be NOP. fix_brk_routine move #1,lc jmp nop_before_label2 ENDDO -Original code: do #M,label1 . . do #N,label2 . . ENDDO . . ED33 cont. label2 . . label1 Will be replaced by: do #M, label1 . . do #N, label2 . . JMP fix_enddo_routine DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 16 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Applies to Mask Errata Description 1J25D 1J25D nop_after_jmp NOP ; This instruction must be NOP. . . label2 . . label1 . . fix_enddo_routine move #1,lc move #nop_after_jmp,la jmp nop_after_jmp ED33 cont. 2) DO FOREVER loops = BRKcc -Original code: do #M,label1 . . do forever,label2 . . BRKcc . . label2 . . label1 DSP56364 DSP56364 Errata © 1997 - 2000, Motorola 364CE1J25D 364CE1J25D_1_3 NG 4/13/00 pg. 17 of 24 Chip Errata DSP56364 DSP56364 Digital Signal Processor Mask:1J25D 1J25D Applies to Mask Errata Description Will be replaced by: 1J25D 1J25D do #M,label1 . . do forever,label2 . . JScc fix_brk_forever_routine note: JScc and not Jcc . . ED33 cont. nop_before_label2 nop label2 . . label1 . . ;