DSP56321 DSP56321RM/D DSP56300 10EFCOP DSP56300FM/AD DSP56321/D DSP56000 - Datasheet Archive

 

Freescale Semiconductor, Inc. DSP56321 Reference Manual 24-Bit Digital Signal Processor DSP56321RM/D Revision 0, August 2001 TM

 

Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. DSP56321 DSP56321 Reference Manual 24-Bit Digital Signal Processor DSP56321RM/D DSP56321RM/D Revision 0, August 2001 TM For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. OnCE, DigitalDNA, and the DigitalDNA LOGO are trademarks owned by Motorola, Inc. All other products or service names are the property of their respective owners. © Motorola, Inc. 2001 How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/ For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 Signals/Connections 2 Memory Configuration Freescale Semiconductor, Inc. Overview 3 Core Configuration 4 Clock Configuration 5 Programming the Peripherals 6 Host Interface (HI08) 7 Enhanced Synchronous Serial Interface (ESSI) 8 Serial Communications Interface (SCI) 9 Triple Timer Module 10 Enhanced Filter Coprocessor (EFCOP) 11 Bootstrap Program A Programming Reference B For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Overview 2 Signals/Connections 3 Freescale Semiconductor, Inc. 1 Memory Configuration 4 Core Configuration 5 Clock Configuration 6 Programming the Peripherals 7 Host Interface (HI08) 8 Enhanced Synchronous Serial Interface (ESSI) 9 Serial Communications Interface (SCI) 10 Triple Timer Module 11 Enhanced Filter Coprocessor (EFCOP) A Bootstrap Program B Programming Reference For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Contents Freescale Semiconductor, Inc. Chapter 1 Overview 1.1 Manual Organization . 1-2 1.2 Manual Conventions . 1-3 1.3 Features . 1-4 1.4 DSP56300 DSP56300 Core . 1-5 1.5 DSP56300 DSP56300 Core Functional Blocks . 1-5 1.5.1 Data ALU. 1-6 1.5.1.1 Data ALU Registers. 1-6 1.5.1.2 Multiplier-Accumulator (MAC) . 1-6 1.5.2 Address Generation Unit (AGU) . 1-7 1.5.3 Program Control Unit (PCU) . 1-7 1.5.4 Clock Generator Circuit. 1-8 1.5.5 JTAG TAP and OnCE Module . 1-9 1.5.6 On-Chip Memory. 1-9 1.5.7 Off-Chip Memory Expansion . 1-10 1.6 Internal Buses . 1-10 1.7 Block Diagram . 1-11 1.8 DMA . 1-12 1.9 Peripherals . 1-12 1.9.1 GPIO Functionality. 1-12 1.9.2 HI08 . 1-12 1.9.3 ESSI . 1-13 1.9.4 SCI . 1-13 1.9.5 Timer Module . 1-14 1.9.6 EFCOP . 1-14 Chapter 2 Signals/Connections 2.1 2.2 2.3 2.4 2.5 2.5.1 Power . 2-3 Ground . 2-3 Clock. 2-3 PLL . 2-4 External Memory Expansion Port (Port A) . 2-4 External Address Bus. 2-4 Contents For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. 2.5.2 2.5.3 2.6 2.7 2.8 2.9 2.10 2.11 2.12 External Data Bus . 2-4 External Bus Control . 2-5 Interrupt and Mode Control . 2-7 HI08 . 2-8 Enhanced Synchronous Serial Interface 0 . 2-11 Enhanced Synchronous Serial Interface 1 . 2-13 SCI . 2-15 Timers . 2-16 JTAG and OnCE Interface. 2-17 Freescale Semiconductor, Inc. Chapter 3 Memory Configuration 3.1 3.1.1 3.1.2 3.1.3 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.5 3.6 3.7 Program Memory Space . 3-1 Internal Program Memory . 3-2 Memory Switch Modes-Program Memory . 3-2 Program Bootstrap ROM . 3-2 X Data Memory Space. 3-2 Internal X Data Memory. 3-3 Memory Switch Modes-X Data Memory . 3-3 Internal X I/O Space . 3-3 Y Data Memory Space. 3-3 Internal Y Data Memory. 3-4 Memory Switch Modes-Y Data Memory . 3-4 Internal Y I/O Space . 3-4 External Y I/O Space . 3-4 Summary of Memory Switch Mode Configurations . 3-5 Dynamic Memory Configuration Switching . 3-5 Sixteen-Bit Compatibility Mode Configuration . 3-6 Memory Maps. 3-6 Chapter 4 Core Configuration 4.1 4.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.4.3 4.5 4.5.1 4.5.2 vi Operating Modes. 4-2 Bootstrap Program . 4-4 Central Processor Unit (CPU) Registers. 4-5 Status Register (SR). 4-5 Operating Mode Register (OMR) . 4-10 Configuring Interrupts . 4-14 Interrupt Priority Registers (IPRC and IPRP). 4-14 Interrupt Table Memory Map . 4-16 Processing Interrupt Source Priorities Within an IPL . 4-18 Bus Interface Unit (BIU) Registers . 4-19 Bus Control Register. 4-20 Address Attribute Registers (AAR[0­3]) . 4-22 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 4.6 4.7 4.8 4.9 DMA Control Registers 5­0 (DCR[5­0]) . 4-24 Device Identification Register (IDR). 4-30 JTAG Identification (ID) Register . 4-30 JTAG Boundary Scan Register (BSR). 4-30 Freescale Semiconductor, Inc. Chapter 5 Clock Configuration 5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.6 5.6.1 5.6.2 5.6.3 5.7 5.7.1 5.7.2 Overview. 5-1 Principal Clock Generation Scheme . 5-2 Clock Acronym List. 5-3 CLKGEN External Pins. 5-4 DPLL . 5-4 DPLL Block Diagram . 5-4 DPLL Description. 5-5 Clock Generator Output Stage . 5-6 EXTAL as Clock Source . 5-6 DPLL as Clock Source . 5-6 Global Clock Generator . 5-7 CLKGEN Programming Model. 5-7 DPLL Clock Control (PCTL) Register . 5-7 DPLL Static Control Register (DSCR). 5-9 Chapter 6 Programming the Peripherals 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 Peripheral Initialization Steps . 6-1 Mapping the Control Registers . 6-2 Reading Status Registers . 6-2 Data Transfer Methods . 6-3 Polling. 6-3 Interrupts . 6-3 DMA . 6-5 Advantages and Disadvantages . 6-6 General-Purpose Input/Output (GPIO) . 6-6 Port B Signals and Registers. 6-6 Port C Signals and Registers. 6-7 Port D Signals and Registers . 6-8 Port E Signals and Registers . 6-8 Triple Timer Signals and Registers . 6-8 Chapter 7 Host Interface (HI08) 7.1 7.1.1 Features . 7-1 DSP Core Interface . 7-1 Contents For More Information On This Product, Go to: www.freescale.com vii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 7.1.2 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.8 Host Processor Interface . 7-2 Host Port Signals . 7-3 Overview. 7-4 Operation . 7-6 Software Polling . 7-7 Core Interrupts and Host Commands. 7-8 Core DMA Access . 7-9 Host Requests . 7-10 Endian Modes . 7-11 Boot-up Using the HI08 Host Port . 7-12 DSP Core Programming Model . 7-13 Host Control Register (HCR) . 7-14 Host Status Register (HSR) . 7-15 Host Data Direction Register (HDDR) . 7-16 Host Data Register (HDR) . 7-16 Host Base Address Register (HBAR) . 7-17 Host Port Control Register (HPCR). 7-18 Host Transmit (HTX) Register . 7-21 Host Receive (HRX) Register. 7-22 DSP-Side Registers After Reset . 7-22 Host Programmer Model . 7-23 Interface Control Register (ICR) . 7-24 Command Vector Register (CVR). 7-27 Interface Status Register (ISR) . 7-28 Interrupt Vector Register (IVR). 7-30 Receive Data Registers (RXH:RXM:RXL). 7-30 Transmit Data Registers (TXH:TXM:TXL). 7-31 Host-Side Registers After Reset . 7-32 Programming Model Quick Reference . 7-33 Chapter 8 Enhanced Synchronous Serial Interface (ESSI) 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.3.1 8.3.2 8.3.3 8.4 viii ESSI Enhancements . 8-2 ESSI Data and Control Signals . 8-3 Serial Transmit Data Signal (STD). 8-3 Serial Receive Data Signal (SRD) . 8-3 Serial Clock (SCK) . 8-3 Serial Control Signal (SC0) . 8-4 Serial Control Signal (SC1) . 8-4 Serial Control Signal (SC2) . 8-6 Operation . 8-6 ESSI After Reset . 8-6 Initialization . 8-6 Exceptions. 8-7 Operating Modes: Normal, Network, and On-Demand. 8-10 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.9 8.5.10 8.6 8.6.1 8.6.2 8.6.3 Normal/Network/On-Demand Mode Selection . 8-10 Synchronous/Asynchronous Operating Modes . 8-11 Frame Sync Selection . 8-11 Frame Sync Signal Format . 8-11 Frame Sync Length for Multiple Devices. 8-12 Word Length Frame Sync and Data Word Timing. 8-12 Frame Sync Polarity. 8-12 Byte Format (LSB/MSB) for the Transmitter. 8-13 Flags. 8-13 ESSI Programming Model. 8-14 ESSI Control Register A (CRA) . 8-14 ESSI Control Register B (CRB) . 8-18 ESSI Status Register (SSISR). 8-28 ESSI Receive Shift Register . 8-29 ESSI Receive Data Register (RX) . 8-30 ESSI Transmit Shift Registers . 8-30 ESSI Transmit Data Registers (TX[2­0]). 8-33 ESSI Time Slot Register (TSR) . 8-33 Transmit Slot Mask Registers (TSMA, TSMB) . 8-33 Receive Slot Mask Registers (RSMA, RSMB) . 8-35 GPIO Signals and Registers. 8-36 Port Control Registers (PCRC and PCRD). 8-36 Port Direction Registers (PRRC and PRRD). 8-37 Port Data Registers (PDRC and PDRD). 8-38 Chapter 9 Serial Communication Interface (SCI) 9.1 Operating Modes. 9-1 9.1.1 Synchronous Mode . 9-2 9.1.2 Asynchronous Mode . 9-2 9.1.3 Multidrop Mode . 9-3 9.1.3.1 Transmitting Data and Address Characters . 9-3 9.1.3.2 Wired-OR Mode . 9-3 9.1.3.3 Idle Line Wakeup. 9-3 9.1.3.4 Address Mode Wakeup. 9-4 9.2 I/O Signals . 9-4 9.2.1 Receive Data (RXD) . 9-4 9.2.2 Transmit Data (TXD). 9-4 9.2.3 SCI Serial Clock (SCLK) . 9-4 9.3 SCI After Reset . 9-5 9.4 SCI Initialization. 9-7 9.4.1 Preamble, Break, and Data Transmission Priority. 9-8 9.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A). 9-8 9.5 Exceptions. 9-9 9.6 SCI Programming Model. 9-10 Contents For More Information On This Product, Go to: www.freescale.com ix Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 9.6.1 SCI Control Register (SCR) . 9-13 9.6.2 SCI Status Register (SSR) . 9-18 9.6.3 SCI Clock Control Register (SCCR) . 9-20 9.6.4 SCI Data Registers. 9-23 9.6.4.1 SCI Receive Register (SRX). 9-23 9.6.4.2 SCI Transmit Register (STX) . 9-24 9.7 GPIO Signals and Registers. 9-25 9.7.1 Port E Control Register (PCRE) . 9-25 9.7.2 Port E Direction Register (PRRE) . 9-26 9.7.3 Port E Data Register (PDRE). 9-26 Chapter 10 Triple Timer Module 10.1 Overview. 10-1 10.1.1 Triple Timer Module Block Diagram . 10-2 10.1.2 Individual Timer Block Diagram. 10-2 10.2 Operation . 10-3 10.2.1 Timer After Reset . 10-3 10.2.2 Timer Initialization . 10-4 10.2.3 Timer Exceptions . 10-4 10.3 Operating Modes. 10-5 10.3.1 Triple Timer Modes . 10-6 10.3.1.1 Timer GPIO (Mode 0) . 10-6 10.3.1.2 Timer Pulse (Mode 1) . 10-8 10.3.1.3 Timer Toggle (Mode 2) . 10-10 10.3.1.4 Timer Event Counter (Mode 3) . 10-12 10.3.2 Signal Measurement Modes. 10-14 10.3.2.1 Measurement Input Width (Mode 4) . 10-14 10.3.2.2 Measurement Input Period (Mode 5). 10-16 10.3.2.3 Measurement Capture (Mode 6) . 10-18 10.3.3 Pulse Width Modulation (PWM, Mode 7). 10-19 10.3.4 Watchdog Modes . 10-22 10.3.4.1 Watchdog Pulse (Mode 9) . 10-22 10.3.4.2 Watchdog Toggle (Mode 10). 10-24 10.3.4.3 Reserved Modes. 10-25 10.3.5 Special Cases . 10-25 10.3.6 DMA Trigger . 10-25 10.4 Triple Timer Module Programming Model . 10-25 10.4.1 Prescaler Counter . 10-25 10.4.2 Timer Prescaler Load Register (TPLR) . 10-27 10.4.3 Timer Prescaler Count Register (TPCR) . 10-28 10.4.4 Timer Control/Status Register (TCSR). 10-28 10.4.5 Timer Load Register (TLR) . 10-33 10.4.6 Timer Compare Register (TCPR) . 10-34 10.4.7 Timer Count Register (TCR) . 10-34 x DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Chapter 11 Enhanced Filter Coprocessor (EFCOP) 11.1 Features . 11-2 11.2 Architecture Overview. 11-3 11.2.1 PMB Interface. 11-4 11.2.2 EFCOP Memory Banks . 11-4 11.2.3 Filter Multiplier and Accumulator (FMAC) . 11-6 11.3 EFCOP Operation . 11-6 11.3.1 EFCOP Operation Summary . 11-7 11.3.2 EFCOP Initialization. 11-8 11.3.2.1 FIR Initialization. 11-8 11.3.2.2 IIR Initialization. 11-8 11.3.3 FIR Filter Type . 11-8 11.3.3.1 FIR Operating Modes . 11-9 11.3.3.1.1 Real Mode. 11-9 11.3.3.1.2 Complex Mode . 11-10 11.3.3.1.3 Alternating Complex Mode . 11-10 11.3.3.1.4 Magnitude Mode. 11-11 11.3.3.2 FIR Filter Type Processing Options . 11-11 11.3.3.2.1 Coefficient Update Option. 11-11 11.3.3.2.2 Adaptive Mode Option . 11-11 11.3.3.2.3 Multichannel Mode Option. 11-12 11.3.3.2.4 Decimation Option. 11-12 11.3.4 IIR Filter Type . 11-13 11.3.5 EFCOP Data Transfer Examples . 11-14 11.3.6 EFCOP Operation Examples . 11-15 11.3.6.1 Real FIR Filter . 11-15 11.3.6.1.1 DMA Input/DMA Output . 11-16 11.3.6.1.2 DMA Input/Polling Output . 11-19 11.3.6.1.3 DMA Input/Interrupt Output . 11-21 11.3.6.2 Real FIR Filter With Decimation by M . 11-23 11.3.6.3 Adaptive FIR Filter . 11-24 11.3.6.3.1 Implementation Using Polling . 11-25 11.3.6.3.2 Implementation Using DMA Input and Interrupt Output . 11-26 11.3.6.3.3 Updating an FIR Filter . 11-26 11.3.6.4 Verification for Filter Examples . 11-29 11.3.6.4.1 Input Sequence (input.asm) . 11-29 11.3.6.4.2 Filter Coefficients (coefs.asm). 11-30 11.3.6.4.3 Output Sequence for Examples 11-1, 11-2, and 11-3. 11-30 11.3.6.4.4 Desired Signal for Example 11-4. 11-30 11.3.6.4.5 Output Sequence for Example 11-4. 11-31 11.4 EFCOP Programming Model. 11-32 11.4.1 Filter Data Input Register (FDIR). 11-32 11.4.2 Filter Data Output Register (FDOR) . 11-32 Contents For More Information On This Product, Go to: www.freescale.com xi Freescale Semiconductor, Inc. 11.4.3 Filter K-Constant Input Register (FKIR). 11-33 11.4.4 Filter Count (FCNT) Register. 11-33 11.4.5 EFCOP Control Status Register (FCSR) . 11-34 11.4.6 EFCOP ALU Control Register (FACR) . 11-37 11.4.7 EFCOP Data Base Address (FDBA) . 11-38 11.4.8 EFCOP Coefficient Base Address (FCBA) . 11-38 11.4.9 Decimation/Channel Count Register (FDCH) . 11-39 11.4.10EFCOP 10EFCOP Interrupt Vectors. 11-40 Freescale Semiconductor, Inc. Chapter A Bootstrap Program A.1 Bootstrap Code . A-1 Chapter B Programming Reference B.1 B.2 B.3 xii Internal I/O Memory Map.B-3 Interrupt Sources and Priorities .B-9 Programming Sheets .B-13 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Figures 1-1 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 DSP56321 DSP56321 Block Diagram. 1-11 Signals Identified by Functional Group. 2-2 MSW[2­0] = 000, Cache Off, 24-Bit Mode . 3-7 MSW[2­0] = 000, Cache On, 24-Bit Mode . 3-8 MSW[2­0] = 001, Cache Off, 24-Bit Mode . 3-9 MSW[2­0] = 001, Cache On, 24-Bit Mode . 3-10 MSW[2­0] = 010, Cache Off, 24-Bit Mode . 3-11 MSW[2­0] = 010, Cache On, 24-Bit Mode . 3-12 MSW[2­0] = 011, Cache Off, 24-Bit Mode . 3-13 MSW[2­0] = 011, Cache On 24-Bit Mode . 3-14 MSW[2­0] = 100, Cache Off, 24-Bit Mode . 3-15 MSW[2­0] = 100, Cache On 24-Bit Mode . 3-16 MSW[2­0] = 101, Cache Off, 24-Bit Mode . 3-17 MSW[2­0] = 101, Cache On, 24-Bit Mode . 3-18 MSW[2­0] = 110, Cache Off, 24-Bit Mode . 3-19 MSW[2­0] = 110, Cache On, 24-Bit Mode . 3-20 MSW[2­0] = 111, Cache Off, 24-Bit Mode . 3-21 MSW[2­0] = 111, Cache On, 24-Bit Mode . 3-22 MSW[2­0] = 000, Cache Off, 16-Bit Mode . 3-23 MSW[2­0] = 000, Cache On, 16-Bit Mode . 3-24 MSW[2­0] = 001, Cache Off, 16-Bit Mode . 3-25 MSW[2­0] = 001, Cache On, 16-Bit Mode . 3-26 MSW[2­0] = 010, Cache Off, 16-Bit Mode . 3-27 MSW[2­0] = 010, Cache On, 16-Bit Mode . 3-28 MSW[2­0] = 011, Cache Off, 16-Bit Mode . 3-29 MSW[2­0] = 011, Cache On, 16-Bit Mode . 3-30 MSW[2­0] = 100, Cache Off, 16-Bit Mode . 3-31 MSW[2­0] = 100, Cache On, 16-Bit Mode . 3-32 MSW[2­0] = 101, Cache Off, 16-Bit Mode . 3-33 MSW[2­0] = 101, Cache On, 16-Bit Mode . 3-34 MSW[2­0] = 110, Cache Off, 16-Bit Mode . 3-35 MSW[2­0] = 110, Cache On, 16-Bit Mode . 3-36 MSW[2­0] = 111, Cache Off, 16-Bit Mode . 3-37 MSW[2­0] = 111, Cache On, 16-Bit Mode . 3-38 Status Register (SR). 4-6 Operating Mode Register (OMR) . 4-10 Interrupt Priority Register-Core (IPRC) (X:$FFFFFF) . 4-14 Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE) . 4-15 Bus Control Register (BCR) . 4-20 Address Attribute Registers (AAR[0­3]) (X:$FFFFF9­$FFFFF6) . 4-22 DMA Control Register (DCR). 4-24 Identification Register Configuration (Revision A) . 4-30 JTAG Identification Register Configuration (Revision 0) . 4-30 Figures For More Information On This Product, Go to: www.freescale.com xiii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 5-1 5-2 5-3 5-4 6-1 6-3 6-2 6-4 6-5 6-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 xiv Clock Generation Diagram . 5-2 DPLL Block Diagram . 5-4 DPLL Clock Control (PCTL) Register-X:$FFFFD1 . 5-7 DPLL Static Control Register (DSCR)-X:$FFFFD0. 5-9 Memory Mapping of Peripherals Control Registers. 6-2 Port C Signals . 6-7 Port B Signals . 6-7 Port D Signals . 6-8 Port E Signals. 6-8 Triple Timer Signals . 6-8 HI08 Block Diagram. 7-5 HI08 Core Interrupt Operation . 7-8 HI08 Host Request Structure . 7-10 HI08 Read and Write Operations in Little Endian Mode . 7-11 HI08 Read and Write Operations in Big Endian Mode . 7-12 Host Control Register (HCR) (X:$FFFFC2) . 7-14 Host Status Register (HSR) (X:$FFFFC3) . 7-15 Host Data Direction Register (HDDR) (X:$FFFFC8). 7-16 Host Data Register (HDR) (X:$FFFFC8). 7-16 Host Base Address Register (HBAR) (X:$FFFFC5). 7-17 Self Chip-Select Logic. 7-17 Host Port Control Register (HPCR) (X:$FFFFC4) . 7-18 Single-Strobe Mode . 7-21 Dual-Strobe Mode. 7-21 Interface Control Register (ICR) . 7-24 Command Vector Register (CVR). 7-27 Interface Status Register (ISR) . 7-28 Interrupt Vector Register (IVR). 7-30 ESSI Block Diagram. 8-1 ESSI Control Register A(CRA) . 8-14 ESSI Clock Generator Functional Block Diagram . 8-17 ESSI Frame Sync Generator Functional Block Diagram . 8-17 ESSI Control Register B (CRB) . 8-18 CRB FSL0 and FSL1 Bit Operation (FSR = 0) . 8-24 CRB SYN Bit Operation. 8-25 CRB MOD Bit Operation . 8-26 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) . 8-27 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame). 8-27 ESSI Status Register (SSISR). 8-28 ESSI Data Path Programming Model (SHFD = 0) . 8-31 ESSI Data Path Programming Model (SHFD = 1) . 8-32 ESSI Transmit Slot Mask Register A (TSMA) . 8-33 ESSI Transmit Slot Mask Register B (TSMB). 8-34 ESSI Receive Slot Mask Register A (RSMA). 8-35 ESSI Receive Slot Mask Register B (RSMB) . 8-35 Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF) . 8-36 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 8-19 8-20 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE). 8-37 Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD). 8-38 SCI Data Word Formats (SSFTD = 1), 1. 9-11 SCI Data Word Formats (SSFTD = 0), 2. 9-12 SCI Control Register (SCR) . 9-13 SCI Clock Control Register (SCCR) . 9-20 SCI Baud Rate Generator . 9-21 16 x Serial Clock. 9-22 SCI Programming Model-Data Registers . 9-23 Port E Control Register (PCRE X:$FFFF9F) . 9-25 Port E Direction Register (PRRE X:$FFFF9E). 9-26 Port Data Registers (PDRE X:$FFFF9D). 9-26 Triple Timer Module Block Diagram . 10-2 Timer Module Block Diagram. 10-3 Timer Mode (TRM = 1). 10-7 Timer Mode (TRM = 0). 10-7 Pulse Mode (TRM = 1). 10-8 Pulse Mode (TRM = 0). 10-9 Toggle Mode, TRM = 1. 10-10 Toggle Mode, TRM = 0. 10-11 Event Counter Mode, TRM = 1 . 10-12 Event Counter Mode, TRM = 0 . 10-13 Pulse Width Measurement Mode, TRM = 1. 10-15 Pulse Width Measurement Mode, TRM = 0. 10-15 Period Measurement Mode, TRM = 1 . 10-16 Period Measurement Mode, TRM = 0 . 10-17 Capture Measurement Mode, TRM = 0. 10-18 Pulse Width Modulation Toggle Mode, TRM = 1. 10-20 Pulse Width Modulation Toggle Mode, TRM = 0. 10-21 Watchdog Pulse Mode . 10-23 Watchdog Toggle Mode . 10-24 Timer Module Programmer's Model . 10-26 Timer Prescaler Load Register (TPLR) . 10-27 Timer Prescaler Count Register (TPCR) . 10-28 Timer Control/Status Register (TCSR). 10-28 EFCOP Block Diagram . 11-3 Storage of Filter Coefficients. 11-5 EFCOP Memory Organization . 11-5 FIR Filter Type Processing . 11-9 IIR Filter Type Processing . 11-13 Real FIR Filter Data Stream . 11-18 Real FIR Filter Data Stream With Decimation by M . 11-23 Adaptive FIR Filter . 11-24 Adaptive FIR Filter Using Polling. 11-25 Adaptive FIR Filter Using DMA Input and Interrupt Output. 11-26 Filter Count (FCNT) Register. 11-33 Figures For More Information On This Product, Go to: www.freescale.com xv Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 11-12 11-13 11-14 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 B-11 B-12 B-13 B-14 B-15 B-16 B-17 B-18 B-19 B-20 B-21 B-22 B-23 B-24 B-25 B-26 B-27 B-28 xvi EFCOP Control Status Register (FCSR) . 11-34 EFCOP ALU Control Register (FACR) . 11-37 Decimation/Channel Count Register (FDCH) . 11-39 Status Register (SR).B-13 Operating Mode Register (OMR) .B-14 Interrupt Priority Register-Core (IPRC) .B-15 Interrupt Priority Register-Peripherals (IPRP) .B-16 Digital Phase-Lock Loop Control (PCTL) Register .B-17 DPLL Static Control Register (DSCR).B-18 Bus Control Register (BCR) .B-19 Address Attribute Registers (AAR[3­0]) .B-20 DMA Control Registers 5­0 (DCR[5­0]) .B-21 Host Transmit Data Register.B-22 Host Base Address and Host Port Control Registers .B-23 Host Control Register .B-24 Interrupt Control and Command Vector Registers .B-25 Interrupt Vector and Host Transmit Data Registers .B-26 ESSI Control Register A (CRA) .B-27 ESSI Control Register B (CRB) .B-28 ESSI Transmit and Receive Slot Mask Registers (TSM, RSM).B-29 SCI Control Register (SCR) .B-30 SCI Clock Control Registers (SCCR).B-31 Timer Prescaler Load Register (TPLR) .B-32 Timer Control/Status Register (TCSR).B-33 Timer Load Registers (TLR) .B-34 Host Data Direction and Host Data Registers (HDDR, HDR) .B-35 Port C Registers (PCRC, PRRC, PDRC).B-36 Port D Registers (PCRD, PRRD, PDRD).B-37 Port E Registers (PCRE, PRRE, PDRE).B-38 EFCOP Counter and Control Status Registers (FCNT and FCSR) .B-39 EFCOP FACR, FDBA, FCBA, and FDCH Registers .B-40 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Tables 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 High True/Low True Signal Conventions . 1-3 DSP56321 DSP56321 Switch Memory Configuration. 1-9 DSP56321 DSP56321 Functional Signal Groupings . 2-1 Power Inputs . 2-3 Grounds. 2-3 Clock Signals . 2-3 Digital Phase-Lock Loop Signals . 2-4 External Address Bus Signals. 2-4 External Data Bus Signals . 2-4 External Bus Control Signals. 2-5 Interrupt and Mode Control . 2-7 Host Interface. 2-8 Enhanced Synchronous Serial Interface 0 (ESSI0) . 2-11 Enhanced Synchronous Serial Interface 1 (ESSI1) . 2-13 Serial Communication Interface (SCI) . 2-15 Triple Timer Signals . 2-16 OnCE/JTAG Interface . 2-17 DSP56321 DSP56321 Switch Memory Configuration. 3-5 DSP56321 DSP56321 Operating Modes . 4-2 Status Register Bit Definitions . 4-6 Operating Mode Register (OMR) Bit Definitions . 4-11 Interrupt Priority Level Bits. 4-15 Interrupt Sources. 4-16 Interrupt Source Priorities Within an IPL. 4-18 Bus Control Register (BCR) Bit Definitions . 4-20 Address Attribute Registers (AAR[0­3]) Bit Definitions . 4-22 DMA Control Register (DCR) Bit Definitions. 4-24 Acronym List . 5-3 DPLL Clock Control Register (PCTL) . 5-7 DPLL Static Control Register (DSCR) Bit Definitions. 5-9 DMA-Accessible Registers. 6-5 HI08 Signal Definitions for Operational Modes. 7-3 HI08 Data Strobe Signals . 7-4 HI08 Host Request Signals . 7-4 DMA Request Sources. 7-9 HREQ Pin Operation In Single Request Mode (ICR[2]=HDRQ=0). 7-10 HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2]=HDRQ=1) . 7-11 HI08 Boot Modes. 7-12 Host Control Register (HCR) Bit Definitions. 7-14 Host Status Register (HSR) Bit Definitions . 7-15 HDR and HDDR Functionality. 7-16 Host Base Address Register (HBAR) Bit Definitions . 7-17 Host Port Control Register (HPCR) Bit Definitions. 7-18 Tables For More Information On This Product, Go to: www.freescale.com xvii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 B-1 B-2 B-3 B-4 B-5 xviii DSP-Side Registers After Reset . 7-22 Host-Side Register Map. 7-24 Interface Control Register (ICR) Bit Definitions . 7-25 Command Vector Register (CVR) Bit Definitions. 7-27 Interface Status Register (ISR) Bit Definitions . 7-28 Host-Side Registers After Reset . 7-32 HI08 Programming Model, DSP Side . 7-33 HI08 Programming Model: Host Side . 7-35 ESSI Clock Sources . 8-3 Mode and Signal Definitions . 8-5 ESSI Control Register A (CRA) Bit Definitions . 8-15 ESSI Control Register B (CRB) Bit Definitions . 8-19 ESSI Status Register (SSISR) Bit Definitions . 8-28 ESSI Port Signal Configurations . 8-37 SCI Registers After Reset . 9-6 SCI Control Register (SCR) Bit Definitions. 9-13 SCI Status Register . 9-18 SCI Status Register (SSR) Bit Definitions . 9-18 SCI Clock Control Register (SCCR) Bit Definitions . 9-20 Timer Prescaler Load Register (TPLR) Bit Definitions . 10-27 Timer Prescaler Count Register (TPCR) Bit Definitions . 10-28 Timer Control/Status Register (TCSR) Bit Definitions. 10-28 Inverter (INV) Bit Operation . 10-32 EFCOP Registers Accessible Through the PMB. 11-4 EFCOP Operating Modes . 11-7 DMA Channel 0 Register Initialization . 11-16 DMA Channel 1 Register Initialization . 11-17 EFCOP Registers and Base Addresses . 11-32 Filter Count FCNT Register Bits . 11-33 FCSR Bits . 11-34 EFCOP ALU Control Register (FACR) Bits. 11-37 Decimation/Channel Count Register (FDCH) Bits . 11-39 EFCOP Interrupt Vectors. 11-40 EFCOP DMA Request Sources . 11-40 Guide to Programming Sheets .B-2 Internal I/O Memory Map (X Data Memory).B-3 Internal I/O Memory Map (Y Data Memory).B-8 Interrupt Sources.B-9 Interrupt Source Priorities Within an IPL.B-11 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Chapter 1 Overview This manual describes the DSP56321 DSP56321 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56321 DSP56321 is an implementation of the DSP56300 DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals. Use this manual in conjunction with the DSP56300 DSP56300 Family Manual (DSP56300FM/AD DSP56300FM/AD), which describes the CPU, core programming models, and instruction set. Note: The DSP56321 DSP56321 Digital Phase-Lock Loop (DPLL) and clock modules differ from other members of the DSP56300 DSP56300 family. Detailed information about these modules, including the programming model, is included in Chapter 4 of this manual. The DSP56321 DSP56321 Technical Data (DSP56321/D DSP56321/D)-referred to as the data sheet-provides DSP56321 DSP56321 electrical specifications, timing, pinout, and packaging descriptions. You can obtain these documents-and the Motorola DSP development tools-through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information on this DSP, access the Motorola DSP home page at the address given on the back cover of this document. Overview For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. Manual Organization 1.1 Manual Organization This manual contains the following sections and appendices: Chapter 2, Signals/Connections - DSP56321 DSP56321 signals and their functional groupings. s Chapter 3, Memory Configuration - DSP56321 DSP56321 memory spaces, RAM configuration, memory configuration bit settings, memory configurations, and memory maps. s Chapter 4, Core Configuration - Registers for configuring the DSP56300 DSP56300 core when programming the DSP56321 DSP56321, in particular the interrupt vector locations and the operation of the interrupt priority registers; operating modes and how they affect the processor's program and data memories. This chapter also provides detailed information about the Digital Phase-Lock Loop (DPLL) and clock modules that are unique to the DSP56321 DSP56321. s Chapter 5, Programming the Peripherals - Guidelines on initializing the DSP56321 DSP56321 peripherals, including mapping control registers, specifying a method of transferring data, and configuring for general-purpose input/output (GPIO). s Chapter 6, Host Interface (HI08) - Features, signals, architecture, programming model, reset, interrupts, external host programming model, initialization, and a quick reference to the HI08 programming model. s Chapter 7, Enhanced Synchronous Serial Interface (ESSI) - Enhancements, data and control signals, programming model, operating modes, initialization, exceptions, and GPIO. s Chapter 8, Serial Communication Interface (SCI) - Signals, programming model, operating modes, reset, initialization, and GPIO. s Chapter 9, Triple Timer Module - Architecture, programming model, and operating modes of three identical timer devices available for use as internals or event counters. s Chapter 10, Enhanced Filter Coprocessor (EFCOP) - Structure and function of the EFCOP, including features, architecture, and programming model; programming topics such as data transfer to and from the EFCOP, its use in different modes, and examples of usage. s Appendix A, Bootstrap Code - Bootstrap code for the DSP56321 DSP56321. s 1-2 Chapter 1, Overview - Features list and block diagram, related documentation, organization of this manual, and the notational conventions used. s Freescale Semiconductor, Inc. s Appendix B, Programming Reference - Peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56321 DSP56321; programming sheets listing the contents of the major DSP56321 DSP56321 registers for programmer's reference. DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Manual Conventions 1.2 Manual Conventions This manual uses the following conventions: Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). s Freescale Semiconductor, Inc. s Bits within a register are indicated AA[n­m], n > m, when more than one bit is involved in a description. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmer's sheets to see the exact location of bits within a register. s When a bit is described as "set," its value is 1. When a bit is described as "cleared," its value is 0. s The word "assert" means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. The word "deassert" means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC. See Table 1-1. Table 1-1. High True/Low True Signal Conventions Signal/Symbol True Asserted Ground2 False Deasserted VCC3 PIN True Asserted VCC PIN s Voltage PIN 3. Signal State PIN1 1. 2. Logic State False Deasserted Ground PIN is a generic term for any pin on the chip. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low). VCC is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high voltage levels (typically a TTL logic high). Pins or signals that are asserted low (made active when pulled to ground) are indicated like this in text: - In text, they have an overbar: for example, RESET is asserted low. - In code examples, they have a tilde in front of their names. In Example 1-1, line 3 refers to the SS0 signal (shown as ~SS0). s Sets of signals are indicated by the first and last signals in the set, for instance HA[0­3]. s "Input/Output" indicates a bidirectional signal. "Input or Output" indicates a signal that is exclusively one or the other. Overview For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. Features s Code examples are displayed in a monospaced font, as shown in Example 1-1. Example 1-1. Sample Code Listing BFSET #$0007,X:PCC; Configure: line 1 ; line 2 MISO0, MOSI0, SCK0 for SPI master ; ~SS0 as PC3 for GPIO line 3 Freescale Semiconductor, Inc. s Hex values are indicated with a $ preceding the hex value, as follows: $FFFFFF is the X memory address for the core interrupt priority register. s The word "reset" is used in four different contexts in this manual: - the reset signal, written as RESET - the reset instruction, written as RESET - the reset operating state, written as Reset - the reset function, written as reset 1.3 Features The Motorola DSP56321 DSP56321, a member of the DSP56300 DSP56300 core family of programmable DSPs, supports wireless infrastructure applications with general filtering operations. The on-chip EFCOP processes filter algorithms in parallel with core operation, thus increasing overall DSP performance and efficiency. Like the other family members, the DSP56321 DSP56321 uses a high-performance, single-clock-cycle-per-instruction engine (code compatible with Motorola's popular DSP56000 DSP56000 core family), a barrel shifter, 24-bit addressing, instruction cache, and DMA controller. The DSP56321 DSP56321 offers 200 million instructions per second (MIPS) performance (360 MIPS using the EFCOP in filtering applications) using an internal 200 MHz clock with 1.5 V core and independent 3.3 V input/output (I/O) power. All DSP56300 DSP56300 core family members contain the DSP56300 DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements, such as memories and peripherals. A standard interface between the DSP56300 DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. In particular, the DSP56321 DSP56321 includes Motorola's JTAG port and OnCE module. The DSP56321 DSP56321, with its large on-chip memory array of 192 K words and its EFCOP, is well suited for high-end multichannel telecommunication applications, such as wireless infrastructure, multi-line voice/data/FAX processing, video conferencing, and general digital signal processing. 1-4 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56300 DSP56300 Core 1.4 DSP56300 DSP56300 Core Core features are fully described in the DSP56300 DSP56300 Family Manual. (This manual, in contrast, documents pinout, memory, and peripheral features.) Core features are as follows: 200 MIPS (360 MIPS using the EFCOP in filtering applications) with a 200 MHz clock at 1.5 V s Object code compatible with the DSP56000 DSP56000 core s Highly parallel instruction set s Freescale Semiconductor, Inc. s Large on-chip RAM memory of 192 K words s EFCOP running concurrently with the core, capable of executing 200 million filter taps per second at peak performance s Hardware debugging support - JTAG test access port (TAP) - OnCE module - Address trace mode reflects internal accesses at the external port s Reduced power dissipation - Very low-power CMOS design - Wait and stop low-power standby modes - Fully-static design specified to operate down to 0 Hz (dc) - Optimized power-management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) 1.5 DSP56300 DSP56300 Core Functional Blocks The functional blocks of the DSP56300 DSP56300 core are: s Data arithmetic logic unit (ALU) s Address generation unit s Program control unit s DPLL and clock oscillator s JTAG TAP and OnCE module s Memory In addition, the DSP56321 DSP56321 provides a set of on-chip peripherals, discussed in Section 1.9, Peripherals, on page 1-12. Overview For More Information On This Product, Go to: www.freescale.com 1-5 Freescale Semiconductor, Inc. DSP56300 DSP56300 Core Functional Blocks 1.5.1 Data ALU The data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 DSP56300 core. These are the components of the data ALU: Fully pipelined 24 × 24-bit parallel multiplier-accumulator s Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) s Conditional ALU instructions s Freescale Semiconductor, Inc. s Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support s Four 24-bit or 48-bit input general-purpose registers: X1, X0, Y1, and Y0 s Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two general-purpose, 56-bit accumulators, A and B, accumulator shifters s Two data bus shifter/limiter circuits 1.5.1.1 Data ALU Registers The data ALU registers are read or written over the X data bus and the Y data bus as 16- or 32-bit operands. The source operands for the data ALU can be 16, 32, or 40 bits and always originate from data ALU registers. The results of all data ALU operations are stored in an accumulator. Data ALU operations are performed in two clock cycles in a pipeline so that a new instruction can be initiated in every clock cycle, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be a source operand for the immediately following operation without penalty. 1.5.1.2 Multiplier-Accumulator (MAC) The MAC unit comprises the main arithmetic processing unit of the DSP56300 DSP56300 core and performs all of the calculations on data operands. For arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following form: extension:most significant product:least significant product (EXT:MSP:LSP). The multiplier executes 24-bit × 24-bit parallel, fractional multiplies between twos-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP is either truncated or rounded into the MSP. Rounding is performed if specified. 1-6 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56300 DSP56300 Core Functional Blocks 1.5.2 Address Generation Unit (AGU) Freescale Semiconductor, Inc. The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead. The AGU is divided into halves, each with its own identical address ALU. Each address ALU has four sets of register triplets, and each register triplet includes an address register, offset register, and modifier register. Each contains a 24-bit full adder (called an offset adder). A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided. The offset adder and the reverse-carry adder work in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output. Each address ALU can update one address register from its own address register file during one instruction cycle. The contents of the associated modifier register specify the type of arithmetic used in the address register update calculation. The modifier value is decoded in the address ALU. 1.5.3 Program Control Unit (PCU) The PCU fetches and decodes instructions, controls hardware DO loops, and processes exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300 DSP56300 core. The PCU consists of three hardware blocks: s Program decode controller - decodes the 24-bit instruction loaded into the instruction latch and generates all signals for pipeline control. s Program address generator - contains all the hardware needed for program address generation, system stack, and loop control. s Program interrupt controller - arbitrates among all interrupt requests (internal interrupts, as well as the five external requests IRQA, IRQB, IRQC, IRQD, and NMI), and generates the appropriate interrupt vector address. PCU features include the following: s Position-independent code support s Addressing modes optimized for DSP applications (including immediate offsets) s On-chip instruction cache controller Overview For More Information On This Product, Go to: www.freescale.com 1-7 Freescale Semiconductor, Inc. DSP56300 DSP56300 Core Functional Blocks s On-chip memory-expandable hardware stack s Nested hardware DO loops s Fast auto-return interrupts s Hardware system stack The PCU uses the following registers: Program counter register s Status register s Freescale Semiconductor, Inc. s Loop address register s Loop counter register s Vector base address register s Size register s Stack pointer s Operating mode register s Stack counter register 1.5.4 Clock Generator Circuit The DSP56321 DSP56321 contain a Clock Generator (CLKGEN) that is different from the clock generator and Phase-Lock Loop (PLL) used by other members of the DSP56300 DSP56300 family. The DSP56321 DSP56321 uses a CLKGEN module with an integrated Digital Phase-Lock Loop (DPLL). As with the previous clock generator, the DSP56321 DSP56321 allows you to change the low-power Division Factor (DF) without losing lock. The CLKGEN module uses two internal X-I/O-mapped registers that are different from the standard DSP56300 DSP56300 design described in the DSP56300 DSP56300 Family Manual. Chapter 5 describes the new clock registers in detail. The DPLL allows the processor to operate at a high internal clock frequency using a low-frequency clock input, a feature that offers two immediate benefits: s s 1-8 A lower-frequency clock input reduces the overall electromagnetic interference generated by a system. The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56300 DSP56300 Core Functional Blocks 1.5.5 JTAG TAP and OnCE Module Freescale Semiconductor, Inc. In the DSP56300 DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems with testing high-density circuit boards led to the development of this standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The DSP56300 DSP56300 core implementation supports circuit-board test strategies based on this standard. The test logic includes a TAP with four dedicated signals, a 16-state controller, and three test data registers. A boundary scan register links all device signals into a single shift register. The test logic, implemented utilizing static logic design, is independent of the device system logic. For details on the JTAG port, consult the DSP56300 DSP56300 Family Manual. The OnCE module interacts with the DSP56300 DSP56300 core and its peripherals nonintrusively so that you can examine registers, memory, or on-chip peripherals. This facilitates hardware and software development on the DSP56300 DSP56300 core processor. OnCE module functions are provided through the JTAG TAP signals. For details on the OnCE module, consult the DSP56300 DSP56300 Family Manual. 1.5.6 On-Chip Memory The memory space of the DSP56300 DSP56300 core is partitioned into program, X data, and Y data memory space. The data memory space is divided into X and Y data memory in order to work with the two address ALUs and to feed two operands simultaneously to the data ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software control. There is an on-chip 192 × 24-bit bootstrap ROM. For details on internal memory, see Chapter 3, Memory Configuration. Program RAM, instruction cache, X data RAM, and Y data RAM size are programmable, as Table 1-2 shows. Table 1-2. DSP56321 DSP56321 Switch Memory Configuration Program RAM Size Instruction Cache Size X Data RAM Size* Y Data RAM Size* Instruction Cache (CE) MSW2 MSW1 MSW0 32 K × 24-bit 0 80 K × 24-bit 80 K × 24-bit disabled 0 0 0 31 K × 24-bit 1024 × 24-bit 80 K × 24-bit 80 K × 24-bit enabled 0 0 0 40 K × 24-bit 0 76 K × 24-bit 76 K × 24-bit disabled 0 0 1 39 K × 24-bit 1024 × 24-bit 76 K × 24-bit 76 K × 24-bit enabled 0 0 1 48 K × 24-bit 0 72 K × 24-bit 72 K × 24-bit disabled 0 1 0 47 K × 24-bit 1024 × 24-bit 72 K × 24-bit 72 K × 24-bit enabled 0 1 0 64 K × 24-bit 0 64 K × 24-bit 64 K × 24-bit disabled 0 1 1 63 K × 24-bit 1024 × 24-bit 64 K × 24-bit 64 K × 24-bit enabled 0 1 1 72 K × 24-bit 0 60 K × 24-bit 60 K × 24-bit disabled 1 0 0 71 K × 24-bit 1024 × 24-bit 60 K × 24-bit 60 K × 24-bit enabled 1 0 0 80 K × 24-bit 0 56 K × 24-bit 56 K × 24-bit disabled 1 0 1 79 K × 24-bit 1024 × 24-bit 56 K × 24-bit 56 K × 24-bit enabled 1 0 1 Overview For More Information On This Product, Go to: www.freescale.com 1-9 Freescale Semiconductor, Inc. Internal Buses Table 1-2. DSP56321 DSP56321 Switch Memory Configuration (Continued) Program RAM Size Instruction Cache Size X Data RAM Size* Y Data RAM Size* Instruction Cache (CE) MSW2 MSW1 MSW0 96 K × 24-bit 0 48 K × 24-bit 48 K × 24-bit disabled 1 1 0 95 K × 24-bit 1024 × 24-bit 48 K × 24-bit 48 K × 24-bit enabled 1 1 0 112 K × 24-bit 0 40 K × 24-bit 40 K × 24-bit disabled 1 1 1 111 K × 24-bit 1024 × 24-bit 40 K × 24-bit 40 K × 24-bit enabled 1 1 1 *Includes 12 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP) Freescale Semiconductor, Inc. 1.5.7 Off-Chip Memory Expansion Memory can be expanded off chip to the following capacities: s s Data memory expansion to two 256 K × 24-bit word memory spaces using standard address lines Program memory expansion to one 256 K × 24-bit word memory space using standard address lines Further features of off-chip memory include the following: s s External memory expansion port Simultaneous glueless interface to Static RAM (SRAM) 1.6 Internal Buses To provide data exchange between blocks, the DSP56321 DSP56321 implements the following buses: s s s s s s s s s s s I/O expansion bus to peripherals Program memory expansion bus to program ROM X memory expansion bus to X memory Y memory expansion bus to Y memory Global data bus between PCU and other core structures Program data bus for carrying program data throughout the core X memory data bus for carrying X data throughout the core Y memory data bus for carrying Y data throughout the core Program address bus for carrying program memory addresses throughout the core X memory address bus for carrying X memory addresses throughout the core Y memory address bus for carrying Y memory addresses throughout the core The block diagram in Figure 1-1 illustrates these buses among other components. 1-10 DSP56321 DSP56321 Reference Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Block Diagram 1.7 Block Diagram All internal buses on the DSP56300 DSP56300 family members are 24-bit buses. The program data bus is also a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56321 DSP56321. 3 16 6 6 Memory Expansion Area Triple Timer Host ESSI Interface Interface (HI08) Enhanced Filter Coprocessor 32 K × 24 bit or (EFCOP) 31 K × 24 bit and Program RAM X Data Y Data RAM RAM 80 K × 24 bit 1024 × 24 bit 80 K × 24 bit YAB Address Generation Unit YM_EB PM_EB Peripheral Expansion Area XM_EB Instruction Cache PIO_EB Freescale Semiconductor, Inc. SCI Interface External Address Bus Switch XAB PAB DAB Six Channel DMA Unit External Bus Interface and I - Cache Control 24-Bit Bootstrap ROM DSP56300 DSP56300 Core 18 Address 10 Control DDB Internal Data Bus Switch External Data Bus Switch YDB XDB PDB 24 Data GDB Power Management CLOCK Generator DPLL Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24+5656-bit MAC Two 56-bit Accumulators 5 JTAG OnCETM Port DE 56-bit Barrel Shifter EXTAL XTAL RESET PINIT/NMI MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1-1. DSP56321 DSP56321 Block Diagram Note: See Section 1.5.6, On-Chip Memory, on page 1-9 for details about memory size. Overview For More Information On This Product, Go to: www.freescale.com 1-11 Freescale Semiconductor, Inc. DMA 1.8 DMA The DMA block has the following features: s s s s Six DMA channels supporting internal and external accesses One-, two-, and three-dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals Freescale Semiconductor, Inc. 1.9 Peripherals In addition to the core features, the DSP56321 DSP56321 provides the following peripherals: s s s s s s s As many as 34 user-configurable GPIO signals HI08 to external hosts Dual ESSI