DSP56305/D DSP56300 DSP56305 DSP56000 DSP56300FM/AD DSP56305UM/D DSP56301 HAD10 - Datasheet Archive

 

DSP56305/D Rev. 3, 1/2002 24-Bit Digital Signal Processor 51 6 6 3 Memory Expansion Area Program Memory* FCOP VCOP CCOP

 

Technical Data DSP56305/D DSP56305/D Rev. 3, 1/2002 24-Bit Digital Signal Processor 51 6 6 3 Memory Expansion Area Program Memory* FCOP VCOP CCOP Peripheral Expansion Area RAM 6.5 K × 24 ROM 6 K × 24 *default RAM 3.75 K × 24 YAB XAB PAB DAB Core DDB YDB XDB PDB GDB Internal Data Bus Switch External 24 Address Bus Switch Address External Data Bus Switch Power Mngmnt EXTAL PLL ROM 3 K × 24 External Bus 15 Interface & I-Cache Control Control DSP56300 DSP56300 XTAL RAM 2 K × 24 *default 24-Bit Clock Generator Y Memory YM_EB SCI XM_EB Address Generation Unit Six Channel DMA Unit ESSI PM_EB Motorola designed the DSP56305 DSP56305 to deliver the high performance required to support Global System for Mobile (GSM) communications applications that use digital signal processing to perform channel equalization, channel coding, and speech coding. Host PIO_EB Timer X Memory* Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24 + 56 56-bit MAC JTAG Two 56-bit Accumulators OnCETM 56-bit Barrel Shifter 24 Data 5 DE 2 RESET PINIT/NMI MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1. DSP56305 DSP56305 Block Diagram By combining three dedicated on-chip hardware coprocessors (filter, Viterbi, and cyclic code) with a DSP56300 DSP56300 core, the DSP56305 DSP56305 performs all the complex signal processing required by a single radio frequency (RF) carrier in one chip, satisfying the demand for high integration cost effectively. The DSP56300 DSP56300 core includes an on-chip PLL, a Data ALU, an instruction cache, on-chip debugging modules, on-chip program and data memory, six DMA channels, and an external memory expansion port. In addition to the coprocessors, the DSP56305 DSP56305 provides two types of serial ports, a PCI/Universal bus 32-bit host interface, and timers (see Figure 1). The DSP56305 DSP56305 provides an industry-leading performance rate of 100 MIPS at 3.3 V. Table of Contents DSP56305 DSP56305 Features. iii Product Documentation.v Product Documentation.v Chapter 1 Signal/ Connection Descriptions 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 Chapter 2 Specifications 2.1 2.2 2.4 2.5 2.6 Chapter 3 Pin-Out and Package Information. 3-1 MAP-BGA Package Description . 3-2 MAP-BGA Package Mechanical Drawing . 3-13 Design Considerations 4.1 4.2 4.3 4.4 4.5 Appendix A Introduction . 2-1 Maximum Ratings. 2-1 Thermal Characteristics . 2-2 DC Electrical Characteristics . 2-3 AC Electrical Characteristics . 2-4 Packaging 3.1 3.2 3.3 Chapter 4 Signal Groupings. 1-1 Power. 1-4 Ground. 1-4 Clock . 1-4 Phase Lock Loop (PLL) . 1-5 External Memory Expansion Port (Port A). 1-5 Interrupt and Mode Control . 1-8 Host Interface (HI32) . 1-10 Enhanced Synchronous Serial Interface 0 (ESSI0). 1-18 Enhanced Synchronous Serial Interface 1 (ESSI1). 1-20 Serial Communication Interface (SCI). 1-22 Timers. 1-23 JTAG/OnCE Interface . 1-24 Thermal Design Considerations. 4-1 Electrical Design Considerations . 4-2 Power Consumption Considerations . 4-3 PLL Performance Issues . 4-4 Input (EXTAL) Jitter Requirements. 4-5 Power Consumption Benchmark Index Data Sheet Conventions OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. ii DSP56305 DSP56305 Features High-Performance DSP56300 DSP56300 Core · 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0­3.6 V · Object code compatible with the DSP56000 DSP56000 core with highly parallel instruction set · Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control · Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts · Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals · Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination · Hardware debugging support including On-Chip Emulation (OnCETM) module, Joint Test Action Group (JTAG) Test Access Port (TAP) On-Chip Coprocessors · The Filter Coprocessor (FCOP) implements a wide variety of convolution and correlation filtering algorithms. In GSM applications, the FCOP cross-correlates between the received training sequence and a known midamble sequence to estimate the channel impulse response, and then performs match filtering of received data symbols using coefficients derived from that estimated channel. · The Viterbi Coprocessor (VCOP) implements a Maximum Likelihood Sequential Estimation (MLSE) algorithm for channel decoding and equalization (uplink) and channel convolution coding (downlink). The VCOP supports constraint lengths (k) of 4, 5, 6, or 7 with number of states 8, 16, 32, or 64, respectively; code rates of 1/2, 1/3, 1/4, or 1/6; and trace-back Trellis depth of 36. · The Cyclic-code Coprocessor (CCOP) executes cyclic code calculations for data ciphering and deciphering, as well as parity code generation and check. The CCOP is fully programmable and not dedicated to a specific algorithm, but it is well suited for GSM A5.1 and A5.2 data ciphering algorithms. The CCOP can generate mask sequences for data ciphering, and supports Fire encode and decode for burst error correction, as well as generation of Cyclic Redundancy Code (CRC) syndrome for any polynomial of any degree up to 48. On-Chip Peripherals · 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless interface to other DSP563xx buses or ISA interface requiring only 74LS45-style buffers · Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) · Serial communications interface (SCI) with baud rate generator · Triple timer module · Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled iii On-Chip Memories · · · · 192 K × 24-bit bootstrap ROM 6144 K × 24-bit program ROM 3072 K × 24-bit Y data ROM Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: Program RAM Instruction Cache X Data RAM Size Y Data RAM Size Size Size Instruction Cache Switch Mode 6656 × 24 bits 0 3840 × 24 bits 2048 × 24 bits disabled disabled 5632 × 24 bits 1024 × 24 bits 3840 × 24 bits 2048 × 24 bits enabled disabled 7680 × 24 bits 0 2816 × 24 bits 2048 × 24 bits disabled enabled 6656 × 24 bits 1024 × 24 bits 2816 × 24 bits 2048 × 24 bits enabled enabled Off-Chip Memory Expansion · Data memory expansion to two 16 M × 24-bit word memory spaces in 24-Bit mode or two 64 K × 16-bit memory spaces in 16-Bit Compatibility mode · Program memory expansion to one 16 M × 24-bit words memory space in 24-Bit mode or 64 K × 16-bit in 16-Bit Compatibility mode · External memory expansion port · Chip Select Logic for glueless interface to SRAMs · On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs) Reduced Power Dissipation · · · · Very low-power CMOS design Wait and Stop low-power standby modes Fully static design specified to operate down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) Packaging The DSP56305 DSP56305 is available in a 252-pin molded array process-ball grid array (MAP-BGA) package. iv Product Documentation The three documents listed in the following table are required for a complete description of the DSP56305 DSP56305 and are necessary to design properly with the part. Documentation is available from the following sources. (See the back cover for detailed information.) · · · · A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW) Table 1. DSP56305 DSP56305 Name Documentation Description Order Number DSP56300 DSP56300 Family Manual Detailed description of the DSP56300 DSP56300 family processor core and instruction set DSP56300FM/AD DSP56300FM/AD DSP56305 DSP56305 User's Manual Detailed functional description of the DSP56305 DSP56305 memory configuration, operation, and register programming DSP56305UM/D DSP56305UM/D DSP56305 DSP56305 Technical Data DSP56305 DSP56305 features list and physical, electrical, timing, and package specifications DSP56305/D DSP56305/D v vi Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings The DSP56305 DSP56305 input and output signals are organized into functional groups, as shown in Table 1-1 and illustrated in Figure 1-1. The DSP56305 DSP56305 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1. DSP56305 DSP56305 Functional Signal Groupings Number of Signals Functional Group Detailed Description Power (VCC) 45 Table 1-2 Ground (GND) 38 Table 1-3 Clock 2 Table 1-4 PLL 3 Table 1-5 24 Table 1-6 Data Bus 24 Table 1-7 Bus Control 15 Table 1-8 5 Table 1-9 Port B2 52 Table 1-11 Ports C and D3 12 Table 1-12 and Table 1-13 Port E4 3 Table 1-14 Timer 3 Table 1-15 JTAG/OnCE Port 6 Table 1-16 Address Bus Port A1 Interrupt and Mode Control Host Interface (HI32) Enhanced Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Notes: 1. 2. 3. 4. 5. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI32 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. Each device also includes twenty no connect (NC) pins. Do not connect any line, component, trace, or via to these pins. See Chapter 3 for details. 1-1 Signal Groupings DSP56305 DSP56305 VCCP VCC 44 Power Inputs: PLL Internal VCC plane MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Interrupt /Mode Control PCI Bus GNDP GNDP1 GND 36 EXTAL XTAL Grounds: PLL PLL Internal GND plane Clock CLKOUT PCAP PINIT/NMI 52 Extended Synchronous Serial Interface Port 0 (ESSI0)2 3 Extended Synchronous Serial Interface Port 1 (ESSI1)2 3 24 D[0-23] AA[0­3] RAS[0­3] RD WR BS TA BR BG BB BL CAS BCLK BCLK External Address Bus 24 A[0-23] External Data Bus 4 Serial Communications Interface (SCI) Port2 External Bus Control Timers3 JTAG/OnCE Port 1. 2. 3. SC[00-02] SCK0 SRD0 STD0 Port C GPIO PC[0-2] PC3 PC4 PC5 SC[10-12] SCK1 SRD1 STD1 Port D GPIO PD[0-2] PD3 PD4 PD5 RXD TXD SCLK Port E GPIO PE0 PE1 PE2 TIO0 TIO1 TIO2 Timer GPIO TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE The HI32 port supports PCI and non-PCI bus configurations. Twenty-four HI32 signals can also be configured as GPIO signals (PB[0­23]). The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0­5]), Port D GPIO signals (PD[0­5]), and Port E GPIO signals (PE[0­2]), respectively. TIO[0­2] can be configured as GPIO signals. Figure 1-1. Signals Identified by Functional Group 1-2 Port B GPIO See Figure 1-2 for a listing of the Host Interface/Port B Signals PLL Port A Notes: Host Interface (HI32) Port1 Universal Bus Signal Groupings PCI Bus DSP56301 DSP56301 Host Interface (HI32)/ Port B Signals Note: Universal Bus Port B GPIO HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD10 HAD11 HAD11 HAD12 HAD12 HAD13 HAD13 HAD14 HAD14 HAD15 HAD15 HC0/HBE0 HC1/HBE1 HC2/HBE2 HC3/HBE3 HTRDY HIRDY HDEVSEL HLOCK HPAR HPERR HGNT HREQ HSERR HSTOP HIDSEL HFRAME HCLK HAD16 HAD16 HAD17 HAD17 HAD18 HAD18 HAD19 HAD19 HAD20 HAD20 HAD21 HAD21 HAD22 HAD22 HAD23 HAD23 HAD24 HAD24 HAD25 HAD25 HAD26 HAD26 HAD27 HAD27 HAD28 HAD28 HAD29 HAD29 HAD30 HAD30 HAD31 HAD31 HRST HINTA PVCL HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA0 HA1 HA2 Tie to pull-up or VCC HDBEN HDBDR HSAK HBS HDAK HDRQ HAEN HTA HIRQ HWR/HRW HRD/HDS Tie to pull-up or VCC Tie to pull-up or VCC HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HRST HINTA Leave unconnected PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Leave unconnected Host Port (HP) Reference HP0 HP1 HP2 HP3 HP4 HP5 HP6 HP7 HP8 HP9 HP10 HP11 HP12 HP13 HP14 HP15 HP16 HP17 HP18 HP19 HP20 HP21 HP22 HP23 HP24 HP25 HP26 HP27 HP28 HP29 HP30 HP31 HP32 HP33 HP34 HP35 HP36 HP37 HP38 HP39 HP40 HP41 HP42 HP43 HP44 HP45 HP46 HP47 HP48 HP49 HP50 PVCL HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been renamed PBxx for consistency with other Motorola DSPs. Figure 1-2. Host Interface/Port B Detail Signal Diagram 1-3 Power 1.2 Power Table 1-2. Power Inputs Power Name Description VCCP PLL Power Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCC Quiet Power Isolated power for the internal processing logic. This input is tied externally to all other chip power inputs except VCCP. The user must provide adequate external decoupling capacitors. 1.3 Ground Table 1-3. Grounds Ground Name Description GNDP PLL Ground Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package. GNDP1 PLL Ground 1 Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. GND Quiet Ground Isolated ground for the internal processing logic. This connection is tied internally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors. 1.4 Clock Table 1-4. Clock Signals Signal Name Type State During Reset Signal Description EXTAL Input External Clock/Crystal Input Interfaces the internal crystal oscillator input to an external crystal or an external clock. XTAL 1-4 Input Output Chip-driven Crystal Output Connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. Phase Lock Loop (PLL) 1.5 Phase Lock Loop (PLL) Table 1-5. Phase Lock Loop Signals Signal Name CLKOUT Type Output State During Reset Chip-driven Signal Description Clock Output Provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. PCAP Input Input PLL Capacitor Connects an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP can be tied to VCC, GND, or left floating. PINIT/NMI Input Input PLL Initial/Non-Maskable Interrupt During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT. PINIT/NMI can tolerate 5 V. 1.6 External Memory Expansion Port (Port A) Note: When the DSP56305 DSP56305 enters a low-power stand-by mode (Stop or Wait), it releases bus mastership and tri-states the relevant Port A signals: A[0­23], D[0­23], AA0/RAS0­AA3/RAS3, RD, WR, BB, CAS, BCLK, and BCLK. If hardware refresh of external DRAM is enabled, Port A exits the Wait mode to allow the refresh to occur and then returns to the Wait mode. 1.6.1 External Address Bus Table 1-6. External Address Bus Signals Signal Name A[0­23] Type Output State During Reset Tri-stated Signal Description Address Bus When the DSP is the bus master, A[0­23] specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A[0­23] do not change state when external memory spaces are not being accessed. 1-5 External Memory Expansion Port (Port A) 1.6.2 External Data Bus Table 1-7. External Data Bus Signals Signal Name D[0­23] Type Input/Output State During Reset Tri-stated Signal Description Data Bus When the DSP is the bus master, D[0­23] provide the bidirectional data bus for external program and data memory accesses. Otherwise, D[0­23] are tri-stated. 1.6.3 External Bus Control Table 1-8. External Bus Control Signals Signal Name Type State During Reset Signal Description AA0/RAS0­ AA3/RAS3 Output Tri-stated Address Attribute or Row Address Strobe As AA, these signals function as chip selects or additional address lines. Unlike address lines, however, the AA lines do not hold their state after a read or write operation. As RAS, these signals can be used for Dynamic Random Access Memory (DRAM) interface. These signals have programmable polarity. RD Output Tri-stated Read Enable When the DSP is the bus master, RD is asserted to read external memory on the data bus (D[0­23]). Otherwise, RD is tri-stated. WR Output Tri-stated Write Enable When the DSP is the bus master, WR is asserted to write external memory on the data bus (D[0­23]). Otherwise, WR is tri-stated. TA Input Ignored Input Transfer Acknowledge If the DSP56305 DSP56305 is the bus master and there is no external bus activity, or the DSP56305 DSP56305 is not the bus master, the TA input is ignored. The TA input is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2,., infinity) can be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, asserted to enable completion of the bus cycle, and deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the Bus Control Register (BCR), whichever is longer. The BCR can set the minimum number of wait states in external bus cycles. To use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion; otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the Operating Mode Register (OMR). TA functionality cannot be used during DRAM-type accesses; otherwise improper operation may result. 1-6 External Memory Expansion Port (Port A) Table 1-8. External Bus Control Signals (Continued) Signal Name Type State During Reset Signal Description BR Output Output (deasserted) Bus Request Asserted when the DSP requests bus mastership and deasserted when the DSP no longer needs the bus. BR can be asserted or deasserted independently of whether the DSP56305 DSP56305 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP56305 DSP56305 is the bus master (see the description of bus "parking" in the BB signal description). The Bus Request Hole (BRH) bit in the BCR allows BR to be asserted under software control, even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking and tenure of each master on the same external bus. BR is affected only by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. BG Input Ignored Input Bus Grant Must be asserted/deasserted synchronous to CLKOUT for proper operation. An external bus arbitration circuit asserts BG when the DSP56305 DSP56305 becomes the next bus master. When BG is asserted, the DSP56305 DSP56305 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. BB Input/ Output Input Bus Busy Indicates that the bus is active and must be asserted and deasserted synchronous to CLKOUT. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master can keep BB asserted after ceasing bus activity, regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to reuse the bus without re-arbitration until another device requires the bus. BB is deasserted by an "active pull-up" method (that is, BB is driven high and then released and held high by an external pull-up resistor). BB requires an external pull-up resistor. BL Output Driven high (deasserted) Bus Lock-BL is asserted at the start of an external divisible Read-Modify-Write (RMW) bus cycle, remains asserted between the read and write cycles, and is deasserted at the end of the write bus cycle. This provides an "early bus start" signal for the bus controller. BL may be used to "resource lock" an external multi-port memory for secure semaphore updates. Early deassertion provides an "early bus end" signal useful for external bus control. If the external bus is not used during an instruction cycle, BL remains deasserted until the next external indivisible RMW cycle. The only instructions that assert BL automatically are the BSET, CLR, and BCHG instructions when they are used to modify external memory. An operation can also assert BL by setting the BLH bit in the Bus Control Register. 1-7 Interrupt and Mode Control Table 1-8. External Bus Control Signals (Continued) Signal Name Type State During Reset Signal Description CAS Output Tri-stated Column Address Strobe When the DSP is the bus master, DRAM uses CAS to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM Control Register is cleared, the signal is tri-stated. BCLK Output Tri-stated Bus Clock When the DSP is the bus master, BCLK is active when the OMR[ATE] is set. When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. BCLK Output Tri-stated Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. 1.7 Interrupt and Mode Control The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 1-9. Interrupt and Mode Control Signal Name MODA Type Input State During Reset Input Signal Description Mode Select A Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQA during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. Input IRQA External Interrupt Request A Internally synchronized to CLKOUT. If IRQA is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQA to exit the Wait state. If the processor is in the Stop stand-by state and IRQA is asserted, the processor exits the Stop state. These inputs are 5 V tolerant. 1-8 Interrupt and Mode Control Table 1-9. Interrupt and Mode Control (Continued) Signal Name Type MODB Input IRQB State During Reset Input Input Signal Description Mode Select B Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQB during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request B Internally synchronized to CLKOUT. If IRQB is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the Wait state. If the processor is in the Stop stand-by state and IRQC is asserted, the processor will exit the Stop state. These inputs are 5 V tolerant. MODC Input IRQC Input Input Mode Select C Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQC during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request C Internally synchronized to CLKOUT. If IRQC is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQC to exit the Wait state. If the processor is in the Stop stand-by state and IRQC is asserted, the processor exits the Stop state. These inputs are 5 V tolerant. MODD Input IRQD Input Input Mode Select D Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQD during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request D Internally synchronized to CLKOUT. If IRQD is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQD to exit the Wait state. If the processor is in the Stop stand-by state and IRQD is asserted, the processor exits the Stop state. These inputs are 5 V tolerant. 1-9 Host Interface (HI32) Table 1-9. Interrupt and Mode Control (Continued) Signal Name RESET State During Reset Type Input Input Signal Description Reset Deassertion of RESET is internally synchronized to the clock out (CLKOUT). When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in "lock-step." When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power-up. This input is 5 V tolerant. 1.8 Host Interface (HI32) The Host Interface (HI32) provides fast parallel data to a 32-bit port directly connected to the host bus. The HI32 supports a variety of standard buses and directly connects to a PCI bus and a number of industry-standard microcomputers, microprocessors, DSPs, and DMA hardware. 1.8.4 Host Port Usage Considerations Careful synchronization is required when the system reads multiple-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the Host port). The considerations for proper operation are discussed in Table 1-10. Table 1-10. Host Port Usage Considerations Action Description Asynchronous read of receive byte registers Asynchronous write to transmit byte registers Do not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set, indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the Host Receive (HRX) register. Asynchronous write to host vector 1-10 When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL), use interrupts or poll the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data in the receive byte registers is valid. Change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a stable vector. Host Interface (HI32) 1.8.5 Host Port Configuration HI32 signal functions vary according to the programmed configuration of the interface as determined by the 24-bit DSP Control Register (DCTR). Refer to the DSP56305 DSP56305 User's Manual for details on HI32 configuration registers. Table 1-11. Host Interface Signal Name Type State During Reset Tri-stated Signal Description HAD[0­7] Input/Output Host Address/Data 0­7 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 0­7 of the Address/Data bus. HA[3­10] Input Host Address 3­10 When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, these signals are lines 3­10 of the Address bus. PB[0­7] Input or Output Port B 0­7 When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed through the HI32 Data Direction Register (DIRH). These inputs are 5 V tolerant. Tri-stated Host Address/Data 8­15 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 8­15 of the Address/Data bus. HAD[8­15] Input/Output HD[0­7] Input/Output Host Data 0­7 When HI32 is programmed to interface with a universal non-PCI bus and the HI function is selected, these signals are lines 0­7 of the Data bus. PB[8­15] Input or Output Port B 8­15 When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed through the HI32 DIRH. These inputs are 5 V tolerant. 1-11 Host Interface (HI32) Table 1-11. Host Interface (Continued) Signal Name Type HC[0­3]/ HBE[0­3] Input/Output HA[0­2] State During Reset Input Tri-stated Signal Description Command 0­3/Byte Enable 0­3 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 0­7 of the Address/Data bus. Host Address 0­2 When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, these signals are lines 0­2 of the Address bus. The fourth signal in this set should connect to a pull-up resistor or directly to VCC when a non-PCI bus is used. PB[16­19] Port B 16­19 When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed through the HI32 DIRH. Input or Output These inputs are 5 V tolerant. HTRDY Input/ Output HDBEN Output Host Data Bus Enable When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Bus Enable signal. PB20 Input or Output Port B 20 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. Tri-stated Host Target Ready When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Target Ready signal. This input is 5 V tolerant. HIRDY Input/ Output HDBDR Output Host Data Bus Direction When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Bus Direction signal. PB21 Input or Output Port B 21 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. Tri-stated Host Initiator Ready When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Initiator Ready signal. This input is 5 V tolerant. 1-12 Host Interface (HI32) Table 1-11. Host Interface (Continued) Signal Name Type State During Reset Tri-stated Signal Description HDEVSEL Input/ Output Host Device Select When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Device Select signal. HSAK Output Host Select Acknowledge When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Select Acknowledge signal. PB22 Input or Output Port B 22 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input is 5 V tolerant. HLOCK Input Tri-stated Host Lock When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Lock signal. HBS Input Host Bus Strobe When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Bus Strobe Schmitt-trigger signal. PB23 Input or Output Port B 23 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input is 5 V tolerant. HPAR Input/ Output HDAK Input Tri-stated Host Parity When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Parity signal. Host DMA Acknowledge When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host DMA Acknowledge Schmitt-trigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. 1-13 Host Interface (HI32) Table 1-11. Host Interface (Continued) Signal Name Type HPERR Input/ Output HDRQ State During Reset Tri-stated Output Signal Description Host Parity Error When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Parity Error signal. Host DMA Request When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host DMA Request output. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. HGNT Input HAEN Input Input Host Bus Grant When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Bus Grant signal. Host Address Enable When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Address Enable output signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. HREQ Output HTA Output Tri-stated Host Bus Request When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Bus Request signal. Host Transfer Acknowledge-When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Bus Enable signal. HTA can be programmed as active high or active low. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. 1-14 Host Interface (HI32) Table 1-11. Host Interface (Continued) Signal Name Type HSERR Output, open drain HIRQ State During Reset Tri-stated Output, open drain Signal Description Host System Error When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host System Error signal. Host Interrupt Request When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Interrupt Request signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. HSTOP Input/ Output HWR/HRW Input Tri-stated Host Stop When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Stop signal. Host Write/Host Read-Write When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Write/Host Read-Write Schmitt-trigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. HIDSEL Input HRD/HDS Input Input Host Initialization Device Select When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Initialization Device Select signal. Host Read/Host Data Strobe When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Read/Host Data Strobe Schmitt-trigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. 1-15 Host Interface (HI32) Table 1-11. Host Interface (Continued) Signal Name HFRAME Type Input/ Output State During Reset Tri-stated Signal Description Host Frame When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host cycle Frame signal. Non-PCI bus When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly to VCC. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. HCLK Input Input Host Clock When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Bus Clock input. Non-PCI bus When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly to VCC. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. HAD[16­31] Input/Output HD[8­23] Input/Output Tri-stated Host Address/Data 16­31 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 16­31 of the Address/Data bus. Host Data 8­23 When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, these signals are lines 8­23 of the Data bus. Port B When the HI32 is configured as GPIO through the DCTR, these signals are internally disconnected. These inputs are 5 V tolerant. 1-16 Host Interface (HI32) Table 1-11. Host Interface (Continued) Signal Name Type HRST Input HRST State During Reset Tri-stated Input Signal Description Hardware Reset When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Hardware Reset input. Hardware Reset When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Hardware Reset Schmitt-trigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. HINTA Output, open drain Tri-stated Host Interrupt A When the HI function is selected, this signal is the Interrupt A open-drain output. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant. PVCL Input Input PCI Voltage Clamp When the HI32 is programmed to interface with a PCI bus and the HI function is selected and the PCI bus uses a 3 V signal environment, connect this pin to VCC (3.3 V) to enable the high voltage clamping required by the PCI specifications. In all other cases, including a 5 V PCI signal environment, leave the input unconnected. 1-17 Enhanced Synchronous Serial Interface 0 (ESSI0) 1.9 Enhanced Synchronous Serial Interface 0 (ESSI0) Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard CODECs, other DSPs, microprocessors, and peripherals that implement the Motorola Serial Peripheral Interface (SPI). Table 1-12. Enhanced Synchronous Serial Interface 0 (ESSI0) Signal Name SC00 Type Input or Output State During Reset Input PC0 Signal Description Serial Control 0 Functions in either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is either for Transmitter 1 output or Serial I/O Flag 0. Port C 0 The default configuration following reset is GPIO. For PC0, signal direction is controlled through the Port Directions Register (PRR0). The signal can be configured as ESSI signal SC00 through the Port Control Register (PCR0). This input is 5 V tolerant. SC01 Input/Output PC1 Input Input or Output Serial Control 1 Functions in either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receiver frame sync I/O. For Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag 1. Port C 1 The default configuration following reset is GPIO. For PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0. This input is 5 V tolerant. SC02 Input/Output PC2 Input or Output Input Serial Control Signal 2 The frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2 The default configuration following reset is GPIO. For PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. This input is 5 V tolerant. 1-18 Enhanced Synchronous Serial Interface 0 (ESSI0) Table 1-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued) Signal Name SCK0 Type Input/Output State During Reset Input Signal Description Serial Clock Provides the serial bit rate clock for the ESSI interface for both the transmitter and receiver in Synchronous modes, or the transmitter only in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6 T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PC3 Port C 3 The default configuration following reset is GPIO. For PC3, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SCK0 through PCR0. Input or Output This input is 5 V tolerant. SRD0 Input/Output PC4 Input Input or Output Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is being received. Port C 4 The default configuration following reset is GPIO. For PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0. This input is 5 V tolerant. STD0 Input/Output PC5 Input or Output Input Serial Transmit Data Transmits data from the serial transmit shift register. STD0 is an output when data is being transmitted. Port C 5 The default configuration following reset is GPIO. For PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. This input is 5 V tolerant. 1-19 Enhanced Synchronous Serial Interface 1 (ESSI1) 1.10 Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13. Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name SC10 Type Input or Output State During Reset Input Signal Description Serial Control 0 Selection of Synchronous or Asynchronous mode determines function. For Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is either Transmitter 1 output or Serial I/O Flag 0. Port D 0 The default configuration following reset is GPIO. For PD0, signal direction is controlled through the Port Directions Register (PRR1). The signal can be configured as an ESSI signal SC10 through the Port Control Register (PCR1). PD0 This input is 5 V tolerant. SC11 Input/Output PD1 Input Input or Output Serial Control 1 Selection of Synchronous or Asynchronous mode determines function. For Asynchronous mode, this signal is the receiver frame sync I/O. For Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag 1. Port D 1 The default configuration following reset is GPIO. For PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1. This input is 5 V tolerant. SC12 Input/Output PD2 Input or Output Input Serial Control Signal 2 Frame sync for both the transmitter and receiver in Synchronous mode, for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in Synchronous operation). Port D 2 The default configuration following reset is GPIO. For PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1. This input is 5 V tolerant. 1-20 Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued) Signal Name SCK1 Type Input/Output State During Reset Input Signal Description Serial Clock Provides the serial bit rate clock for the ESSI interface. Clock input or output can be used by the transmitter and receiver in Synchronous modes, by the transmitter only in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PD3 Port D 3 The default configuration following reset is GPIO. For PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. Input or Output This input is 5 V tolerant. SRD1 Input/Output PD4 Input Input or Output Serial Receive Data Receives serial data and transfers it to the ESSI receive shift register. SRD1 is an input when data is being received. Port D 4 The default configuration following reset is GPIO. For PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1. This input is 5 V tolerant. STD1 Input/Output PD5 Input or Output Input Serial Transmit Data Transmits data from the serial transmit shift register. STD1 is an output when data is being transmitted. Port D 5 The default configuration following reset is GPIO. For PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1. This input is 5 V tolerant. 1-21 Serial Communication Interface (SCI) 1.11 Serial Communication Interface (SCI) The Serial Communication interface (SCI) provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. Table 1-14. Serial Communication Interface (SCI) Signal Name Type RXD Input PE0 State During Reset Input Input or Output Signal Description Serial Receive Data Receives byte-oriented serial data and transfers it to the SCI receive shift register. Port E 0 The default configuration following reset is GPIO. When configured as PE0, signal direction is controlled through the SCI Port Directions Register (PRR). The signal can be configured as an SCI signal RXD through the SCI Port Control Register (PCR). This input is 5 V tolerant. TXD Output PE1 Input Input or Output Serial Transmit Data Transmits data from SCI transmit data register. Port E 1 The default configuration following reset is GPIO. When configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR. This input is 5 V tolerant. SCLK Input/Output PE2 Input or Output Input Serial Clock Provides the input or output clock used by the transmitter and/or the receiver. Port E 2 The default configuration following reset is GPIO. For PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR. This input is 5 V tolerant. 1-22 Timers 1.12 Timers The DSP56305 DSP56305 has three identical and independent timers. Each can use internal or external clocking, interrupt the DSP56305 DSP56305 after a specified number of events (clocks), or signal an external device after counting a specific number of internal events. Table 1-15. Triple Timer Signals Signal Name TIO0 Type Input or Output State During Reset Input Signal Description Timer 0 Schmitt-Trigger Input/Output As an external event counter or in Measurement mode, TIO0 is input. In Watchdog, Timer, or Pulse Modulation mode, TIO0 is output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 0 Control/Status Register (TCSR0). This input is 5 V tolerant. TIO1 Input or Output Input Timer 1 Schmitt-Trigger Input/Output As an external event counter or in Measurement mode, TIO1 is input. In Watchdog, Timer, or Pulse Modulation mode, TIO1 is output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 1 Control/Status Register (TCSR1). This input is 5 V tolerant. TIO2 Input or Output Input Timer 2 Schmitt-Trigger Input/Output As an external event counter or in Measurement mode, TIO2 is input. In Watchdog, Timer, or Pulse Modulation mode, TIO2 is output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 2 Control/Status Register (TCSR2). This input is 5 V tolerant. 1-23 JTAG/OnCE Interface 1.13 JTAG/OnCE Interface Table 1-16. JTAG/OnCE Interface Signal Name TCK Type Input State During Reset Input Signal Description Test Clock A test clock signal for synchronizing JTAG test logic. This input is 5 V tolerant. TDI Input Input Test Data Input A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TDO Output Tri-stated Test Data Output A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. This input is 5 V tolerant. TMS Input Input Test Mode Select Sequences the test controller's state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. This input is 5 V tolerant. TRST Input Input Test Reset Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted after power up. This input is 5 V tolerant. DE Input/Output Input Debug Event Provides a way to enter Debug mode from an external command controller (as input) or to acknowledge that the chip has entered Debug mode (as output). When asserted as an input, DE causes the DSP56300 DSP56300 core to finish the current instruction, save the instruction pipeline information, enter Debug mode, and wait for commands from the debug serial input line. When a debug request or a breakpoint condition causes the chip to enter Debug mode, DE is asserted as an output for three clock cycles. DE has an internal pull-up resistor. DE is not a standard part of the JTAG Test Access Port (TAP) Controller. It connects to the OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode. All other interface with the OnCE module must occur through the JTAG port. This input is 5 V tolerant. 1-24 Chapter 2 Specifications 2.1 Introduction The DSP56305 DSP56305 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. 2.2 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification never occurs in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. 2-1 Absolute Maximum Ratings 2.3 Absolute Maximum Ratings Table 2-1. Maximum Ratings Rating1 Symbol Value1, 2 Unit Supply Voltage VCC -0.3 to +4.0 V All input voltages excluding "5 V tolerant" inputs3 VIN GND - 0.3 to VCC + 0.3 V All "5 V tolerant" input voltages3 VIN5 GND - 0.3 to VCC + 3.95 V I 10 mA TJ -40 to +100 °C TSTG -55 to +150 °C Current drain per pin excluding VCC and GND Operating temperature range Storage temperature Notes: 1. 2. 3. GND = 0 V, VCC = 3.3 V ± 0.3 V, TJ = ­40°C to +100°C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. CAUTION: All "5 V Tolerant" input voltages cannot be more than 3.95 V greater than the supply voltage; this restriction applies to "power on," as well as during normal operation. In any case, the input voltages must not be higher than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V. 2.4 Thermal Characteristics Table 2-2. Thermal Characteristics Symbol PBGA3 Value PBGA4 Value Unit Junction-to-ambient thermal resistance1 RJA or JA 48.4 25.2 °C/W Junction-to-case thermal resistance2 RJC or JC 9 - °C/W Thermal characterization parameter JT 5 - °C/W Characteristic Notes: 1. 2. 3. 4. 2-2 Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per JEDEC Specification JESD51-3 JESD51-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 G30-88, with the exception that the cold plate temperature is used for the case temperature. These are simulated values. See note 1 for test board conditions. These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid ground planes internal to the test board. DC Electrical Characteristics 2.5 DC Electrical Characteristics Table 2-3. DC Electrical Characteristics6 Characteristics Symbol Min Typ Max Unit VCC 3.0 3.3 3.6 V VIH VIHP 2.0 2.0 - - VCC 5.25 V V VIHX 0.8 × VCC - VCC V VIL VILP VILX ­0.3 ­0.3 ­0.3 - - - 0.8 0.8 0.2 × VCC V V V Input leakage current IIN ­10 - 10 µA High impedance (off-state) input current (@ 2.4 V / 0.4 V) ITSI ­10 - 10 µA Output high voltage · TTL (IOH = ­0.4 mA)5,7 · CMOS (IOH = ­10 µA)5 VOH 2.4 VCC ­ 0.01 - - - - V V Output low voltage · TTL (IOL = 1.6 mA, open-drain pins IOL = 6.7 mA)5,7 · CMOS (IOL = 10 µA)5 VOL - - - - 0.4 0.01 V V - - - 80 MHz 100 MHz 102 127 6 7.5 100 100 - - - mA mA µA - 1 2.5 mA - - 10 pF Supply voltage Input high voltage · D[0­23], BG, BB, TA · MOD1/IRQ1, RESET, PINIT/NMI and all JTAG/ESSI/SCI/Timer/HI32 pins · EXTAL8 Input low voltage · D[0­23], BG, BB, TA, MOD1/IRQ1, RESET, PINIT · All JTAG/ESSI/SCI/Timer/HI32 pins · EXTAL8 Internal supply current2: · In Normal mode · In Wait mode3 · In Stop mode4 ICCI ICCW ICCS PLL supply current Input capacitance5 Notes: 1. 2. 3. 4. 5. 6. 7. 8. CIN Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins. Power Consumption Considerations on page 4-3 provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.0 V at TJ = 100°C. To obtain these results, all inputs must be terminated (that is, not allowed to float). To obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that is, not allowed to float). PLL and XTAL signals are disabled during Stop state. Periodically sampled and not 100 percent tested. VCC = 3.3 V ± 0.3 V; TJ = ­40°C to +100 °C, CL = 50 pF This characteristic does not apply to XTAL and PCAP. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 × VCC and the maximum VILX should be no higher than 0.1 × VCC. 2-3 AC Electrical Characteristics 2.6 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of Table 2-3. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal's transition. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed. All specifications for the high impedance state are guaranteed by design. 2.6.1 Internal Clocks Table 2-4. Internal Clocks, CLKOUT Expression1, 2 Characteristics Symbol Min Typ Max Internal operation frequency and CLKOUT with PLL enabled f - (Ef × MF)/ (PDF × DF) - Internal operation frequency and CLKOUT with PLL disabled f - Ef/2 - TH - 0.49 × ETC × PDF × DF/MF ETC - - 0.51 × ETC × PDF × DF/MF 0.47 × ETC × PDF × DF/MF - 0.53 × ETC × PDF × DF/MF - 0.49 × ETC × PDF × DF/MF ETC - - 0.51 × ETC × PDF × DF/MF 0.47 × ETC × PDF × DF/MF - 0.53 × ETC × PDF × DF/MF Internal clock and CLKOUT high period · With PLL disabled · With PLL enabled and MF 4 · With PLL enabled and MF > 4 Internal clock and CLKOUT low period · With PLL disabled · With PLL enabled and MF 4 · TL With PLL enabled and MF > 4 Internal clock and CLKOUT cycle time with PLL enabled TC - ETC × PDF × DF/MF - Internal clock and CLKOUT cycle time with PLL disabled TC - 2 × ETC - Instruction cycle time Notes: 1. 2. 2-4 ICYC - TC - DF = Division Factor; Ef = External frequency; ETC = External clock cycle = 1/Ef; MF = Multiplication Factor; PDF = Predivision Factor; TC = Internal clock cycle See the PLL and Clock Generator section in the DSP56300 DSP56300 Family Manual for details on the PLL. AC Electrical Characteristics 2.6.2 External Clock Operation The DSP56305 DSP56305 system clock is derived from the on-chip oscillator or it is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1. EXTAL XTAL EXTAL XTAL R R2 R1 C XTAL1 C Note: Make sure that in the PCTL Register: · XTLD (bit 16) = 0 · If fOSC 200 kHz, XTLR (bit 15) = 1 Fundamental Frequency Fork Crystal Oscillator C Note: Make sure that in the PCTL Register: · XTLD (bit 16) = 0 · If fOSC > 200 kHz, XTLR (bit 15) = 0 C XTAL1 Fundamental Frequency Crystal Oscillator Suggested Component Values: fOSC = 4 MHz fOSC = 20 MHz R = 680 k ± 10% R = 680 k ± 10% C = 56 pF ± 20% C = 22 pF ± 20% Suggested Component Values: fOSC = 32.768 kHz R1 = 3.9 M ± 10% C = 22 pF ± 20% R2 = 200 k ± 10% Calculations were done for a 32.768 kHz crystal with the following parameters: · load capacitance (CL) of 12.5 pF, · shunt capacitance (C0) of 1.8 pF, · series resistance of 40 k, and · drive level of 1 µW. Calculations were done for a 4/20 MHz crystal with the following parameters: · CLof 30/20 pF, · C0 of 7/6 pF, · series resistance of 100/20 , and · drive level of 2 mW. Figure 2-1. Crystal Oscillator Circuits If an externally supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by setting XTLD (PCTL Register bit 16 = 1-see the DSP56301 DSP56301 User's Manual). The external square wave source connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship between the EXTAL input and the internal clock and CLKOUT. Midpoint EXTAL VILX ETH ETL 2 Note: 3 4 5 ETC VIHX The midpoint is 0.5 (VIHX + VILX). 5 CLKOUT with PLL disabled 7 CLKOUT with PLL enabled 6a 6b 7 Figure 2-2. External Clock Timing 2-5 AC Electrical Characteristics Table 2-5. Clock Operation 80 MHz No. Characteristics 100 MHz Symbol Min Max Min Max Ef 0 80.0 MHz 0 100.0 MHz 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. 2 EXTAL input high1, 2 · With PLL disabled (46.7%­53.3% duty cycle6) · With PLL enabled (42.5%­57.5% duty cycle6) ETH 5.84 ns 5.31 ns 157.0 µs 4.67 ns 4.25 ns 157.0 µs EXTAL input low1, 2 · With PLL disabled (46.7%­53.3% duty cycle6) · With PLL enabled (42.5%­57.5% duty cycle6) ETL 5.84 ns 5.31 ns 157.0 µs 4.67 ns 4.25 ns 157.0 µs EXTAL cycle time2 · With PLL disabled · With PLL enabled ETC 12.50 ns 12.50 ns 273.1 µs 10.00 ns 10.00 ns 273.1 µs 3 4 5 CLKOUT change from EXTAL fall with PLL disabled 4.3 ns 11.0 ns 4.3 ns 11.0 ns 6 a. CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz)3,5 0.0 ns 1.8 ns 0.0 ns 1.8 ns b. CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF 4, PDF 1, Ef / PDF > 15 MHz)3,5 0.0 ns 1.8 ns 0.0 ns 1.8 ns 25.0 ns 12.50 ns 8.53 µs 20.0 ns 10.00 ns 8.53 µs Instruction cycle time = ICYC = TC4 (see Table 2-4) (46.7%­53.3% duty cycle) · With PLL disabled · With PLL enabled 7 Notes: 1. 2. 3. 4. 5. 6. ICYC Measured at 50 percent of the input transition The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-6) and maximum MF. Periodically sampled and not 100 percent tested The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF. The skew is not guaranteed for any other MF value. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 2.6.3 Phase Lock Loop (PLL) Characteristics Table 2-6. PLL Characteristics 80 MHz 100 MHz Characteristics Unit Min Voltage Controlled Oscillator (VCO) frequency when PLL enabled (MF × Ef × 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP) · @ MF 4 · @ MF > 4 Note: 2-6 Max Min Max 30 160 30 200 MHz (MF × 580) - 100 MF × 830 (MF × 780) - 140 MF × 1470 (MF × 580) - 100 (MF × 780) - 140 pF MF × 830 MF × 1470 pF CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (680 × MF) ­ 120, for MF 4, or 1100 × MF, for MF > 4. AC Electrical Characteristics 2.6.4 Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 80 MHz No. Characteristics 100 MHz Expression Unit Min Max Min Max - - 26.0 - 26.0 ns 50 × ETC 1000 × ETC 75000 × ETC 75000 × ETC 2.5 × TC 2.5 × TC 625.0 12.5 1.0 1.0 31.3 31.3 - - - - - - 500.0 10.0 0.75 0.75 25.0 25.0 - - - - - - ns µs ms ms ns ns 3.25 × TC + 2.0 20.25 TC + 10.0 42.6 - - 263.1 34.5 - - 212.5 ns ns 7.4 - - 12.5 5.9 - - 10.0 ns ns 41.6 - - 258.1 33.5 - - 207.5 ns ns Mode select setup time 30.0 - 30.0 - ns 14 Mode select hold time 0.0 - 0.0 - ns 15 Minimum edge-triggered interrupt request assertion width 8.25 - 6.6 - ns 16 Minimum edge-triggered interrupt request deassertion width 8.25 - 7.1 - ns 17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid · Caused by first interrupt instruction fetch 4.25 × TC + 2.0 7.25 × TC + 2.0 · Caused by first interrupt instruction execution 55.1 92.6 - - 44.5 74.5 - - ns ns 130.0 - 105.0 - ns 8 9 10 11 12 13 Delay from RESET assertion to all pins at reset value3 duration4 Required RESET · Power on, external clock generator, PLL disabled · Power on, external clock generator, PLL enabled · Power on, internal oscillator · During STOP, XTAL disabled (PCTL Bit 16 = 0) · During STOP, XTAL enabled (PCTL Bit 16 = 1) · During normal operation Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 · Minimum · Maximum Synchronous reset setup time from RESET deassertion to CLKOUT Transition 1 · Minimum · Maximum Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output · Minimum · Maximum TC 3.25 × TC + 1.0 20.25 × TC + 1.0 18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution 10 × TC + 5.0 19 Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1 - 80 MHz: 3.75 × TC + WS × TC ­ 12.4 100 MHz: 3.75 × TC + WS × TC ­ 10.94 Note 8 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1 - 80 MHz: 3.25 × TC + WS × TC ­ 12.4 100 MHz: 3.25 × TC + WS × TC ­ 10.94 Note 8 20 ns - Note 8 ns ns - Note 8 ns 2-7 AC Electrical Characteristics Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 80 MHz No. Characteristics Unit Min 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1 · DRAM for all WS7 · · · SRAM WS = 1 SRAM WS = 2, 3 SRAM WS 4 22 Synchronous interrupt delay time from the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state · Minimum · Maximum 80 MHz: (WS + 3.5) × TC ­ 12.4 100 MHz: (WS + 3.5) × TC ­ 10.94 80 MHz: (WS + 3.5) × TC ­ 12.4 100 MHz: (WS + 3.5) × TC ­ 10.94 80 MHz: (WS + 3) × TC ­ 12.4 100 MHz: (WS + 3) × TC ­ 10.94 80 MHz: (WS + 2.5) × TC ­ 12.4 100 MHz: (WS + 2.5) × TC ­ 10.94 24 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 · PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) · · 26 PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 · PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) · · 27 2-8 PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) Interrupt Request Rate · HI32, ESSI, SCI, Timer · DMA · IRQ, NMI (edge trigger) · IRQ, NMI (level trigger) - Min Note 8 ns - - ns ns Note 8 Note 8 ns ns - - Note 8 Note 8 - - Max Note 8 Note 8 ns ns - Note 8 ns PLC × ETC × PDF + (128 K - PLC/2) × TC TC 5.9 TC ns 116.6 - - 314.4 83.5 - - 252.5 ns ns 7.4 8.25 × TC + 1.0 24.75 × TC + 5.0 Duration for IRQA assertion to recover from Stop state 25 Max 7.4 Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 23 100 MHz Expression - 5.9 - ns 1.6 17.0 1.3 13.6 ms 232.5 ns 12.3 ms PLC × ETC × PDF + (23.75 ± 290.6 ns 15.4 ms 0.5) × TC (9.25 ± 0.5) × TC 109.4 121.9 87.5 97.5 ns PLC × ETC × PDF + (128K - PLC/2) × TC 17.0 - 13.6 - ms PLC × ETC × PDF + (20.5 ± 0.5) × TC 15.4 - 12.3 - ms 5.5 × TC 68.8 - 55.0 - ns 12 × TC 8 × TC 8 × TC 12 × TC - - - - 150.0 100.0 100.0 150.0 - - - - 120.0 80.0 80.0 120.0 ns ns ns ns AC Electrical Characteristics Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 80 MHz No. Characteristics 100 MHz Expression Unit Min 28 29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid Notes: 1. 2. 3. 4. 5. 6. 7. 8. Min Max 6 × TC 7 × TC 2 × TC 3 × TC DMA Request Rate · Data read from HI32, ESSI, SCI · Data write to HI32, ESSI, SCI · Timer · IRQ, NMI (edge trigger) Max - - - - 75.0 87.5 25.0 37.5 - - - - 60.0 70.0 20.0 30.0 ns ns ns ns 4.25 × TC + 2.0 55.1 - 44.5 - ns When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. This timing depends on several settings: · For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee timings for that case. · For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored). · For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the PCTL Bit 17 and Operating Mode Register Bit 6 settings. · For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. · PLC value for PLL disable is 0. · The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66 MHz = 62 µs). During the stabilization period, TC, TH, and TL is not constant, and their width may vary, so timing may vary as well. Periodically sampled and not 100 percent tested. Value depends on clock source: · For an external clock generator, RESET duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is active and valid. · For an internal oscillator, RESET duration is measured while RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. · When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock. VCC = 3.3 V ± 0.3 V; TJ = ­40°C to +100°C, CL = 50 pF. WS = number of wait states (measured in clock cycles, number of TC). Use the expression to compute a maximum value. RESET VIH 9 10 8 All Pins Reset Value A[0­23] First Fetch Figure 2-3. Reset Timing 2-9 AC Electrical Characteristics CLKOUT 11 RESET 12 A[0­23] Figure 2-4. Synchronous Reset Timing First Interrupt Instruction Execution/Fetch A[0­23] RD 20 WR 21 IRQA, IRQB, IRQC, IRQD, NMI 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General-Purpose I/O Figure 2-5. External Fast Interrupt Timing 2-10 AC Electrical Characteristics IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI 16 Figure 2-6. External Interrupt Timing (Negative Edge-Triggered) CLKOUT IRQA, IRQB, IRQC, IRQD, NMI 22 23 A[0­23] Figure 2-7. Synchronous Interrupt from Wait State Timing VIH RESET 13 14 MODA, MODB, MODC, MODD, PINIT VIH VIH IRQA, IRQB, IRQC, IRQD, NMI VIL VIL Figure 2-8. Operating Mode Select Timing 2-11 AC Electrical Characteristics 24 IRQA 25 First Instruction Fetch A[0­23] Figure 2-9. Recovery from Stop State Using IRQA 26 IRQA 25 First IRQA Interrupt Instruction Fetch A[0­23] Figure 2-10. Recovery from Stop State Using IRQA Interrupt Service DMA Source Address A[0­23] RD WR 29 IRQA, IRQB, IRQC, IRQD, NMI First Interrupt Instruction Execution Figure 2-11. External Memory Access (DMA Source) Timing 2-12 AC Electrical Characteristics 2.6.5 External Memory Expansion Port (Port A) 2.6.5.1 SRAM Timing Table 2-8. SRAM Read and Write Accesses3,6 80 MHz No. Characteristics Symbol 100 MHz Expression1 Unit Min Max Min Max 100 Address valid and AA assertion pulse width2 tRC, tWC (WS + 1) × TC - 4.0 [1 WS 3] (WS + 2) × TC - 4.0 [4 WS 7] (WS + 3) × TC - 4.0 [WS 8] 21.0 71.0 133.5 - - - 16.0 56.0 106.0 - - - ns ns ns 101 Address and AA valid to WR assertion tAS 0.25 × TC - 2.0 [WS = 1] 0.75 × TC - 2.0 [2 WS 3] 1.25 × TC - 2.0 [WS 4] 1.1 7.4 13.6 - - - 0.5 5.5 10.5 - - - ns ns ns 102 WR assertion pulse width tWP 1.5 × TC - 4.0 [WS = 1] WS × TC - 4.0 [2 WS 3] (WS - 0.5) × TC - 4.0 [WS 4] 14.8 21.0 39.8 - - - 11.0 16.0 31.0 - - - ns ns ns 103 WR deassertion to address not valid tWR 0.25 × TC - 2.0 [1 WS 3] 1.25 × TC - 4.0 [4 WS 7] 2.25 × TC - 4.0 [WS 8] 1.1 11.6 24.1 - - - 0.5 8.5 18.5 - - - ns ns ns 104 Address and AA valid to input data valid tAA, tAC 80 MHz: (WS + 0.75) × TC - 9.5 [WS 1] 100 MHz: (WS + 0.75) × TC - 5.0 [WS 1] - 16.9 - - ns - - - 12.5 ns - 10.6 - - ns - - - 7.5 ns 0.0 - 0.0 - ns 105 RD assertion to input data valid tOE 80 MHz: (WS + 0.25) × TC - 9.5 [WS 1] 100 MHz: (WS + 0.25) × TC - 5.0 [WS 1] 106 RD deassertion to data not valid (data hold time) tOHZ 107 Address valid to WR deassertion2 tAW (WS + 0.75) × TC - 4.0 [WS 1] 17.9 - 13.5 - ns 108 Data valid to WR deassertion (data setup time) tDS (tDW) (WS - 0.25) × TC - 3.0 [WS 1] 6.4 - 4.5 - ns 109 Data hold time from WR deassertion tDH 0.25 × TC - 2.0 [1 WS 3] 1.25 × TC - 2.0 [4 WS 7] 2.25 × TC - 2.0 [WS 8] 1.1 13.6 26.1 - - - 0.5 10.5 20.5 - - - ns ns ns 110 WR assertion to data active 0.75 × TC - 3.7 [WS = 1] 0.25 × TC - 3.7 [2 WS 3] -0.25 × TC - 3.7 [WS 4] 5.7 ­0.6 ­6.8 - - - 3.8 ­1.2 ­6.2 - - - ns ns ns 111 WR deassertion to data high impedance 0.25 × TC + 0.2 [1 WS 3] 1.25 × TC + 0.2 [4 WS 7] 2.25 × TC + 0.2 [WS 8] - - - 3.3 15.8 28.3 - - - 2.7 12.7 22.7 ns ns ns 2-13 AC Electrical Characteristics Table 2-8. SRAM Read and Write Accesses3,6 (Continued) 80 MHz No. Characteristics Symbol 100 MHz Expression1 Unit Min Max Min Max 112 Previous RD deassertion to data active (write) 1.25 × TC - 4.0 [1 WS 3] 2.25 × TC - 4.0 [4 WS 7] 3.25 × TC - 4.0 [WS 8] 11.6 24.1 36.6 - - - 8.5 18.5 28.5 - - - ns ns ns 113 RD deassertion time 0.75 × TC - 4.0 [1 WS 3] 1.75 × TC - 4.0 [4 WS 7] 2.75 × TC - 4.0 [WS 8] 5.4 17.9 30.4 - - - 3.5 13.5 23.5 - - - ns ns ns 114 WR deassertion time 0.5 × TC - 4.0 [WS = 1] TC - 4.0 [2 WS 3] 2.5 × TC - 4.0 [4 WS 7] 3.5 × TC - 4.0 [WS 8] 2.3 8.5 27.3 39.8 - - - - 1.0 6.0 21.0 31.0 - - - - ns ns ns ns 115 Address valid to RD assertion 0.5 × TC - 4.0 2.3 - 1.0 - ns 116 RD assertion pulse width (WS + 0.25) × TC -4.0 11.6 - 8.5 - ns 117 RD deassertion to address not valid 0.25 × TC - 2.0 [1 WS 3] 1.25 × TC - 2.0 [4 WS 7] 2.25 × TC - 2.0 [WS 8] 1.1 13.6 26.1 - - - 0.5 10.5 20.5 - - - ns ns ns 118 TA setup before RD or WR deassertion4 0.25 × TC + 2.0 5.1 - 4.5 - ns 119 TA hold after RD or WR deassertion 0 - 0 - ns Notes: 2-14 1. 2. 3. 4. 5. 6. WS is the number of wait states specified in the BCR. Timings 100, 107 are guaranteed by design, not tested. All timings for 100 MHz are measured from 0.5 · Vcc to 0.5 · Vcc Timing 118 is relative to the deassertion edge of RD or WR even if TA remains active. Timings 110, 111, and 112, are not helpful and are not specified for 100 MHz. VCC = 3.3 V ± 0.3 V; TJ = ­40°C to +100°C, CL = 50 pF AC Electrical Characteristics 100 A[0­23] AA[0­3] 113 117 116 RD 105 106 WR 104 118 119 TA Data In D[0­23] Note: Address lines A[0­23] hold their state after a read or write operation. AA[0­3] do not hold their state after a read or write operation. Figure 2-12. SRAM Read Access 100 A[0­23] AA[0­3] 107 101 102 103 WR 114 RD 119 118 TA 108 109 Data Out D[0­23] Note: Address lines A[0­23] hold their state after a read or write operation. AA[0­3] do not hold their state after a read or write operation. Figure 2-13. SRAM Write Access 2-15 AC Electrical Characteristics 2.6.5.2 DRAM Timing The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based on the timing in the following tables. For example, the selection guide suggests that four wait states must be used for 100 MHz operation in Page Mode DRAM. However, using the information in the appropriate table, a designer could choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, by running the chip at a slightly lower frequency (for example, 95 MHz), by using faster DRAM (if it becomes available), and by manipulating control factors such as capacitive and resistive load to improve overall system performance. DRAM type (tRAC ns) Note: This figure should be used for primary selection. For exact and detailed timings see the following tables. 100 80 70 60 50 40 66 80 100 120 Chip frequency (MHz) 1 Wait state 3 Wait states 2 Wait states 4 Wait states Figure 2-14. DRAM Page Mode Wait States Selection Guide 2-16 AC Electrical Characteristics Table 2-9. DRAM Page Mode Timings, Two Wait States1, 2, 3, 7 80 MHz No. Characteristics Symbol Expression Unit Min 131 3 × TC Page mode cycle time for two consecutive accesses of the same direction Max 37.5 - ns Page mode cycle time for mixed (read and write) accesses tPC 2.75 × TC 34.4 - ns 132 CAS assertion to data valid (read) tCAC 1.5 × TC - 6.5 - 12.3 ns 133 Column address valid to data valid (read) tAA 2.5 × TC - 6.5 134 CAS deassertion to data not valid (read hold time) tOFF 135 Last CAS assertion to RAS deassertion tRSH 136 Previous CAS deassertion to RAS deassertion 137 138 - 24.8 ns 0.0 - ns 1.75 × TC - 4.0 17.9 - ns tRHCP 3.25 × TC - 4.0 36.6 - ns CAS assertion pulse width tCAS 1.5 × TC - 4.0 14.8 - ns Last CAS deassertion to RAS deassertion5 BRW[1­0] = 00 BRW[1­0] = 01 BRW[1­0] = 10 BRW[1­0] = 11 tCRP Not supported 3.5 × TC - 6.0 4.5 × TC - 6.0 6.5 × TC - 6.0 - 37.8 50.3 75.3 - - - - ns ns ns ns 139 CAS deassertion pulse width tCP 1.25 × TC - 4.0 11.6 - ns 140 Column address valid to CAS assertion tASC TC - 4.0 8.5 - ns 141 CAS assertion to column address not valid tCAH 1.75 × TC - 4.0 17.9 - ns 142 Last column address valid to RAS deassertion tRAL 3 × TC - 4.0 33.5 - ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC - 4 11.6 - ns 144 CAS deassertion to WR assertion tRCH 0.5 × TC - 3.7 2.6 - ns 145 CAS assertion to WR deassertion tWCH 1.5 × TC - 4.2 14.6 - ns 146 WR assertion pulse width tWP 2.5 × TC - 4.5 26.8 - ns 147 Last WR assertion to RAS deassertion tRWL 2.75 × TC - 4.3 30.1 - ns 148 WR assertion to CAS deassertion tCWL 2.5 × TC - 4.3 27.0 - ns 149 Data valid to CAS assertion (write) tDS 0.25 × TC - 3.0 0.1 - ns 150 CAS assertion to data not valid (write) tDH 1.75 × TC - 4.0 17.9 - ns 151 WR assertion to CAS assertion tWCS TC - 4.3 8.2 - ns 152 Last RD assertion to RAS deassertion tROH 2.5 × TC - 4.0 27.3 - ns 1.75 × TC - 6.5 153 RD assertion to data valid tGA 154 RD deassertion to data not valid6 tGZ 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. 7. - 15.4 ns 0.0 - ns 0.75 × TC - 1.5 7.9 - ns 0.25 × TC - 3.1 ns The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for the DSP56305 DSP56305. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 × TC for read-after-read or write-after-write sequences). BRW[1­0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. At this time, there are no DRAMs fast enough to fit with two wait states Page mode @ 100MHz (see Table 2-14). However, DRAM speeds are approaching two-wait-state compatibility. 2-17 AC Electrical Characteristics Table 2-10. DRAM Page Mode Timings, Three Wait States1, 2, 3 80 MHz No. Characteristics Symbol 100 MHz Expression Unit Min 131 Min Max 4 × TC Page mode cycle time for two consecutive accesses of the same direction Max 50.0 - 40.0 - ns Page mode cycle time for mixed (read and write) accesses tPC 3.5 × TC 43.7 - 35.0 - ns 132 CAS assertion to data valid (read) tCAC 2 × TC - 5.7 - 19.3 - 14.3 ns 133 Column address valid to data valid (read) tAA 3 × TC - 5.7 - 31.8 - 24.3 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 - 0.0 - ns 135 Last CAS assertion to RAS deassertion tRSH 2.5 × TC - 4.0 27.3 - 21.0 - ns 136 Previous CAS deassertion to RAS deassertion tRHCP 4.5 × TC - 4.0 52.3 - 41.0 - ns 137 CAS assertion pulse width tCAS 2 × TC - 4.0 21.0 - 16.0 - ns Not supported 3.75 × TC - 6.0 4.75 × TC - 6.0 6.75 × TC - 6.0 - 40.9 53.4 78.4 - - - - - 31.5 41.5 61.5 - - - - ns ns ns ns 138 Last CAS deassertion to RAS assertion · BRW[1­0] = 00 · BRW[1­0] = 01 · BRW[1­0] = 10 · BRW[1­0] = 11 5 tCRP 139 CAS deassertion pulse width tCP 1.5 × TC - 4.0 14.8 - 11.0 - ns 140 Column address valid to CAS assertion tASC TC - 4.0 8.5 - 6.0 - ns 141 CAS assertion to column address not valid tCAH 2.5 × TC - 4.0 27.3 - 21.0 - ns 142 Last column address valid to RAS deassertion tRAL 4 × TC - 4.0 46.0 - 36.0 - ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC - 4.0 11.6 - 8.5 - ns 144 CAS deassertion to WR assertion tRCH 0.75 × TC - 4.0 5.4 - 3.5 - ns 145 CAS assertion to WR deassertion tWCH 2.25 × TC - 4.2 23.9 - 18.3 - ns 146 WR assertion pulse width tWP 3.5 × TC - 4.5 39.3 - 30.5 - ns 147 Last WR assertion to RAS deassertion tRWL 3.75 × TC - 4.3 42.6 - 33.2 - ns 148 WR assertion to CAS deassertion tCWL 3.25 × TC - 4.3 36.3 - 28.2 - ns 149 Data valid to CAS assertion (write) tDS 0.5 × TC ­ 4.8 2.0 - 0.2 - ns 150 CAS assertion to data not valid (write) tDH 2.5 × TC - 4.0 27.3 - 21.0 - ns 151 WR assertion to CAS assertion tWCS 1.25 × TC - 4.3 11.3 - 8.2 - ns 152 Last RD assertion to RAS deassertion tROH 3.5 × TC - 4.0 39.8 - 31.0 - ns 153 RD assertion to data valid tGA 2.5 × TC - 5.7 - 25.6 - 19.3 ns 0.0 - 0.0 - ns 0.75 × TC ­ 1.5 7.9 - 6.0 - ns 0.25 × TC - 3.1 - 2.5 ns valid6 154 RD deassertion to data not 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. 2-18 tGZ The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56305 DSP56305. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 4 × TC for read-after-read or write-after-write sequences). BRW[1­0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. AC Electrical Characteristics Table 2-11. DRAM Page Mode Timings, Four Wait States1, 2, 3 80 MHz No. Characteristics Symbol 100 MHz Expression Unit Min 131 Min Max 5 × TC Page mode cycle time for two consecutive accesses of the same direction Max 62.5 - 50.0 - ns Page mode cycle time for mixed (read and write) accesses tPC 4.5 × TC 56.2 - 45.0 - ns 132 CAS assertion to data valid (read) tCAC 2.75 × TC - 5.7 - 28.7 - 21.8 ns 133 Column address valid to data valid (read) tAA 3.75 × TC - 5.7 - 41.2 - 31.8 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 - 0.0 - ns 135 Last CAS assertion to RAS deassertion tRSH 3.5 × TC - 4.0 39.8 - 31.0 - ns 136 Previous CAS deassertion to RAS deassertion tRHCP 6 × TC - 4.0 71.0 - 56.0 - ns 137 CAS assertion pulse width tCAS 2.5 × TC - 4.0 27.3 - 21.0 - ns Not supported 4.25 × TC - 6.0 5.25 × TC - 6.0 7.25 × TC - 6.0 - 47.2 59.6 84.6 - - - - - 36.5 46.5 66.5 - - - - ns ns ns ns 138 Last CAS deassertion to RAS assertion · BRW[1­0] = 00 · BRW[1­0] = 01 · BRW[1­0] = 10 · BRW[1­0] = 11 5 tCRP 139 CAS deassertion pulse width tCP 2 × TC - 4.0 21.0 - 16.0 - ns 140 Column address valid to CAS assertion tASC TC - 4.0 8.5 - 6.0 - ns 141 CAS assertion to column address not valid tCAH 3.5 × TC - 4.0 39.8 - 31.0 - ns 142 Last column address valid to RAS deassertion tRAL 5 × TC - 4.0 58.5 - 46.0 - ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC - 4.0 11.8 - 8.5 - ns 144 CAS deassertion to WR assertion tRCH 1.25 × TC ­ 3.7 11.9 - 8.8 - ns 145 CAS assertion to WR deassertion tWCH 3.25 × TC - 4.2 36.4 - 28.3 - ns 146 WR assertion pulse width tWP 4.5 × TC - 4.5 51.8 - 40.5 - ns 147 Last WR assertion to RAS deassertion tRWL 4.75 × TC - 4.3 55.1 - 43.2 - ns 148 WR assertion to CAS deassertion tCWL 3.75 × TC - 4.3 42.6 - 33.2 - ns 149 Data va