DSP56304/D DSP56304 DSP56300 24-BIT AA0853 DSP56000 DSP56300FM/AD DSP56304UM/AD - Datasheet Archive

 

SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56304/D DSP56304 Advance Information Motorola designed the ROM-based

 

MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56304/D DSP56304/D DSP56304 DSP56304 Advance Information Motorola designed the ROM-based DSP56304 DSP56304 to support multifunction wireless and embedded DSP applications. In addition to the large on-chip ROM spaces, the DSP56304 DSP56304 also has a ROM patch feature that facilitates updates to the on-chip mask Program ROM-based on-chip software. The DSP56304 DSP56304 includes a triple timer module, Host Interface (HI08), an Enhanced Synchronous Serial Interface (ESSI), and a Serial Communications Interface (SCI). The DSP56300 DSP56300 core family includes a Phase Lock Loop (PLL), External Memory Interface (EMI), Data Arithmetic Logic Unit (Data ALU), 24-bit addressing, instruction cache, and DMA. The DSP56304 DSP56304 offers 66/80 MIPS using an internal 66/80 MHz clock at 3.0­3.6 volts. 16 6 6 3 Memory Expansion Area SCI Interface PM_EB *default Peripheral Expansion Area Address Generation Unit Six Channel DMA Unit Y Data X Data RAM RAM 3328 × 24* 1792 × 24* ROM ROM 9216 × 24 9216 × 24 *default *default YAB XAB PAB DAB 24-Bit DSP56300 DSP56300 Core Bootstrap ROM YM_EB ESSI Interface Program RAM 1024 × 24* Program ROM 33792 × 24 XM_EB Triple Timer Host Interface HI08 PIO_EB Freescale Semiconductor, Inc. 24-BIT 24-BIT DIGITAL SIGNAL PROCESSOR External Address Bus Switch External Bus Interface & I-Cache Control 18 Address 13 Control DDB YDB Internal Data Bus Switch XDB PDB XTAL PLL 24 Data GDB EXTAL Clock Generator External Data Bus Switch Program Interrupt Controller 2 RESET PINIT/NMI Program Decode Controller Program Address Generator Power Mngmnt Data ALU 24 × 24 + 56 56-bit MAC JTAG Two 56-bit Accumulators OnCETM 56-bit Barrel Shifter MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1 DSP56304 DSP56304 Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. Preliminary Data ©1996 MOTOROLA, INC. For More Information On This Product, Go to: www.freescale.com 5 DE AA0853 AA0853 Freescale Semiconductor, Inc. TABLE OF CONTENTS SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 SECTION 5 Freescale Semiconductor, Inc. SECTION 1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 APPENDIX A POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . A-1 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Index-1 FOR TECHNICAL ASSISTANCE: Telephone: 1-800-521-6274 Email: dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) "asserted" Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN Note: Signal/Symbol False Deasserted VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. Preliminary Data ii DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56304 DSP56304 Features FEATURES DSP56304 DSP56304 FEATURES High Performance DSP56300 DSP56300 Core 66/80 Million Instructions Per Second (MIPS) with a 66/80 MHz clock · Object code compatible with the DSP56000 DSP56000 core · Highly parallel instruction set · Fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC) · 56-bit parallel barrel shifter · 24-bit or 16-bit arithmetic support under software control · Position independent code support · Addressing modes optimized for DSP applications · On-chip instruction cache controller · On-chip memory-expandable hardware stack · Nested hardware DO loops · Fast auto-return interrupts · On-chip concurrent six-channel DMA controller · On-chip Phase Lock Loop (PLL) and clock generator · On-Chip Emulation (OnCETM) module · JTAG Test Access Port (TAP) · Freescale Semiconductor, Inc. · Address Tracing mode reflects internal accesses at the external port Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com iii Freescale Semiconductor, Inc. DSP56304 DSP56304 DSP56304 DSP56304 Features On-chip Memories · Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable: Switch Mode Program RAM Size Instruction Cache Size X Data RAM Size Y Data RAM Size disabled disabled 1024 × 24-bit 0 3328 × 24-bit 1792 × 24-bit enabled disabled 0 1024 × 24-bit 3328 × 24-bit 1792 × 24-bit disabled Freescale Semiconductor, Inc. Instruction Cache enabled 3584 × 24-bit 0 2048 × 24-bit 512 × 24-bit enabled enabled 2560 × 24-bit 1024 × 24-bit 2048 × 24-bit 512 × 24-bit · 33, 792 × 24-bit Program ROM with Patch mode update capability using instruction cache memory space · 9,216 × 24-bit X data ROM and 9,216 × 24-bit Y data ROM · 192 × 24-bit bootstrap ROM Off-chip Memory Expansion · Data memory expansion to two 256 K × 24-bit word memory spaces (the usage of address attribute pins and/or DRAM interface may further extend the data memory expansion up to two 16 M × 24-bit words memory space) · Program memory expansion to one 256 K × 24-bit word memory space (the usage of address attribute pins and/or DRAM interface may further extend the program memory expansion up to two 16 M × 24-bit words memory space) · External memory expansion port · Chip select logic requires no additional circuitry to interface to SRAMs and SSRAMs · On-chip DRAM controller requires no additional circuitry to interface to DRAMs Preliminary Data iv DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56304 DSP56304 Target Applications On-chip Peripherals 8-bit parallel Host Interface (HI08), ISA-compatible bus interface, providing a cost-effective solution for applications not requiring the PCI bus · Two Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1) · Serial Communications Interface (SCI) with baud rate generator · Triple timer module · Freescale Semiconductor, Inc. · Up to thirty-four programmable General Purpose I/O pins (GPIO), depending on which peripherals are enabled Reduced Power Dissipation · Very low power CMOS design · Wait and Stop low power standby modes · Fully-static logic, operation frequency down to DC · Optimized power management circuitry TARGET APPLICATIONS The DSP56304 DSP56304 is intended for use in embedded multifunction DSP applications requiring large on-board ROM spaces, such as wireless products that combine standard cellular phone operation with options such as two-way digital paging and fax capability in one unit. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. DSP56304 DSP56304 Product Documentation PRODUCT DOCUMENTATION The three manuals listed in Table 1 are required for a complete description of the DSP56304 DSP56304 and are necessary to design with the part properly. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or the World Wide Web. Table 1 DSP56304 DSP56304 Documentation Freescale Semiconductor, Inc. Document Name Description of Contents Order Number DSP56300 DSP56300 Family Manual Detailed description of the DSP56300 DSP56300 family architecture and the 24-bit core processor and instruction set DSP56300FM/AD DSP56300FM/AD DSP56304 DSP56304 User's Manual Detailed description of DSP56304 DSP56304 memory, peripherals, and interfaces DSP56304UM/AD DSP56304UM/AD DSP56304 DSP56304 Technical Data DSP56304 DSP56304 pin and package descriptions, and electrical and timing specifications DSP56304/D DSP56304/D Preliminary Data vi DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS Freescale Semiconductor, Inc. SIGNAL GROUPINGS The input and output signals of the DSP56304 DSP56304 are organized into functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1. The DSP56304 DSP56304 is operated from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1 DSP56304 DSP56304 Functional Signal Groupings Number of Signals Detailed Description Power (VCC) 18 Table 1-2 Ground (GND) 19 Table 1-3 Clock 2 Table 1-4 PLL 3 Table 1-5 18 Table 1-6 24 Table 1-7 13 Table 1-8 5 Table 1-9 Port B 16 Table 1-11 Ports C and D3 12 Table 1-12 and Table 1-13 Port E4 3 Table 1-14 Timer 3 Table 1-15 OnCE/JTAG Port 6 Table 1-16 Functional Group Address Bus Port A1 Data Bus Bus Control Interrupt and Mode Control 2 Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Note: 1. 2. 3. 4. Port A signals define the External Memory Interface port, including the external address bus, data bus, and control signals. Port B signals are the HI08 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. Figure 1-1 is a diagram of DSP56304 DSP56304 signals by functional group. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. Signal/Connection Descriptions Signal Groupings DSP56304 DSP56304 Freescale Semiconductor, Inc. VCCP VCCQ VCCA VCCD VCCC VCCH VCCS GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS 4 4 4 2 2 Power Inputs: PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer Grounds: PLL PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer 4 4 4 2 2 EXTAL XTAL Clock CLKOUT PCAP PINIT/NMI PLL MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Interrupt/ Mode Control 8 Host Interface (HI08) Port1 Enhanced Synchronous Serial Interface Port 0 (ESSI0)2 3 Enhanced Synchronous Serial Interface Port 1 (ESSI1)2 3 NonMultiplexed Bus H0­H7 HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HREQ/HREQ HACK/HACK Multiplexed Bus HAD0­HAD7 HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ SC00­SC02 SCK0 SRD0 STD0 Port C GPIO PC0­PC2 PC3 PC4 PC5 SC10-SC12 SC10-SC12 SCK1 SRD1 STD1 Port D GPIO PD0-PD2 PD3 PD4 PD5 RXD TXD SCLK Port B GPIO PB0­PB7 PB8 PB9 PB10 PB13 Port E GPIO PE0 PE1 PE2 PB11 PB12 PB14 PB15 Port A A0­A17 D0­D23 AA0­AA3/ RAS0­RAS3 RD WR TA BR BG BB CAS BCLK BCLK Note: 1. 2. 3. 18 24 4 External Address Bus External Data Bus External Bus Control Serial Communications Interface (SCI) Port2 Timers3 OnCE/ JTAG Port TIO0 TIO1 TIO2 Timer GPIO TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE AA0601 AA0601 The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0­PB15). Signals with dual designations (e.g., HAS/ HAS) have configurable polarity. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0­PC5), Port D GPIO signals (PD0­PD5), and Port E GPIO signals (PE0­PE2), respectively. TIO0­TIO2 can be configured as GPIO signals. Figure 1-1 Signals Identified by Functional Group Preliminary Data 1-2 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Power POWER Table 1-2 Power Inputs Power Name Description PLL Power-VCCP is VCC dedicated for Phase Lock Loop (PLL) use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. VCCQ (4) Freescale Semiconductor, Inc. VCCP Quiet Power-VCCQ is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCQ inputs. VCCA (4) Address Bus Power-VCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCA inputs. VCCD (4) Data Bus Power-VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCD inputs. VCCC (2) Bus Control Power-VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCC inputs. VCCH Host Power-VCCH is an isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCH input. VCCS (2) ESSI, SCI, and Timer Power-VCCS is an isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCS inputs. Note: These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each other internally. On those packages, all power input, except VCCP, are labeled VCC. The numbers of connections indicated in this table are minimum values; the total VCC connections are package-dependent. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. Signal/Connection Descriptions Ground GROUND Table 1-3 Grounds Ground Name Description PLL Ground-GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package. There is one GNDP connection. GNDP1 Freescale Semiconductor, Inc. GNDP PLL Ground 1-GNDP1 is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. There is one GNDP1 connection. GNDQ (4) Quiet Ground-GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. GNDA (4) Address Bus Ground-GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. GNDD (4) Data Bus Ground-GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDD connections. GNDC (2) Bus Control Ground-GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDC connections. GNDH Host Ground-GNDH is an isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDH connection. GNDS (2) ESSI, SCI, and Timer Ground-GNDS is an isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDS connections. Note: These designations are package-dependent. Some packages connect all GND inputs, except GNDP and GNDP1, to each other internally. On those packages, all ground connections, except GNDP and GNDP1, are labeled GND. The numbers of connections indicated in this table are minimum values; the total GND connections are package-dependent. Preliminary Data 1-4 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Clock CLOCK Table 1-4 Clock Signals Signal Name Type State During Reset Signal Description Input Input External Clock/Crystal Input-EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock. XTAL Freescale Semiconductor, Inc. EXTAL Output Chip Driven Crystal Output-XTAL connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. PHASE LOCK LOOP (PLL) Table 1-5 Phase Lock Loop Signals Signal Name PCAP Type Input State During Reset Input Signal Description PLL Capacitor-PCAP is an input connecting an offchip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. CLKOUT Output Chip-driven Clock Output-CLKOUT provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-5 Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) Table 1-5 Phase Lock Loop Signals (Continued) Signal Name Freescale Semiconductor, Inc. PINIT/ NMI Type Input State During Reset Signal Description Input PLL Initial/Non-Maskable Interrupt-During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT. PINIT/NMI can tolerate 5 V. EXTERNAL MEMORY EXPANSION PORT (PORT A) Note: When the DSP56304 DSP56304 enters a low-power standby mode (Stop or Wait), it releases bus mastership and tri-states the relevant Port A signals: A0­A17, D0­D23, AA0/RAS0­AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK. Note: If the hardware refresh of external DRAM is enabled, the Port A pins exit Wait state to perform the refresh, and then return to the Wait state again. EXTERNAL ADDRESS BUS Table 1-6 External Address Bus Signals Signal Name A0­A17 Type Output State During Reset, Stop, or Wait Tri-stated Signal Description Address Bus-When the DSP is the bus master, A0­ A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0­A17 do not change state when external memory spaces are not being accessed. Preliminary Data 1-6 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) EXTERNAL DATA BUS Table 1-7 External Data Bus Signals Signal Name Type Freescale Semiconductor, Inc. D0­D23 Input/ Output State During Reset, Stop, or Wait Tri-stated Signal Description Data Bus-When the DSP is the bus master, D0­D23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0­ D23 are tri-stated. EXTERNAL BUS CONTROL Table 1-8 External Bus Control Signals Signal Name Type State During Reset, Stop, or Wait Signal Description AA0­ AA3/ RAS0­ RAS3 Output Tri-stated Address Attribute or Row Address Strobe-When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for Dynamic Random Access Memory (DRAM) interface. These signals are tri-statable outputs with programmable polarity. RD Output Tri-stated Read Enable-When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0­D23). Otherwise, RD is tri-stated. WR Output Tri-stated Write Enable-When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0­D23). Otherwise, the signals are tri-stated. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-7 Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) Table 1-8 External Bus Control Signals (Continued) Signal Name Freescale Semiconductor, Inc. TA Type Input State During Reset, Stop, or Wait Ignored Input Signal Description Transfer Acknowledge-If the DSP56304 DSP56304 is the bus master and there is no external bus activity, or the DSP56304 DSP56304 is not the bus master, the TA input is ignored. The TA input is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2,., infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the Bus Control Register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access can not be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the Operating Mode Register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. BR Output Output (driven high/ deasserted) Bus Request-BR is an active-low output, never tristated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56304 DSP56304 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP56304 DSP56304 is the bus master (see the description of bus "parking" in the BB signal description). The Bus Request Hole (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. Preliminary Data 1-8 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Expansion Port (Port A) Table 1-8 External Bus Control Signals (Continued) Signal Name Type State During Reset, Stop, or Wait Signal Description Freescale Semiconductor, Inc. BG Input Ignored Input Bus Grant-BG is an active-low input. BG must be asserted/deasserted synchronous to CLKOUT for proper operation. BG is asserted by an external bus arbitration circuit when the DSP56304 DSP56304 becomes the next bus master. When BG is asserted, the DSP56304 DSP56304 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. BB Input/ Output Input Bus Busy-BB is a bidirectional active-low input/output and must be asserted and deasserted synchronous to CLKOUT. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to reuse the bus without re-arbitration until another device requires the bus. The deassertion of BB is done by an "active pullup" method (i.e., BB is driven high and then released and held high by an external pull-up resistor). BB requires an external pull-up resistor. CAS Output Tri-stated Column Address Strobe-When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM Control Register is cleared, the signal is tri-stated. BCLK Output Tri-stated Bus Clock-When the DSP is the bus master, BCLK is an active-high output used by Synchronous Static Random Access Memory (SSRAM) to sample address, data, and control signals. BCLK is active either during SSRAM accesses or as a sampling signal when the program Address Tracing mode is enabled (by setting the ATE bit in the OMR). When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. The BCLK rising edge may be used to sample the internal program memory access on the A0­A23 address lines. BCLK Output Tri-stated Bus Clock Not-When the DSP is the bus master, BCLK is an active-low output and is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-9 Freescale Semiconductor, Inc. Signal/Connection Descriptions Interrupt and Mode Control INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 1-9 Interrupt and Mode Control Freescale Semiconductor, Inc. Signal Name RESET Type State During Reset Input Input Signal Description Reset-RESET is an active-low, Schmitt-trigger input. Deassertion of RESET is internally synchronized to the clock out (CLKOUT). When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in "lock-step". When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power up. RESET can tolerate 5 V. MODA/IRQA Input Input Mode Select A/External Interrupt Request A-MODA/ IRQA is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If IRQA is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQA to exit the Wait state. If the processor is in the Stop standby state and IRQA is asserted, the processor will exit the Stop state. MODA/IRQA can tolerate 5 V. Preliminary Data 1-10 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Interrupt and Mode Control Table 1-9 Interrupt and Mode Control (Continued) Type State During Reset MODB/IRQB Freescale Semiconductor, Inc. Signal Name Input Input Signal Description Mode Select B/External Interrupt Request B-MODB/ IRQB is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQB is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the Wait state. MODB/IRQB can tolerate 5 V. MODC/IRQC Input Input Mode Select C/External Interrupt Request C-MODC/ IRQC is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQC is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQC to exit the Wait state. MODC/IRQC can tolerate 5 V. MODD/IRQD Input Input Mode Select D/External Interrupt Request D- MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQD is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQD to exit the Wait state. MODD/IRQD can tolerate 5 V. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-11 Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) HOST INTERFACE (HI08) The HI08 provides a fast parallel data to 8-bit port, which may be connected directly to the host bus. Freescale Semiconductor, Inc. The HI08 supports a variety of standard buses, and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware. Host Port Usage Considerations Careful synchronization is required when reading multiple-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the Host port). The considerations for proper operation are discussed in the following table: Table 1-10 Host Port Usage Considerations Action Description Asynchronous read of receive byte registers When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll the Receive register Data Full (RXDF) flag which indicates that data is available. This assures that the data in the receive byte registers will be valid. Asynchronous write to transmit byte registers The host interface programmer should not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the Host Receive (HRX) register. Asynchronous write to host vector The host interface programmer should change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This will guarantee that the DSP interrupt control logic will receive a stable vector. Preliminary Data 1-12 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Host Port Configuration The functions of the signals associated with the HI08 vary according to the programmed configuration of the interface as determined by the 16 bits in the HI08 Port Control Register (HPCR). Refer to the DSP56304 DSP56304 User's Manual for detailed descriptions of this and the other configuration registers used with the HI08. Freescale Semiconductor, Inc. Table 1-11 Host Interface Signal Name Type State During Reset or Stop1 Disconnected Signal Description H0­H7 Input/ Output Host Data-When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, these signals are lines 0­7 of the Data bidirectional, tri-state bus. HAD0­ HAD7 Input/ Output Host Address-When HI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0­7 of the Address/ Data bidirectional, multiplexed, tri-state bus. PB0­PB7 Input or Output Port B 0­7-When the HI08 is configured as GPIO through the HPCR, these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register (HDDR). This input is 5 V tolerant. HA0 Input HAS/HAS Input PB8 Input or Output Disconnected Host Address Input 0-When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 0 of the Host Address input bus. Host Address Strobe-When HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the Host Address Strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS) following reset. Port B 8-When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input is 5 V tolerant. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-13 Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 1-11 Host Interface (Continued) Type State During Reset or Stop1 HA1 Input Disconnected HA8 Freescale Semiconductor, Inc. Signal Name Input PB9 Input or Output Signal Description Host Address Input 1-When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 1 of the Host Address (HA1) input bus. Host Address 8-When HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the Host Address (HA8) input bus. Port B 9-When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input is 5 V tolerant. HA2 Input HA9 Input PB10 Input or Output Disconnected Host Address Input 2-When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the Host Address (HA2) input bus. Host Address 9-When HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the Host Address (HA9) input bus. Port B 10-When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input is 5 V tolerant. Preliminary Data 1-14 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 1-11 Host Interface (Continued) Type State During Reset or Stop1 HRW Input Disconnected HRD/HRD Freescale Semiconductor, Inc. Signal Name Input PB11 Signal Description Host Read/Write-When HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read Data-When HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the Host Read Data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Input or Output Port B 11-When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input is 5 V tolerant. HDS/HDS Input HWR/HWR Input PB12 Input or Output Disconnected Host Data Strobe-When HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Data Strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as activelow (HDS) following reset. Host Write Data-When HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the Host Write Data Strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12-When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input is 5 V tolerant. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-15 Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 1-11 Host Interface (Continued) Type State During Reset or Stop1 HCS Freescale Semiconductor, Inc. Signal Name Input Disconnected HA10 Input PB13 Input or Output Signal Description Host Chip Select-When HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is the Host Chip Select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10-When HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the Host Address (HA10) input bus. Port B 13-When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input is 5 V tolerant. HREQ/ HREQ Output Disconnected Host Request-When HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the Host Request (HREQ) output. The polarity of the host request is programmable, but is configured as active-low (HREQ) following reset. The host request may be programmed as a driven or open-drain output. HTRQ/ HTRQ Output Transmit Host Request-When HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the Transmit Host Request (HTRQ) output. The polarity of the host request is programmable, but is configured as activelow (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. PB14 Input or Output Port B 14-When the HI08 is programmed to interface a multiplexed host bus and the signal is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input is 5 V tolerant. Preliminary Data 1-16 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Host Interface (HI08) Table 1-11 Host Interface (Continued) Type State During Reset or Stop1 HACK/ HACK Freescale Semiconductor, Inc. Signal Name Input Disconnected HRRQ/ HRRQ Output Receive Host Request-When HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the Receive Host Request (HRRQ) output. The polarity of the host request is programmable, but is configured as activelow (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. PB15 Input or Output Port B 15-When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Signal Description Host Acknowledge-When HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the Host Acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. This input is 5 V tolerant. Note: 1. Wait state does not affect signal state. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-17 Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface 0 (ESSI0) ENHANCED SYNCHRONOUS SERIAL INTERFACE 0 (ESSI0) There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a fullduplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola Serial Peripheral Interface (SPI). Freescale Semiconductor, Inc. Table 1-12 Enhanced Synchronous Serial Interface 0 (ESSI0) Signal Name SC00 Type State During1 Reset Input or Output Stop Input Disconnected Signal Description PC0 Serial Control 0-The function of SC00 is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal will be used for the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is used either for Transmitter 1 output or for Serial I/O Flag 0. Port C 0-The default configuration following reset is GPIO input PC0. When configured as PC0, signal direction is controlled through the Port Directions Register (PRR0). The signal can be configured as ESSI signal SC00 through the Port Control Register (PCR0). This input is 5 V tolerant. SC01 Input/ Output PC1 Input or Output Input Disconnected Serial Control 1-The function of this signal is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receiver frame sync I/O. For Synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. Port C 1-The default configuration following reset is GPIO input PC1. When configured as PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0. This input is 5 V tolerant. Preliminary Data 1-18 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface 0 (ESSI0) Table 1-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued) Signal Name Type Reset SC02 Freescale Semiconductor, Inc. State During1 Input/ Output PC2 Stop Input Disconnected Signal Description Input or Output Serial Control Signal 2-SC02 2-SC02 is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2-The default configuration following reset is GPIO input PC2. When configured as PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. This input is 5 V tolerant. SCK0 Input/ Output Input Disconnected Serial Clock-SCK0 is a bidirectional Schmitttrigger input signal providing the serial bit rate clock for the ESSI interface. The SCK0 is a clock input or output used by both the transmitter and receiver in Synchronous modes, or by the transmitter in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6 T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PC3 Input or Output Port C 3-The default configuration following reset is GPIO input PC3. When configured as PC3, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SCK0 through PCR0. This input is 5 V tolerant. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-19 Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface 0 (ESSI0) Table 1-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued) Signal Name Type Reset SRD0 Input/ Output PC4 Freescale Semiconductor, Inc. State During1 Stop Input Disconnected Signal Description Input or Output Serial Receive Data-SRD0 receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is being received. Port C 4-The default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0. This input is 5 V tolerant. STD0 Input/ Output PC5 Input Disconnected Input or Output Serial Transmit Data-STD0 is used for transmitting data from the serial transmit shift register. STD0 is an output when data is being transmitted. Port C 5-The default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. This input is 5 V tolerant. Note: 1. Wait state does not affect signal state. Preliminary Data 1-20 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface 1 (ESSI1) ENHANCED SYNCHRONOUS SERIAL INTERFACE 1 (ESSI1) Table 1-13 Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name Freescale Semiconductor, Inc. SC10 Type State During1 Reset Input or Output Input Signal Description Stop Disconnected PD0 Serial Control 0-The function of SC10 is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal will be used for the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is used either for Transmitter 1 output or for Serial I/O Flag 0. Port D 0-The default configuration following reset is GPIO input PD0. When configured as PD0, signal direction is controlled through the Port Directions Register (PRR1). The signal can be configured as an ESSI signal SC10 through the Port Control Register (PCR1). This input is 5 V tolerant. SC11 Input/ Output PD1 Input or Output Input Disconnected Serial Control 1-The function of this signal is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receiver frame sync I/O. For Synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. Port D 1-The default configuration following reset is GPIO input PD1. When configured as PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1. This input is 5 V tolerant. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-21 Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued) Signal Name Type Reset SC12 Freescale Semiconductor, Inc. State During1 Input/ Output PD2 Input Signal Description Stop Disconnected Input or Output Serial Control Signal 2-SC12 2-SC12 is used for frame sync I/O. SC12 is the frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in Synchronous operation). Port D 2-The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1. This input is 5 V tolerant. SCK1 Input/ Output Input Disconnected Serial Clock-SCK1 is a bidirectional Schmitttrigger input signal providing the serial bit rate clock for the ESSI interface. The SCK1 is a clock input or output used by both the transmitter and receiver in Synchronous modes, or by the transmitter in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PD3 Input or Output Port D 3-The default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. This input is 5 V tolerant. Preliminary Data 1-22 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued) Signal Name Type Reset SRD1 Input/ Output PD4 Freescale Semiconductor, Inc. State During1 Input Signal Description Stop Disconnected Input or Output Serial Receive Data-SRD1 receives serial data and transfers the data to the ESSI receive shift register. SRD1 is an input when data is being received. Port D 4-The default configuration following reset is GPIO input PD4. When configured as PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1. This input is 5 V tolerant. STD1 Input/ Output PD5 Input Disconnected Input or Output Serial Transmit Data-STD1 is used for transmitting data from the serial transmit shift register. STD1 is an output when data is being transmitted. Port D 5-The default configuration following reset is GPIO input PD5. When configured as PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1. This input is 5 V tolerant. Note: 1. Wait state does not affect signal state. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-23 Freescale Semiconductor, Inc. Signal/Connection Descriptions Serial Communication Interface (SCI) SERIAL COMMUNICATION INTERFACE (SCI) The Serial Communication interface (SCI) provides a full duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. Table 1-14 Serial Communication Interface (SCI) Freescale Semiconductor, Inc. Signal Name Type State During1 Reset RXD Input PE0 Input Disconnected Signal Description Stop Input or Output Serial Receive Data-This input receives byte oriented serial data and transfers it to the SCI receive shift register. Port E 0-The default configuration following reset is GPIO input PE0. When configured as PE0, signal direction is controlled through the SCI Port Directions Register (PRR). The signal can be configured as an SCI signal RXD through the SCI Port Control Register (PCR). This input is 5 V tolerant. TXD Output (may be open drain) PE1 Input Disconnected Input or Output Serial Transmit Data-This signal transmits data from SCI transmit data register. Port E 1-The default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR. This input is 5 V tolerant. SCLK Input/ Output PE2 Input Disconnected Input or Output Serial Clock-This is the bidirectional Schmitttrigger input signal providing the input or output clock used by the transmitter and/or the receiver. Port E 2-The default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR. This input is 5 V tolerant. Note: 1. Wait state does not affect signal state. Preliminary Data 1-24 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions TimerS TIMERS Three identical and independent timers are implemented in the DSP56304 DSP56304. Each timer can use internal or external clocking, and can interrupt the DSP56304 DSP56304 after a specified number of events (clocks), or can signal an external device after counting a specific number of internal events. Table 1-15 Triple Timer Signals Freescale Semiconductor, Inc. Signal Name Type State During1 Reset TIO0 Input or Output Input Signal Description Stop Disconnected Timer 0 Schmitt-Trigger Input/Output-When Timer 0 functions as an external event counter or in Measurement mode, TIO0 is used as input. When Timer 0 functions in Watchdog, Timer, or Pulse Modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 0 Control/Status Register (TCSR0). This input is 5 V tolerant. TIO1 Input or Output Input Disconnected Timer 1 Schmitt-Trigger Input/Output-When Timer 1 functions as an external event counter or in Measurement mode, TIO1 is used as input. When Timer 1 functions in Watchdog, Timer, or Pulse Modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 1 Control/Status Register (TCSR1). This input is 5 V tolerant. TIO2 Input or Output Input Disconnected Timer 2 Schmitt-Trigger Input/Output-When Timer 2 functions as an external event counter or in Measurement mode, TIO2 is used as input. When Timer 2 functions in Watchdog, Timer, or Pulse Modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 2 Control/Status Register (TCSR2). This input is 5 V tolerant. Note: 1. Wait state does not affect signal state. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-25 Freescale Semiconductor, Inc. Signal/Connection Descriptions OnCE/JTAG Interface OnCE/JTAG INTERFACE Table 1-16 OnCE/JTAG Interface Signal Name TCK Type Input State During Reset Input Signal Description Test Clock-TCK is a test clock input signal used to synchronize the JTAG test logic. Freescale Semiconductor, Inc. This input is 5 V tolerant. TDI Input Input Test Data Input-TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TDO Output Tri-stated Test Data Output-TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. TMS Input Input Test Mode Select-TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TRST Input Input Test Reset-TRST is an active-low Schmitttrigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up. This input is 5 V tolerant. Preliminary Data 1-26 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal/Connection Descriptions OnCE/JTAG Interface Table 1-16 OnCE/JTAG Interface (Continued) Signal Name Freescale Semiconductor, Inc. DE Type Input/ Output State During Reset Input Signal Description Debug Event-DE is an open-drain, bidirectional, active-low signal providing, as an input, a means of entering the Debug mode of operation from an external command controller, and, as an output, a means of acknowledging that the chip has entered the Debug mode. This signal, when asserted as an input, causes the DSP56300 DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter the Debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters the Debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. This is not a standard part of the JTAG Test Access Port (TAP) Controller. The signal connects directly to the OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode. All other interface with the OnCE module must occur through the JTAG port. This input is 5 V tolerant. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 1-27 Freescale Semiconductor, Inc. Signal/Connection Descriptions Freescale Semiconductor, Inc. OnCE/JTAG Interface Preliminary Data 1-28 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 2 SPECIFICATIONS Freescale Semiconductor, Inc. INTRODUCTION The DSP56304 DSP56304 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56304 DSP56304 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after full characterization and device qualifications are complete. MAXIMUM RATINGS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. Specifications Thermal Characteristics Table 2-1 Maximum Ratings Rating1 Symbol Value1, 2 Unit Supply Voltage VCC V All input voltages excluding "5 V tolerant" inputs3 VIN -0.3 to +4.0 GND - 0.3 to VCC + 0.3 V All "5 V tolerant" input voltages3 VIN5 GND - 0.3 to VCC + 3.95 V Current drain per pin excluding VCC and GND I 10 mA Operating temperature range TJ -40 to +100 -55 to +150 °C °C Freescale Semiconductor, Inc. Storage temperature Note: 1. 2. 3. TSTG GND = 0 V, VCC = 3.3 V ± 0.3 V, TJ = ­40°C to +100°C, CL = 50 pF + 2 TTL Loads Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. CAUTION: All "5 V Tolerant" input voltages cannot be more than 3.95 V greater than the supply voltage; this restriction applies to "power on", as well as during normal operation. In any case, the input voltages can not be more than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V. THERMAL CHARACTERISTICS Table 2-2 Thermal Characteristics Characteristic Symbol TQFP Value PBGA3 Value PBGA4 Value Unit Junction-to-ambient thermal resistance RJA or JA 55.7 57 28 °C/W Junction-to-case thermal resistance RJC or JC 11.4 15 - °C/W Thermal characterization parameter JT 6.8 8 - °C/W Note: 1. 2. 3. 4. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G3088 G3088, with the exception that the cold plate temperature is used for the case temperature. These are simulated values; testing is not complete. See note 1 for test board conditions. These are simulated values; testing is not complete. The test board has two, 2-ounce signal layers and two 1-ounce solid ground planes internal to the test board. Preliminary Data 2-2 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics6 Characteristics Symbol Min Typ Max Unit VCC 3.0 3.3 3.6 V VIH VIHP 2.0 2.0 - - VCC VCC + 3.95 V V VIHX 0.8 - VCC V VIL ­0.3 - 0.8 V VILP ­0.3 - 0.8 V VILX ­0.3 - 0.2 V Input leakage current IIN ­10 - 10 µA High impedance (off-state) input current (@ 2.4 V / 0.4 V) ITSI ­10 - 10 µA Output high voltage · TTL (IOH = ­0.4 mA)5,7 · CMOS (IOH = ­10 µA)5 VOH VCC ­ 0.4 VCC ­ 0.01 - - - - V V Output low voltage · TTL (IOL = 3.0 mA, open-drain pins IOL = 6.7 mA)5,7 · CMOS (IOL = 10 µA)5 VOL - - 0.4 V - - 0.01 V Freescale Semiconductor, Inc. Supply voltage Input high voltage · D(0:23), BG, BB, TA · MOD1/IRQ1, RESET, PINIT/ NMI and all JTAG/ESSI/SCI/ Timer/HI08 pins · EXTAL8 Input low voltage · D(0:23), BG, BB, TA, MOD1/ IRQ1, RESET, PINIT · All JTAG/ESSI/SCI/Timer/ HI08 pins · EXTAL8 Internal supply current2: · In Normal mode ICCI - · In Wait mode3 ICCW - · In Stop mode4 ICCS - PLL supply current in Stop mode5 Input capacitance5 66 MHz: 84 80 MHz: 102 66 MHz: 5 80 MHz: 6 66 MHz: 100 80 MHz: 100 66 MHz: 120 80 MHz: 145 66 MHz: 7 80 MHz: 9 66 MHz: 150 80 MHz: 150 mA mA mA mA µA µA - CIN 1 2.5 mA - - 10 pF Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. Specifications AC Electrical Characteristics Table 2-3 DC Electrical Characteristics6 (Continued) Characteristics Note: 1. 2. Freescale Semiconductor, Inc. 3. 4. 5. 6. 7. 8. Symbol Min Typ Max Unit Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins Power Consumption Considerations on page 4-4 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.0 V at TJ = 100°C. Maximum internal supply current is measured with VCC = 3.6 V at TJ = 100°C. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL and XTAL signals are disabled during Stop state. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). Periodically sampled and not 100% tested VCC = 3.3 V ± 0.3 V; TJ = ­40°C to +100 °C, CL = 50 pF + 2 TTL Loads This characteristic does not apply to XTAL and PCAP. Driving EXTAL to the extreme values for VIHX (0.8 VCC) or VILX (0.2 VCC) may cause increased DC current. To achieve the lowest current, maintain the minimum VIHX above 0.9 VCC and the maximum VILX below 0.1 VCC. AC ELECTRICAL CHARACTERISTICS The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56304 DSP56304 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively. INTERNAL CLOCKS Table 2-4 Internal Clocks, CLKOUT Expression1, 2 Characteristics Symbol Min Internal operation frequency and CLKOUT with PLL enabled f - Typ (Ef × MF)/ (PDF × DF) Max - Preliminary Data 2-4 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Internal Clocks Table 2-4 Internal Clocks, CLKOUT Expression1, 2 Characteristics Symbol Min Internal operation frequency and CLKOUT with PLL disabled Freescale Semiconductor, Inc. Internal clock and CLKOUT high period · With PLL disabled Typ Ef/2 Max f - - TH - ETC - · With PLL enabled and MF 4 0.49 × ETC × PDF × DF/ MF - 0.51 × ETC × PDF × DF/ MF · With PLL enabled and MF > 4 0.47 × ETC × PDF × DF/ MF - 0.53 × ETC × PDF × DF/ MF - ETC - Internal clock and CLKOUT low period · With PLL disabled TL · With PLL enabled and MF 4 0.49 × ETC × PDF × DF/ MF - 0.51 × ETC × PDF × DF/ MF · With PLL enabled and MF > 4 0.47 × ETC × PDF × DF/ MF - 0.53 × ETC × PDF × DF/ MF Internal clock and CLKOUT cycle time with PLL enabled TC - ETC × PDF × DF/MF - Internal clock and CLKOUT cycle time with PLL disabled TC - 2 × ETC - Instruction cycle time ICYC - TC - Note: 1. 2. DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle See the PLL and Clock Generation section in the DSP56300 DSP56300 detailed discussion of the PLL. Family Manual for a Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. Specifications External Clock Operation EXTERNAL CLOCK OPERATION The DSP56304 DSP56304 system clock may be derived from the on-chip crystal oscillator, as shown in Figure 1 on the cover page, or it may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically not connected to the board or socket (see Figure 2-2). EXTAL XTAL Freescale Semiconductor, Inc. R1 C EXTAL C XTAL1 XTAL R R2 C Fundamental Frequency Fork Crystal Oscillator XTAL1 C Fundamental Frequency Crystal Oscillator Suggested Component Values: Suggested Component Values: fOSC = 32.768 kHz R1 = 3.9 M ± 10% C = 22 pF ± 20% R2 = 200 k ± 10% fOSC = 4 MHz R = 680 k ± 10% C = 56 pF ± 20% Calculations were done for a 32.768 kHz crystal with the following parameters: a load capacitance (CL) of 12.5 pF, a shunt capacitance (C0) of 1.8 pF, a series resistance of 40 k, and a drive level of 1 µW. fOSC = 20 MHz R = 680 k ± 10% C = 22 pF ± 20% Calculations were done for a 4/20 MHz crystal with the following parameters: a CLof 30/20 pF, a C0 of 7/6 pF, a series resistance of 100/20 , and a drive level of 2 mW. Figure 2-1 Crystal Oscillator Circuits Preliminary Data 2-6 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications External Clock Operation VIHC Midpoint EXTAL VILC ETH ETL 2 4 3 ETC 5 5 Freescale Semiconductor, Inc. CLKOUT With PLL Disabled 7 CLKOUT With PLL Enabled 6a Note: 7 6b The midpoint is 0.5 (VIHC + VILC). AA0459 AA0459 Figure 2-2 External Clock Timing Table 2-5 Clock Operation 66 MHz No. Characteristics 80 MHz Symbol Min 1 Frequency of EXTAL (EXTAL Pin Frequency) Max Min Max Ef 0 66.0 0 80.0 ETH 7.08 ns 5.84 ns 6.44 ns 157.0 µs 5.31 ns 157.0 µs 7.08 ns 5.84 ns 6.44 ns 157.0 µs 5.31 ns 157.0 µs 30.3 ns 25.0 ns The rise and fall time of the external clock should be 3 ns maximum. 2 Clock input high1, 2 · With PLL disabled (46.7%­53.3% duty cycle6) · 3 Clock input low1, 2 · With PLL disabled (46.7%­53.3% duty cycle6) · 4 ETL With PLL enabled (42.5%­57.5% duty cycle6) Clock cycle time2 · With PLL disabled · 5 With PLL enabled (42.5%­57.5% duty cycle6) ETC 15.15 ns 273.1 µs 12.50 ns 273.1 µs With PLL enabled CLKOUT change from EXTAL fall with PLL disabled 4.3 ns 11.0 ns 4.3 ns 11.0 ns Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-7 Freescale Semiconductor, Inc. Specifications Phase Lock Loop (PLL) Characteristics Table 2-5 Clock Operation (Continued) 66 MHz No. Characteristics 80 MHz Symbol Min Freescale Semiconductor, Inc. · Note: 1. 2. 3. 4. 5. 6. Max 1.8 ns 1.8 ns 0.0 ns 0.0 ns 1.8 ns 1.8 ns 30.3 ns 25.0 ns 15.15 ns Instruction cycle time = ICYC = TC4 (See Table 2-4.) (46.7%­53.3% duty cycle) · With PLL disabled 7 Min 0.0 ns 0.0 ns CLKOUT from EXTAL with PLL enabled3,5 a. MF = 1, PDF = 1, Ef > 15 MHz b. MF = 2 or 4, PDF = 1, Ef > 15 MHz, or, MF 4, PDF 1, Ef / PDF > 15 MHz 6 Max 8.53 µs 12.50 ns 8.53 µs ICYC With PLL enabled Measured at 50% of the input transition The maximum value for PLL enabled is given for minimum VCO and maximum MF. Periodically sampled and not 100% tested The maximum value for PLL enabled is given for minimum VCO and maximum DF. The skew is not guaranteed for any other MF value. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. PHASE LOCK LOOP (PLL) CHARACTERISTICS Table 2-6 PLL Characteristics 66 MHz 80 MHz Characteristics Unit Min VCO frequency when PLL enabled (MF × Ef × 2/PDF) Max Min Max 30 132 30 160 PLL external capacitor (PCAP pin to VCCP) (CPCAP1) · @ MF 4 (MF × 425) - 125 (MF × 590) - 175 (MF × 425) - 125 (MF × 590) - 175 · Note: @ MF > 4 MF × 520 MF × 920 MF × 520 MF × 920 MHz pF pF CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (500 × MF) ­ 150, for MF 4, or 690 × MF, for MF > 4. Preliminary Data 2-8 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing RESET, STOP, MODE SELECT, AND INTERRUPT TIMING Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 66 MHz No. Characteristics 80 MHz Expression Unit Min Freescale Semiconductor, Inc. 9 Required RESET duration4 · Power on, external clock generator, PLL disabled Max - Delay from RESET assertion to all pins at reset value3 Min - 26.0 - 26.0 ns 50 × ETC 8 Max 760.0 - 625.0 - ns · 1000 × ETC 15.2 - 12.5 - ms · Power on, internal oscillator 75000 × ETC 1.14 - 1.0 - ms · During STOP, XTAL disabled (PCTL Bit 16 = 0) 75000 × ETC 1.14 - 1.0 - ms · During STOP, XTAL enabled (PCTL Bit 16 = 1) 2.5 × TC 38.0 - 31.3 - ns · 10 Power on, external clock generator, PLL enabled During normal operation 2.5 × TC 38.0 - 31.3 - ns 51.0 - - - ns - - 42.6 - ns - 318.0 - - ns - - - 263.1 ns 9.0 - 7.4 - ns TC - 15.2 - 12.5 ns 3.25 × TC + 1.0 50.0 - 41.6 - ns 20.25 TC + 5.0 - 312.0 - 258.1 ns 30.0 - 30.0 - ns Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 · Minimum · 11 66 MHz: 20.25 TC + 11.0 80 MHz: 20.25 TC + 9.95 Maximum Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output · Minimum · 13 Maximum Synchronous reset setup time from RESET deassertion to CLKOUT Transition 1 · Minimum · 12 66 MHz: 3.25 × TC + 2.0 80 MHz: 3.25 × TC + 2.0 Maximum Mode select setup time Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-9 Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 66 MHz No. Characteristics 80 MHz Expression Unit Min Max Min Max Mode select hold time 0.0 - 0.0 - ns 15 Minimum edge-triggered interrupt request assertion width 10.0 - 8.25 - ns 16 Freescale Semiconductor, Inc. 14 Minimum edge-triggered interrupt request deassertion width 10.0 - 8.25 - ns 17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid · Caused by first interrupt instruction fetch 4.25 × TC + 2.0 66.0 - 55.1 - ns · Caused by first interrupt instruction execution 7.25 × TC + 2.0 112.0 - 92.6 - ns 157.0 - 130.0 - ns 18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to generalpurpose transfer output valid caused by first interrupt instruction execution 10 × TC + 5.0 19 Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1 66 MHz8: 3.75 × TC + WS × TC ­ 14 20 - 80 MHz8: 3.75 × TC + WS × TC ­ 12.4 Delay from RD assertion to interrupt 66 MHz8: request deassertion for level sensitive 3.25 × TC + WS fast interrupts1 × TC ­ 14 ns - - 80 MHz8: 3.25 × TC + WS × TC ­ 12.4 ns ns - ns Preliminary Data 2-10 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 66 MHz No. Characteristics Unit Min 21 Freescale Semiconductor, Inc. Max Min Max Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1 · 66 MHz8: (3.75 + WS) × TC ­ 14 SSRAM for all WS - ns 80 MHz8: (3.75 + WS) × TC ­ 12.4 · 66 MHz8: (3.5 + WS) × TC ­ 14 DRAM for all WS - · 66 MHz8: (WS + 3.5) × TC ­ 14 SRAM WS = 1 ns - 66 MHz8: (WS + 3) × TC ­ 14 SRAM WS = 2, 3 ns - SRAM WS 4 66 MHz8: (2.5 + WS) × TC ­ 14 ns - ns - ns 80 MHz8: (2.5 + WS) × TC ­ 12.4 Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 ns - 80 MHz8: (WS + 3) × TC ­ 12.4 · ns - 80 MHz8: (WS + 3.5) × TC ­ 12.4 · ns - 80 MHz8: (3.5 + WS) × TC ­ 12.4 22 80 MHz Expression - 9.0 TC 7.4 ns TC ns Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-11 Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 66 MHz No. Characteristics 80 MHz Expression Unit Min Freescale Semiconductor, Inc. 23 · 24.75 × TC + 5.0 Maximum 24 Duration for IRQA assertion to recover from Stop state 25 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 · PLL is not active during Stop PLC × ETC × (PCTL Bit 17 = 0) and Stop PDF + (128 K - delay is enabled PLC/2) × TC (OMR Bit 6 = 0) Min Max 141.0 - 116.6 - ns - 380.0 - 314.4 ns 9.0 Synchronous interrupt delay time from the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state · Minimum 9.25 × TC + 1.0 Max - 7.4 - ns 2.0 64.1 1.6 52.8 ms · 352.3 ns 62.1 ms 290.6 ns 51.2 ms · 26 PLL is not active during Stop PLC × ETC × (PCTL Bit 17 = 0) and Stop PDF + (23.75 ± delay is not enabled (OMR Bit 0.5) × TC 6 = 1) PLL is active during Stop (8.25 ± 0.5) × TC 117.4 (PCTL Bit 17 = 1) (Implies No Stop Delay) 132.6 96.9 109.4 ns Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 · PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) · PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) · PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) PLC × ETC × PDF + (128K - PLC/2) × TC 64.1 - 52.8 - ms PLC × ETC × PDF + (20.5 ± 0.5) × TC 62.1 - 51.2 - ms 83.4 - 68.8 - ns 5.5 × TC Preliminary Data 2-12 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 66 MHz No. Characteristics 80 MHz Expression Unit Min 27 Min Max 12TC Interrupt Requests Rate · HI08, ESSI, SCI, Timer Max - 181.8 - 150.0 ns 8TC - 121.2 - 100.0 ns IRQ, NMI (edge trigger) 8TC - 121.2 - 100.0 ns · 28 DMA · Freescale Semiconductor, Inc. · IRQ, NMI (level trigger) 12TC - 181.8 - 150.0 ns 6TC - 90.9 - 75.0 ns DMA Requests Rate · Data read from HI08, ESSI, SCI · - 106.1 - 87.5 ns Timer 2TC - 30.3 - 25.0 ns · Note: 7TC · 29 Data write to HI08, ESSI, SCI IRQ, NMI (edge trigger) 3TC - 45.5 - 37.5 ns 66.0 - 55.1 - ns Delay from IRQA, IRQB, IRQC, 4.25 × TC + 2.0 IRQD, NMI assertion to external memory (DMA source) access address out valid 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-13 Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 66 MHz No. Characteristics Unit Min 2. 80 MHz Expression Max Min Max This timing depends on several settings: Freescale Semiconductor, Inc. For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored). For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 66 MHz it is 4096/66 MHz = 62 µs). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well. 3. Periodically sampled and not 100% tested 4. For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after powerup. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. 5. 6. 7. 8. If PLL does not lose lock VCC = 3.3 V ± 0.3 V; TJ = ­40°C to +100°C, CL = 50 pF + 2 TTL Loads WS = number of wait states (measured in clock cycles, number of TC) Use expression to compute maximum value. Preliminary Data 2-14 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing VIH RESET 9 10 8 Freescale Semiconductor, Inc. All Pins Reset Value First Fetch A0­A17 AA0460 AA0460 Figure 2-3 Reset Timing CLKOUT 11 RESET 12 A0­A17 AA0461 AA0461 Figure 2-4 Synchronous Reset Timing Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-15 Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing First Interrupt Instruction Execution/Fetch A0­A17 RD 20 Freescale Semiconductor, Inc. WR 21 IRQA, IRQB, IRQC, IRQD, NMI 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O AA0462 AA0462 Figure 2-5 External Fast Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI 16 AA0463 AA0463 Figure 2-6 External Interrupt Timing (Negative Edge-Triggered) Preliminary Data 2-16 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing CLKOUT 22 IRQA, IRQB, IRQC, IRQD, NMI 23 Freescale Semiconductor, Inc. A0­A17 AA0464 AA0464 Figure 2-7 Synchronous Interrupt from Wait State Timing VIH RESET 13 14 VIH VIH VIL MODA, MODB, MODC, MODD, PINIT VIL IRQA, IRQB, IRQC, IRQD, NMI AA0465 AA0465 Figure 2-8 Operating Mode Select Timing 24 IRQA 25 First Instruction Fetch A0­A17 AA0466 AA0466 Figure 2-9 Recovery from Stop State Using IRQA Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-17 Freescale Semiconductor, Inc. Specifications Reset, Stop, Mode Select, and Interrupt Timing 26 IRQA 25 First IRQA Interrupt Instruction Fetch A0­A17 AA0467 AA0467 Freescale Semiconductor, Inc. Figure 2-10 Recovery from Stop State Using IRQA Interrupt Service A0­A17 DMA Source Address RD WR IRQA, IRQB, IRQC, IRQD, NMI 29 a) First Interrupt Instruction Execution Figure 2-11 External Memory Access (DMA Source) Timing Preliminary Data 2-18 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications External Memory Interface (Port A) EXTERNAL MEMORY INTERFACE (PORT A) Table 2-8 SRAM Read and Write Accesses No. Characteristics Expression1 66 MHz 80 MHz Unit Max tRC, tWC (WS + 1) × TC - 4.0 [1 WS 3] 26.3 - 21.0 - ns (WS + 2) × TC - 4.0 [4 WS 7] 86.9 - 71.0 - ns 162.7 - 133.5 - ns 66 MHz: 0.25 × TC - 3.7 [WS = 1] 0.1 - - - - - 0.1 - ns 7.4 - 5.4 - ns 1.25 × TC - 4.0 [WS 4] 14.9 - 11.6 - ns 1.5 × TC - 4.5 [WS = 1] 18.2 - 14.8 - ns WS × TC - 4.0 [2 WS 3] 26.3 - 21.0 - ns (WS - 0.5) × TC - 4.0 [WS 4] 49.0 - 39.8 - ns 66 MHz: 0.25 × TC - 3.8 [1 WS 3] 0.1 - - - ns 80 MHz: 0.25 × TC - 3.0 [1 WS 3] - - 0.0 - ns 1.25 × TC - 4.0 [4 WS 7] 14.9 - 11.6 - ns 2.25 × TC - 4.0 [WS 8] 103 WR deassertion to address not valid Min 0.75 × TC - 4.0 [2 WS 3] 102 WR assertion pulse width Max 80 MHz: 0.25 × TC - 3.0 [WS = 1] 101 Address and AA valid to WR assertion Min (WS + 3) × TC - 4.0 [WS 8] 100 Address valid and AA assertion pulse width Freescale Semiconductor, Inc. Symbol 30.1 - 24.1 - ns tAS tWP tWR ns Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-19 Freescale Semiconductor, Inc. Specifications External Memory Interface (Port A) Table 2-8 SRAM Read and Write Accesses (Continued) No. Characteristics Symbol Expression1 66 MHz 80 MHz Unit Freescale Semiconductor, Inc. Min Max - 16.5 - - ns - - - 12.4 ns 66 MHz: (WS + 0.25) × TC - 10.0 [WS 1] - 8.9 - - ns 80 MHz: (WS + 0.25) × TC - 9.5 [WS 1] - - - 6.1 0.0 - 0.0 - ns (WS + 0.75) × TC - 4.0 [WS 1] 22.5 - 17.9 - ns tDS (tDW) 66 MHz: (WS - 0.25) × TC - 3.9 [WS 1] 7.5 - - - ns 80 MHz: (WS - 0.25) × TC - 3.3 [WS 1] - - 6.1 - ns 66 MHz: 0.25 × TC - 3.7 [1 WS 3] 0.1 - - - ns 80 MHz: 0.25 × TC - 3.0 [1 WS 3] - - 0.1 - ns 1.25 × TC - 3.7 [4 WS 7] 15.2 - 11.8 - ns 2.25 × TC - 3.7 [WS 8] 105 RD assertion to input data valid Max 80 MHz: (WS + 0.75) × TC - 9.5 [WS 1] 104 Address and AA valid to input data valid Min 30.4 - 24.3 - ns tAA, tAC 66 MHz: (WS + 0.75) × TC - 10.0 [WS 1] tOE 106 RD deassertion to data not valid (data hold time) tOHZ 107 Address valid to WR deassertion tAW 108 Data valid to WR deassertion (data setup time) 109 Data hold time from WR deassertion tDH ns Preliminary Data 2-20 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications External Memory Interface (Port A) Table 2-8 SRAM Read and Write Accesses (Continued) No. Characteristics Symbol Expression1 66 MHz 80 MHz Unit Min Max Min Max 0.75 × TC - 3.7 [WS = 1] 7.7 - 5.7 - ns 0.25 × TC - 3.7 [2 WS 3] 0.1 - ­0.6 - ns -0.25 × TC - 3.7 [WS 4] ­7.5 - ­6.8 - ns 0.25 × TC + 0.2 [1 WS 3] - 4.0 - 3.3 ns 1.25 × TC + 0.2 [4 WS 7] - 19.1 - 15.8 ns 2.25 × TC + 0.2 [WS 8] - 34.3 - 28.3 ns 1.25 × TC - 4.0 [1 WS 3] 14.9 - 11.6 - ns 2.25 × TC - 4.0 [4 WS 7] 30.1 - 24.1 - ns 3.25 × TC - 4.0 [WS 8] 45.2 - 36.6 - ns 0.75 × TC - 4.0 [1 WS 3] 7.4 - 5.4 - ns 1.75 × TC - 4.0 [4 WS 7] 22.5 - 17.9 - ns 2.75 × TC - 4.0 [WS 8] 37.7 - 30.4 - ns 0.5 × TC - 3.5 [WS = 1] 4.1 - 2.8 - ns TC - 3.5 [2 WS 3] 11.7 - 9.0 - ns 2.5 × TC - 3.5 [4 WS 7] 34.4 - 27.8 - ns 3.5 × TC - 3.5 [WS 8] 49.5 - 40.3 - ns 115 Address valid to RD assertion 0.5 × TC - 4 3.5 - 2.3 - ns 116 RD assertion pulse width (WS + 0.25) × TC - 3.8 15.1 - 11.8 - ns Freescale Semiconductor, Inc. 110 WR assertion to data active 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active (write) 113 RD deassertion time 114 WR deassertion time Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-21 Freescale Semiconductor, Inc. Specifications External Memory Interface (Port A) Table 2-8 SRAM Read and Write Accesses (Continued) No. Characteristics 66 MHz Expression1 Symbol 80 MHz Unit Freescale Semiconductor, Inc. Max 0.7 - 0.1 - ns 15.9 - 12.6 - ns 2.25 × TC - 3.0 [WS 8] 1. 2. Min 1.25 × TC - 3.0 [4 WS 7] Note: Max 0.25 × TC - 3.0 [1 WS 3] 117 RD deassertion to address not valid Min 31.0 - 25.1 - ns WS is the number of wait states specified in the BCR. VCC = 3.3 V ± 0.3 V; TJ = ­40°C to +100 °C, CL = 50 pF + 2 TTL Loads 100 A0­A17 AA0­AA3 113 116 117 RD 115 105 106 WR 104 Data In D0­D23 AA0468 AA0468 Figure 2-12 SRAM Read Access Preliminary Data 2-22 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications External Memory Interface (Port A) 100 A0­A17 AA0­AA3 107 101 102 103 WR Freescale Semiconductor, Inc. 114 RD 108 110 111 109 112 Data Out D0­D23 AA0469 AA0469 Figure 2-13 SRAM Write Access Table 2-9 SSRAM Read and Write Access No. Characteristics Symbol Expression2 50 MHz1 66 MHz 80 MHz Unit Min Max Min Max Min Max 118 BCLK high to BCLK high (cycle time) tKHKH (WS + 1) × TC 20.0 - 119 BCLK high time tKHKL 50 MHz: 0.5 × TC - 5.5 66 MHz: 0.5 × TC - 4.8 80 MHz: 0.5 × TC - 4.2 4.5 - 120 BCLK low time tKLKH 50 MHz and 66 MHz: (WS + 0.5) × TC - 2.5 80 MHz: (WS + 0.5) × TC - 2.3 15.1 - 2.8 12.5 - 1.5 7.5 - 5.1 - ns - ns ns ns - ns 4.0 - ns 121 BCLK high to input data valid tKHQV (WS + 1) × TC - 7.5 - 12.5 - 7.7 - 5.0 ns 122 RD assertion to input data valid tGLQV (WS + 1) × TC - 7.5 - 12.5 - 7.7 - 5.0 ns Preliminary Data MOTOROLA DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com 2-23 Freescale Semiconductor, Inc. Specifications External Memory Interface (Port A) Table 2-9 SSRAM Read and Write Access (Continued) No. Characteristics Symbol Expression2 50 MHz1 66 MHz 80 MHz Unit Min Max Min Max Min Max tGHQX 0.0 - 0.0 - 0.0 - ns 124 Address and AA setup time to clock high Freescale Semiconductor, Inc. 123 RD deassertion to input data invalid tAVKH 0.5 × TC - 4.0 6.0 - 3.6 - 2.8 - ns 125 WR setup time tSWVKH 0.5 × TC - 4.0 to clock high 6.0 - 3.6 - 2.8 - ns 126 Data out setup time to clock high tDVKH (WS + 0.5) × TC - 4.0 6.0 - 3.6 - 2.8 - ns 127 BCLK high to address and AA invalid (hold time) tKHAX (WS + 0.5) × TC -1.0 9.0 - 6.6 - 5.3 - ns 128 BCLK high to tKHSWX (WS + 0.5) × TC -1.0 WR deassertion (hold time) 9.0 - 6.6 - 5.3 - ns 129 BCLK high to input data invalid (data hold time) tKHQX2 0.0 - 0.0 - 0.0 - ns 130 BCLK high to output data invalid (data hold time) BCLK high to data high impedance tKHDX 0.5 × TC - 1.0 9.0 - 6.6 - 5.3 - ns Note: 1. 2. Using available SSRAM, the DSP56304 DSP56304 can be run at 50 MHz with zero wait states. WS is the number of wait states specified in the BCR. Preliminary Data 2-24 DSP56304/D DSP56304/D For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications External Memory Interface (Port A) 118 120 BCLK 124 119 127 Freescale Semiconductor, Inc. A