DSP56300 DSP56303 DSP56301 DSP56000 DSP56300FM/AD DSP56301/D DSP56302 - Datasheet Archive

 

Rev. 0 , 4/16/99 Contents 1 Introduction This application note describes how to interface external Asynchronous Fast Static

 

Freescale Semiconductor Rev. 0 , 4/16/99 Contents 1 Introduction This application note describes how to interface external Asynchronous Fast Static Random Access Memory (Fast SRAM) to Motorola's DSP56300 DSP56300 family of devices. This document is a supplement to the DSP56300 DSP56300 24-Bit Digital Signal Processor Family Manual, and to the user's manuals and technical data sheets for devices in the DSP56300 DSP56300 family. The intent is to describe methods for interfacing various types of memory to the DSP56300 DSP56300's Memory Expansion Port in order to assist the DSP hardware engineer to fully utilize the processor's resources and generate an optimized memory design. These memory designs use a minimum of additional devices. Taking advantage of the DSP's available control lines makes virtually glueless external memory interfaces possible, thereby reducing the cost and using fewer devices in an application's memory design. Specifically, this application note describes implementations for asynchronous Fast SRAM using the DSP56303 DSP56303. The DSP56303 DSP56303 is representative of the DSP56300 DSP56300 family and has all the essential family features. Where appropriate, several memory configurations provide a complete set of examples from which the designer can choose. Introduction . 1-1 1.1 1.2 1.3 1.4 DSP56300 DSP56300 Family . 1-2 Application Note Organization. 1-2 Static RAM (SRAM) Types . 1-3 References . 1-4 2 by Phil Brewer 1 Interface Overview .2-1 2.1 2.2 DSP56300 DSP56300 Control Signals. 2-1 DSP56300 DSP56300 External Memory Timing . 2-1 DSP56303 DSP56303 Memory Control Registers . 2-4 2.3 3 32K × 8-bit Memory Based Designs .3-1 3.1 32K × 24-bit Common Fast SRAM Hardware Design. 3-2 32K × 24-bit `P' Space Fast SRAM Example . 3-6 32K × 24-bit `P'/'X'/`Y' Fast SRAM Example . 3-13 16K × 24-bit `P'/'X' and 16K × 24-bit `Y' Fast SRAM Example . 3-20 3.2 3.3 3.4 4 128K × 8-bit Memory Based Designs.4-1 4.1 128K × 24-bit Common Fast SRAM Hardware Design. 4-2 128K × 24-bit `P'/'X'/`Y' Fast SRAM Example. 4-6 64K × 24-bit 'X' and 64K × 24-bit `Y' Fast SRAM Example . 4-13 4.2 4.3 5 64K × 24-bit Memory Based Designs.5-1 5.1 64K × 24-bit Common Fast SRAM Hardware Design. 5-2 32K × 24-bit `P'/'X' and 32K × 24-bit `Y' Fast SRAM Example . 5-6 32K × 24-bit 'X' and 32K × 24-bit `Y' Fast SRAM Example . 5-14 5.2 5.3 6 6.1 © Freescale Semiconductor, Inc., 2004. All rights reserved. DSP Memory Space Configurations . 6-1 Fast SRAM Advantages . 6-1 Interfacing Fast SRAM to Motorola's DSP56300 DSP56300 Family Interfacing Fast SRAM to Freescale's DSP56300 DSP56300 Family of Digital Signal Processors Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Order by APR 25/D Introduction The Motorola DSP56300 DSP56300 family of DSPs uses a programmable 24-bit fixed-point core. This core is a high-performance, single-clock-cycle-per-instruction engine that provides almost twice the performance of Motorola's popular DSP56000 DSP56000 family core while retaining code compatibility. The DSP56300 DSP56300 family core consists of a Peripheral/Memory Expansion Port (Port A), External Memory and Peripheral DRAM controller, Data Arithmetic Logic Unit (Data ALU), Address Generation Unit (AGU), Instruction Cache Controller, Program Control Unit, on-chip concurrent six-channel DMA controller, PLL Clock Generator, On-Chip Emulation (OnCETM) module, JTAG Test Access Port (TAP) compatible with the IEEE 1149.1 Standard, and a Peripheral and Memory Expansion Bus. The main features of the core include: · Object code compatibility with the DSP56000 DSP56000 core · Modified Harvard architecture with 24-bit instruction and 24-bit data width · Fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC) · 56-bit parallel barrel shifter · 16-bit arithmetic mode of operation · Highly parallel instruction set · Position Independent Code (PIC) instruction-set support · Unique DSP addressing modes · On-chip memory-expandable hardware stack · Nested hardware DO loops · Fast auto-return interrupts · On-chip instruction cache · External Memory and Peripheral Access Attribute select support · On-chip Phase Lock Loop (PLL) · Program address tracing support The main differences between derivatives of the DSP56300 DSP56300 family are the size of the on-chip memory and the types of on-chip peripherals and hardware accelerators. 1.2 Application Note Organization This document has six sections: 1. An overview of the contents of this application note 2. A description of the DSP56303 DSP56303 memory expansion port, Port A, including its use and timing characteristics 3. Three examples of common memory space configurations based on a common hardware memory design that uses 32K x 8-bit 5.0 V Fast SRAM and two Address Attribute Selectors 4. Two examples of common memory space configurations based on a common hardware design that uses 128K x 8-bit 3.3 V Fast SRAM and two Address Attribute Selectors 5. Two examples of common memory space configurations based on a common hardware design that uses 64K x 24-bit 3.3 V Fast SRAM and two Address Attributes Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 1.1 DSP56300 DSP56300 Family Introduction 1.3 Static RAM (SRAM) Types The following SRAM types were considered for this application note. · Asynchronous Fast SRAM - Asynchronous Fast SRAM 8-bit - Fast SRAM 5.0 V - Fast SRAM 3.3 V - Asynchronous Fast SRAM 16-bit - Asynchronous Fast SRAM 24-bit - Asynchronous Fast SRAM 32-bit - Fast SRAM 5.0 V - Fast SRAM 3.3 V - Asynchronous Fast SRAM modules · Cache - Dual I/O Synchronous SRAM - Burst RAM Synchronous Fast SRAM - Pipelined Burst RAM Synchronous Fast SRAM - Flow-Through Pipelined Burst RAM Synchronous Fast SRAM - Secondary Cache Modules · Synchronous Fast SRAM (SSRAM) However, only the most popular memory types and those types requiring little or no supporting hardware (i.e., glue logic) are included in this application note. The examples in this report give designers the insight necessary to implement other memory families and memory types, if needed, with DSP56300 DSP56300 family devices. To achieve the fastest operation on the external memory bus and, consequently, the fewest number of DSP wait states requires the fastest memory available (i.e., Fast SRAM). Slower SRAM can be substituted for the Fast SRAM resulting in DSP-generated external memory wait states each of which is roughly equivalent to one clock period of the DSP core. Each wait state is 12.5 nS for a DSP core running at 80 MHz. An asynchronous external access for a DSP56300 DSP56300 family device incurs an automatic one wait state penalty when the address for the external memory device is required to be stable during the entire access. Since asynchronous Fast SRAM and SRAM devices have this address stability requirement, the DSP operates with at least one wait state when using these external memories. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 6. A summary of the memory design implementations presented in the previous sections and the advantages of using Fast SRAM. Introduction Motorola DSP56300 DSP56300 24-bit Digital Signal Processor Family Manual (DSP56300FM/AD DSP56300FM/AD), Motorola, 1995. DSP56301 DSP56301 Technical Data Sheet (DSP56301/D DSP56301/D), Motorola, 1995. DSP56302 DSP56302 Technical Data Sheet (DSP56302/D DSP56302/D), Motorola, 1996. DSP56303 DSP56303 Technical Data Sheet (DSP56303/D DSP56303/D), Motorola, 1996. Motorola DSP56303 DSP56303 24-bit Digital Signal Processor (DSP56303UM/AD DSP56303UM/AD), Motorola, 1996. Motorola Dynamic RAM's & Memory Modules (DL155/D DL155/D), Motorola, 1993. Motorola Fast Static RAM Component and Module Data (DL156/D DL156/D), Rev 3, Motorola, 1995. Advanced Micro Devices CMOS Memory Products 1991 Data Book/Handbook, AMD, 1991. Advanced Micro Devices FLASH Memory Products 1994/1995 Data Book/Handbook, AMD, 1995. Quality Semiconductor QuickSwitch® Products Databook, Quality Semiconductor, 1995. Quality Semiconductor Application Note AN-11 AN-11, Bus Switches Provide 5 V and 3 V Logic Conversion with Zero Delay, 1995. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 1.4 References Interface Overview Interface Overview This section describes how external memory devices are interfaced to Motorola's DSP56300 DSP56300 family of devices using its memory and peripheral expansion port. 2.1 DSP56300 DSP56300 Control Signals Only the DSP control signals used in the memory implementation examples in this note are described below. Other memory configuration implementations may require other support features, which the DSP56300 DSP56300 family of devices have available to assist the designer. These additional memory control signals are described in the Port A Chapter of the DSP56300 DSP56300 24-Bit Digital Signal Processor Family Manual. · Read Data Enable (RD)-An active low output signal that is asserted during an external memory or peripheral read access. · Write Data Enable (WR)-An active low output signal that is asserted during an external memory or peripheral write access. · Address Bus (A0­A17)-Eighteen address lines that allow the DSP563003 DSP563003 to directly address 256K words of external memory or peripherals. These active high output signals are asserted only during external memory or peripheral read or write accesses. These signal lines maintain state when external memory spaces are not being accessed. · Data Bus (D0­D23)-Twenty-four data lines on the DSP56303 DSP56303 that are active high bidirectional signals asserted only during external program and data memory accesses. These signal lines maintain state when external memory spaces are not being accessed. · Address Attribute/Row Address Strobe (AA[0­3]/RAS[0­3])-Four Address Attribute or Row Address Strobe signals. When the Address Attribute, AA, option is selected for these signal lines, they can function as chip selects or additional address lines. When the Row Address Strobe, RAS, option is selected for these signal lines, they can function as Row Address Strobe lines for DRAM interfacing. 2.2 DSP56300 DSP56300 External Memory Timing The DSP56300 DSP56300 family derives its core clock from one of various sources (see PLL and Clock Generator chapter in the DSP56300 DSP56300 24-Bit Digital Signal Processor Family Manual for details). All memory interface timings are derived from the period of the DSP core clock. For example, if the DSP core clock frequency is 80 MHz, then the memory timings are based on a 12.5 nS clock cycle time, and an external memory typically requires less than 12.5 nS access time for one DSP wait state operation. However, these timings are affected by several factors, such as the use of the Phase Lock Loop, the use of an external frequency over or under 4 MHz, the source of the external frequency, and propagation delays in the DSP itself. Any of these factors can cause this value to deviate from 12.5 nS. Table 2-1 represents expected required memory performance data at an 80 MHz DSP core frequency and various wait states using the DSP56303 DSP56303. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 2 Table 2-1. External Memory Speeds with DSP Wait States External Clock (MHz) DF MF PDF WS Core Clock (MHz) TC (nS) tAA ­ max (nS) tAW ­ min (nS) 4.00 1 20 1 1 80.00 12.5 12.4 17.9 4.00 1 20 1 2 80.00 12.5 24.9 30.4 4.00 1 20 1 3 80.00 12.5 37.4 42.9 4.00 1 20 1 4 80.00 12.5 49.9 55.4 4.00 1 20 1 5 80.00 12.5 62.4 67.9 4.00 1 20 1 6 80.00 12.5 74.9 80.4 4.00 1 20 1 7 80.00 12.5 87.4 92.9 4.00 1 20 1 8 80.00 12.5 99.9 105.4 4.00 1 20 1 9 80.00 12.5 112.4 117.9 4.00 1 20 1 10 80.00 12.5 124.9 130.4 4.00 1 20 1 11 80.00 12.5 137.4 142.9 4.00 1 20 1 12 80.00 12.5 149.9 155.4 4.00 1 20 1 13 80.00 12.5 162.4 167.9 4.00 1 20 1 14 80.00 12.5 174.9 180.4 4.00 1 20 1 15 80.00 12.5 187.4 192.9 4.00 1 20 1 16 80.00 12.5 199.9 205.4 4.00 1 20 1 17 80.00 12.5 212.4 217.9 4.00 1 20 1 18 80.00 12.5 224.9 230.4 4.00 1 20 1 19 80.00 12.5 237.4 242.9 4.00 1 20 1 20 80.00 12.5 249.9 255.4 DF = PLL Division Factor MF = PLL Multiplication Factor PDF = PLL Pre-Division Factor WS = wait states TC = Clock Cycle Time tAA = Data access time (i.e., address and AA valid to input data valid) tAW = Data access time (i.e., address and AA valid to WR deassertion) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Interface Overview Interface Overview When reading from external asynchronous memory, the DSP56303 DSP56303 memory read access is controlled by the following steps. 1. The required memory address is asserted. The memory address is created by combining the address bus, A0­A17, and the Address Attributes, AA0­AA3. 2. After a delay of tAR (i.e., address valid to RD assertion time), the Read enable signal, RD, is asserted. 3. Before a delay of tOE (i.e., RD assertion to input data valid), the memory device puts valid data on the data bus. 4. The DSP latches the data bus data and deasserts RD. The DSP does not require any data hold time, tOHZ, after deassertion of the RD signal. The data access time, tAA (i.e., address and AA valid to input data valid), is the time delay typically used by memory devices to specify data access timing. The tAA for a memory device must be less than or equal to the DSP's tAA time for valid data transfers. A0­A17 AA0­AA3 tAR RD tOE D0­D23 tOHZ Valid Data tAA Figure 2-1. External Memory Bus Asynchronous Read Timing 2.2.2 DSP56303 DSP56303 External Memory Bus Asynchronous Write Timing When writing to external asynchronous memory, the DSP56303 DSP56303 memory write access is controlled by the following steps. 1. The memory select address is asserted. The memory select address is created by combining the Address bus, A0­A17, and the Address Attributes AA0­AA3. 2. After a delay of tAS-address valid to WR assertion time-the Write enable signal, WR, is asserted. 3. Before a delay of tWA-WR assertion to output data valid-the DSP places valid data on the data bus. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 2.2.1 DSP56303 DSP56303 External Memory Bus Asynchronous Read Timing Interface Overview 5. Then the DSP deasserts the address and address attributes after tWR-WR deassertion to address not valid-while holding the data valid for tDH. The data access time, tAW (i.e., address and AA valid to WR deassertion), is typically the critical timing specification for memory devices. The tAW for a memory device must be less than or equal to the DSP's tAW time for valid data transfers. A0­A17 AA0­AA3 tAW tWR WR tAS tWA D0­D23 tDW tDH Valid Data Figure 2-2. External Asynchronous Memory Bus Write Timing 2.3 DSP56303 DSP56303 Memory Control Registers You must configure the following control registers to access external memory or peripherals properly when using the DSP56303 DSP56303: · DSP PLL and Clock Generation register · Bus Control Register · DRAM Control Register (if DRAM is used) · Address Attribute Registers Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 4. After a delay of tDW-data valid to WR deassertion (data setup time)-the DSP deasserts the WR signal. Interface Overview You must set the core speed of the DSP for optimum processor and memory performance by configuring the DSP PLL and Clock Generation in the PLL Control (PCTL) register. For detailed information on the PCTL register, see the PLL and Clock Generator chapter in the DSP56300 DSP56300 24-Bit Digital Signal Processor Family Manual. The PLL Control register is an X data I/O mapped 24-bit register. The PCTL register can be separated into four sub-functions: · Frequency Predivider-The input clock frequency can be pre-divided before passing it to the PLL loop frequency multiplier. This frequency predivider has a programmable Division Factor range of 1 to 16. It is set by controlling the values placed in the PCTL register bits 20­23. The Division Factor is the binary value stored in bits 20­23, plus one. · PLL Loop Frequency Multiplier-The clock frequency output from the predivider is multiplied by the voltage-controlled oscillator (VCO). The Multiplication Factor is set by the value in the PCTL register bits 0­11. The Multiplication Factor is the binary value stored in bits 0­11, plus one. · Frequency Low-power Divider-The Low-power Divider (LPD) can divide the output frequency of the VCO before it is used by the DSP core. This frequency low power divider has a programmable Division Factor range of 1 to 128. It is set by controlling the values placed in the PCTL register bits 12­14. The low-power division factor is 2n, where n is the value in PCTL bits 12­14. · Frequency Control Bits-The following five control bits control the input frequency source, the PLL during Stop mode, the activation of the PLL VCO, and the external availability of the core clock: - Crystal frequency is less than 200 kHz, Bit 15 - Disable XTAL drive output, Bit 16 - PLL runs during STOP mode, Bit 17 - Enable PLL operation, Bit 18 - Disable core clock output, Bit 19 The operating core frequency of the chip is set by the control bits in the PCTL register as follows: F EXTAL × MF F CORE = -PDF × DF where · FCORE is the DSP core frequency. · FEXTAL is the external input frequency source present on the EXTAL pin. · PDF is the Predivider Factor defined by the PD0­PD3 bits in PCTL. · MF is the PLL Multiplication Factor defined by the MF0­MF11 bits in PCTL. · DF is the Division Factor defined by the DF0­DF2 bits in PCTL. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 2.3.1 DSP PLL and Clock Generation Interface Overview The Bus Control Register (BCR) is a 24-bit X data I/O register that controls the external bus wait states generated for each Address Attribute area 0­3 and assigns a default value to all memory areas not covered by an Address Attribute area. Each area can have up to 31 wait states. Select the correct number of wait states for each memory configuration using this register. · Wait states for Address Attribute area 0, allowing 0­31 wait states, Bits 0­4 · Wait states for Address Attribute area 1, allowing 0­31 wait states, Bits 5­9 · Wait states for Address Attribute area 2, allowing 0­7 wait states, Bits 10­12 · Wait states for Address Attribute area 3, allowing 0­7 wait states, Bits 13­15 · Wait states for address areas not specified by areas 0­3, allowing 0­31 wait states, Bits 16­20 · The bus state status, Bit 21 · Enable Bus Lock Hold, Bit 22 · Enable Bus Request Hold, Bit 23 2.3.3 Address Attribute Control Registers (AAR0­AAR3) Four 24-bit Address Attribute Control registers in the X data I/O memory space control the activity of the AA0­AA3/RAS0­RAS3 pins. Each AA/RAS pin is asserted if the address and memory space of the appropriate AARx matches the requested external memory address and address space. · Specify external memory access type; select from Synchronous SRAM, Asynchronous SRAM, and DRAM accesses, Bits 0­1 · Pull the AA pin high, Bit 2 · Activate the AA pin during external program space accesses, Bit 3 · Activate the AA pin during external X data space accesses, Bit 4 · Activate the AA pin during external Y data space accesses, Bit 5 · Move the eight least significant bits of the address to the eight most significant bits of the external address bus, Bit 6 · Enable the internal packing/unpacking logic during external DMA accesses, Bit 7 · Specify the number of address bits to compare, allowing the use of 0­12 address bits, Bits 8­11 · Specify the most significant portion of the address to compare, Bits 12­23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 2.3.2 Bus Control Register (BCR) Interface Overview The Operating Mode Register (OMR) is a 24-bit I/O register that selects the operating mode of the DSP, external memory controls, and stack extension controls. The following flags are applicable to memory interfacing: · The DSP operating mode is specified by MA­MD, Bits 0­3. · The External Bus Disable bit disables the external bus controller for power conservation when external memory is not used, Bit 4. · The Memory Switch mode bit reconfigures internal memory spaces, Bit 7. · The Transfer Acknowledge Synchronize Select bit selects the synchronization method for the Transfer Acknowledge (TA) pin, Bit 11. · The Bus Release Timing bit selects between a fast and slow bus release of the BB pin, Bit 12. · The Address Attribute Priority Disable bit allows the Address Attribute pins, AA0­AA3, to be used in any combination, Bit 14. 2.3.5 Status Register (SR) The Status Register (SR) is a 24-bit I/O register that selects and monitors the results of arithmetic computations and the current state of the DSP. The following flags are applicable to memory interfacing: · Sixteen-bit Compatibility mode enables full compatibility with object code written for the DSP56000 DSP56000 family, Bit 13. · Instruction Cache Enable bit enables the instruction cache controller and changes the last 1K of internal program memory into cache memory, Bit 19. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 2.3.4 Operating Mode Register (OMR) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Interface Overview 32K × 8-bit Memory Based Designs 32K × 8-bit Memory Based Designs Using one hardware memory design based on three 32K × 8-bit 5.0 V memories, the DSP56303 DSP56303's Memory Expansion Port allows the 32K × 24-bit memory bank to be logically configured for use in various memory space arrangements. Configuring and using one Memory Expansion Port Address Attribute Control Register, the 32K memory bank can accommodate seven different memory space arrangements: 1. 32K × 24-bit `P' Space Fast SRAM 2. 32K × 24-bit `X' Space Fast SRAM 3. 32K × 24-bit `Y' Space Fast SRAM 4. 32K × 24-bit `P'/'X' Space Fast SRAM 5. 32K × 24-bit `P'/'Y' Space Fast SRAM 6. 32K × 24-bit `X'/'Y' Space Fast SRAM 7. 32K × 24-bit `P'/'X'/'Y' Space Fast SRAM Configuring and using two Memory Expansion Port Address Attribute Control Registers, the 32K memory bank can accommodate thirteen different memory space arrangements: 1. 32K × 24-bit `P' Space Fast SRAM 2. 32K × 24-bit `X' Space Fast SRAM 3. 32K × 24-bit `Y' Space Fast SRAM 4. 32K × 24-bit `P'/'X' Space Fast SRAM 5. 32K × 24-bit `P'/'Y' Space Fast SRAM 6. 32K × 24-bit `X'/'Y' Space Fast SRAM 7. 32K × 24-bit `P'/'X'/'Y' Space Fast SRAM 8. 16K × 24-bit `P'/'X' and 16K × 24-bit `Y' Space Fast SRAM 9. 16K × 24-bit `P'/'Y' and 16K × 24-bit `X' Space Fast SRAM 10. 16K × 24-bit `P' and 16K × 24-bit `X'/'Y' Space Fast SRAM 11. 16K × 24-bit `P' and 16K × 24-bit `X' Space Fast SRAM 12. 16K × 24-bit `P' and 16K × 24-bit `Y' Space Fast SRAM 13. 16K × 24-bit `X' and 16K × 24-bit `Y' Space Fast SRAM All of these memory space configurations efficiently use the full capacity of the memory chips in the 32K × 24-bit memory bank. To illustrate these configurations, the remainder of this chapter presents examples based on one common hardware design using two Address Attribute Selectors that implement three of the most common configurations: 32K × 24-bit `P' Space Fast SRAM, 32K × 24-bit `P'/'X'/`Y' Space Fast SRAM configuration, and a 16K × 24-bit `P'/'X' and 16K × 24-bit `Y' Space Fast SRAM configuration (see Figure 3-4 for a schematic of the hardware design). Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 3 32K × 8-bit Memory Based Designs This section describes an asynchronous Fast SRAM 32K × 24-bit memory bank implementation using Motorola's MCM6206D MCM6206D device. Figure 3-1 displays the block diagram. Memory bank designs of this size and type can use very low-cost 5.0 V memory devices to satisfy the majority of embedded designs. The memory bank design uses two Address Attribute Selectors. However, the 32K × 24-bit `P' Space and 32K × 24-bit `P'/'X'/'Y' Space Fast SRAM configurations can use a one Address Attribute Selector design with A14 substituted for AA2. The two Address Attribute Selector design demonstrates the ultimate flexibility of the Address Attribute Selectors. For this common hardware design, the DSP core runs at a maximum of 80 MHz, and the input frequency source is a 4.000 MHz crystal. The asynchronous Fast SRAM requires an access time equal to or less than 12.4 nS to satisfy the DSP's one wait state external memory requirements. This 5 V memory device is organized as 32K × 8-bits. Therefore, three memory devices are used to achieve the 24-bit wide bus. Since the DSP's data bus is not 5 V tolerant, level conversion to and from 3.3 V and 5 V is necessary on the 24-bit data to accommodate the 5 V memory devices. This is accomplished by using three Quality Semiconductor's QS3245 QS3245 QuickSwitch® 8-bit bus switches. These switches allow the connection of a 3.3 V CMOS logic DSP data bus on one side and 5 V TTL-compatible logic, memory devices on the other side, effectively providing a 3.3 V-to-5 V level conversion without adding any significant (0.25 nS) propagation delay. D0­D7 D8­D15 D16­D23 Lvl Cnv Data DSP56303 DSP56303 Data Data MCM6206D MCM6206D MCM6206D MCM6206D MCM6206D MCM6206D Addr E Addr E Addr E A0­A13, AA2 AA3 Figure 3-1. 32K × 24-bit Fast SRAM Memory Example 3.1.1 MCM6206D-12 MCM6206D-12 Memory Timing Requirements For the asynchronous Fast SRAM device to work properly, its timing requirements must be met. Following are the timing requirements for the MCM6206D-12 MCM6206D-12 32K × 8-bit 12 nS Fast SRAM. 3.1.1.1 MCM6206D-12 MCM6206D-12 Read Cycle Timing Table 3-1 shows the memory read timing specification values in the memory read cycle timing diagram, Figure 3-2. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 3.1 32K × 24-bit Common Fast SRAM Hardware Design 32K × 8-bit Memory Based Designs Read Cycle Parameter Symbol Min Max Read Cycle Time tAVAV 12 nS - Address Access Time tAVQV - 12 nS Enable Access Time tELQV - 12 nS Output Enable Access Time tGLQV - 6 nS Enable High to Output High-Z tEHQZ 0 nS 7 nS Output Enable High to Output High-Z tGHQZ 0 nS 6 nS tAVAV A0­A14 tELQV E Chip Enable) tEHQZ G Output Enable) tGHQZ tGLQV D0­D7 (Data Out) Valid Data tAVQV Figure 3-2. MCM6206D-12 MCM6206D-12 Memory Read Cycle Timing Diagram 3.1.1.2 MCM6206D-12 MCM6206D-12 Write Cycle Timing Table 3-2 shows the memory write timing specification values in the memory write cycle timing diagram, Figure 3-3. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Table 3-1. MCM6206D-12 MCM6206D-12 Memory Read Timing Specifications 32K × 8-bit Memory Based Designs Write Cycle Parameter Symbol Min Max Write Cycle Time tAVAV 12 nS - Address Setup Time tAVWL 0 nS - Address Valid to End off Write tAVWH 10 nS - Write Pulse Width tWLWH 10 nS - Data Valid to End of Write tDVWH 6 nS - Data Hold Time tWHDX 0 nS - Write Recovery Time tWHAX 0 nS - tAVAV A0­A14 tWHAX tAVWH E Chip Enable) tWLWH W Write Enable) D0­D7 (Data In) tAVWL tDVWH tWHDX Valid Data Figure 3-3. MCM6206D-12 MCM6206D-12 Memory Write Cycle Timing Diagram Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Table 3-2. MCM6206D-12 MCM6206D-12 Memory Write Timing Specifications Figure 3-4. 32K × 24-bit Fast SRAM Schematic AA2 AA1 IRQA\ NMI\ TCK IRQD\ IRQC\ TA\ BG\ R11 4.7K R12 4.7K R13 4.7K 4.000MHz 680K Y1 C6 20pF 33 32 31 137 136 135 134 24 23 21 22 30 C4 +3.3V TCK C10 .1uF NMI\ 56 57 65 74 80 86 91 95 103 111 119 126 129 8 18 25 38 45 55 53 46 6 59 11 144 143 16 2 1 12 4 3 17 7 10 13 14 15 29 28 27 142 141 140 139 TRST\ 138 5 RESET\ 44 IRQA\ IRQB\ IRQC\ IRQD\ 0.015uF C8 .1uF C9 1uF +3.3V C7 1uF +3.3V IRQB\ 4.7K 4.7K 4.7K 4.7K BB\ R10 4.7K R9 R8 R7 R6 4.7K R4 4.7K R5 AA3 R3 4.7K A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 SGND QGND SGND HGND PGND PGND1 QGND CGND CGND AGND AGND AGND QGND AGND DGND DGND DGND QGND DGND RD WR BB BR TA BG CAS BCLK BCLK AA0/RAS0 AA1/RAS1 AA2/RAS2 AA3/RAS3 DSP56303PV80 DSP56303PV80 QVCC CVCC CVCC AVCC AVCC AVCC QVCC AVCC DVCC DVCC DVCC QVCC DVCC SVCC QVCC SVCC HVCC PVCC EXTAL XTAL PCAP PINIT/NMI CLKOUT SC10/PD0 SC10/PD0 SC11/PD1 SC11/PD1 SC12/PD2 SC12/PD2 SCK1/PD3 STD1/PD5 SRD1/PD4 SC00/PC0 SC00/PC0 SC01/PC1 SC01/PC1 SC02/PC2 SC02/PC2 SCK0/PC3 SRD0/PC4 STD0/PC5 RXD/PE0 TXD/PE1 SCLK/PE2 TIO0 TIO1 TIO2 TMS TCK TDI TDO TRST DE RESET MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD HREQ/HTREQ/HP14 HREQ/HTREQ/HP14 HACK/HRREQ/HP15 HACK/HRREQ/HP15 HR/W/HDR/HP12 HR/W/HDR/HP12 HDS/HWR/HP11 HDS/HWR/HP11 HCS/HA10/HP13 HCS/HA10/HP13 HA0/HAS/HP8 HA1/HA8/HP9 HA2/HA9/HP10 HA2/HA9/HP10 HD0/HP0 HD1/HP1 HD2/HP2 HD3/HP3 HD4/HP4 HD5/HP5 HD6/HP6 HD7/HP7 U1 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DA14 DA15 DA16 DA17 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 9 19 26 39 47 48 54 58 66 75 81 87 90 96 104 112 120 127 130 TA\ BG\ RD\ WR\ BB\ 70 69 51 50 68 67 64 63 62 71 52 60 61 AA2 AA3 72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 100 101 102 105 106 107 108 109 110 113 114 115 116 117 118 121 122 123 124 125 128 131 132 133 D[0.23] 10 19 2 3 4 5 6 7 8 9 10 19 2 3 4 5 6 7 8 9 10 19 2 3 4 5 6 7 8 9 TRST\ RESET\ D16 D17 D18 D19 D20 D21 D22 D23 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 VCC B0 B1 B2 B3 B4 B5 B6 B7 VCC B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 .1uF C2 20 18 17 16 15 14 13 12 11 .1uF C1 20 18 17 16 15 14 13 12 11 2 1N4001 1N4001 D3 VCC 1 3 +5V +3.3V +5V DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 1N4001 1N4001 D2 +5V DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 1N4001 1N4001 D1 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DA[0.17] GND DS1233DZ DS1233DZ RESET U8 OE VCC 20 GND C3 QS3245SO QS3245SO .1uF A0 A1 A2 A3 A4 A5 A6 A7 U4 QS3245SO QS3245SO GND OE A0 A1 A2 A3 A4 A5 A6 A7 U3 QS3245SO QS3245SO GND OE A0 A1 A2 A3 A4 A5 A6 A7 U2 U5 U6 Motorola, Inc. DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 AA2 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 AA2 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 AA2 6501 William Cannon Drive West Austin, TX 78735-8598 Title DSP56303 DSP56303 32Kx24-bit 5.0V FSRAM INTERFACE Size Document Number REV B FSRAM1.SCH 1.0 Date: January 22, 1997 Sheet 1 of 1 D0 D1 D2 D3 D4 D5 D6 D7 U7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 AA3 20 E A10 21 A11 23 WR\ 27 W A12 2 A13 26 RD\ 22 G A14 1 MCM6206DJ12 MCM6206DJ12 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 AA3 20 E A10 21 A11 23 WR\ 27 W A12 2 A13 26 RD\ 22 G A14 1 MCM6206DJ12 MCM6206DJ12 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 AA3 20 E A10 21 A11 23 WR\ 27 W A12 2 A13 26 RD\ 22 G A14 1 MCM6206DJ12 MCM6206DJ12 11 12 13 15 16 17 18 19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 C5 20pF AA0 R1 4.7K R2 4.7K R14 +3.3V 43 42 41 40 37 36 35 34 32K × 8-bit Memory Based Designs 32K × 8-bit Memory Based Designs This section describes a 32K × 24-bit `P' memory space, asynchronous Fast SRAM implementation using Motorola's MCM6206D MCM6206D device. Figure 3-5 shows the memory map layout, Figure 3-1 shows the block diagram, and Example 3-1 shows the example code. The DSP core runs at 80 MHz, and the input frequency source is a 4.000 MHz crystal. The asynchronous Fast SRAM requires an access time equal to or less than 12.4 nS to satisfy the DSP's one wait state external memory requirements. Program Reserved $FF00C0 FF00C0 $FF0000 FF0000 Bootstrap ROM X Data Y Data Internal I/O Internal I/O External External Reserved Reserved External $FFFFFF External Internal 2K SRAM Internal 2K SRAM $FFFFC0 $FFF000 FFF000 $FF0000 FF0000 External $108000 External 32K SRAM $100000 $001000 $000C00 000C00 External Internal 1K Cache Internal 3K SRAM $000000 $000800 $000000 Figure 3-5. 32K × 24-bit `P' Space Fast SRAM Memory Map 3.2.1 DSP56303 DSP56303 Port A Timing Requirements and Register Settings For optimal use of the 32K × 24-bit `P' space memory configuration, set up the following DSP control registers. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 3.2 32K × 24-bit `P' Space Fast SRAM Example Set up the core speed of the DSP for optimum processor and memory performance using the DSP PLL and Clock Generation (PCTL) register. For this example, the DSP core runs at 80 MHz, and the input frequency source is a 4.000 MHz crystal. The PCTL register value combines the following bits for each feature: · Desired Core Frequency = 80 MHz · Given the External Frequency = 4.000 MHz · Predivider value = 1, bits 20­23 = $0 · Low-power Divider value = 1, bits 12­14 = $0 · VCO Multiplication value = 20, bits 0­11 = $013 · Crystal less than 200 kHz, Bit 15 = 0 · Disable XTAL drive output, Bit 16 = 0 · PLL runs during STOP, Bit 17 = 1 · Enable PLL operation, Bit 18 = 1 · Disable core clock output, Bit 19 = 1 The value loaded into the PCTL register is $0E0013 0E0013. Address Attribute Pin 3 enables, via Fast SRAM E, external 32K SRAM bank accesses in the address range from $100000 to $107FFF 107FFF during program space requests. Configure the memory address space requirements for the Address Attribute Pin 3 using Address Attribute Register 3 (AAR3). The AAR3 value combines the following bits for each feature: · Specify the external memory access type as asynchronous SRAM, Bits 0­1 = $1. · Pull the AA pin high when selected, Bit 2 = 0. · Activate the AA pin during external program space accesses, Bit 3 = 1. · Activate the AA pin during external X data space accesses, Bit 4 = 0. · Activate the AA pin during external Y data space accesses, Bit 5 = 0. · Move the eight least significant bits of the address to the eight most significant bits of the external address bus, Bit 6 = 0. · Enable the internal packing/unpacking logic during external DMA accesses, Bit 7 = 0 · Specify the number of address bits to compare, Bits 8­11 = $9 · Specify the most significant portion of the address to compare, Bits 12­23 = $100 The value loaded into the AAR3 is $100909. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs Address Attribute Pin 2 selects, via Fast SRAM A14, address line A14 in the external 32K SRAM bank during accesses in the address range from $100000 to $107FFF 107FFF during program space requests. Configure the memory address space requirements for the Address Attribute Pin 2 using Address Attribute Register 2 (AAR2). The AAR2 value combines the following bits for each feature: · Specify the external memory access type as asynchronous SRAM, Bits 0­1 = $1. · Pull the AA pin high when selected, Bit 2 = 1. · Activate the AA pin during external program space accesses, Bit 3 = 1. · Activate the AA pin during external X data space accesses, Bit 4 = 0. · Activate the AA pin during external Y data space accesses Bit 5 = 0. · Move the eight least significant bits of address to eight most significant bits of the external address bus, Bit 6 = 0. · Enable the internal packing/unpacking logic during external DMA accesses, Bit 7 = 0. · Specify the number of address bits to compare, Bits 8­11 = $A · Specify the most significant portion of the address to compare, Bits 12­23 = $104 The value loaded into the AAR2 is $104A0D 104A0D. The value loaded into AAR0 and AAR1 is $000000. Select the proper number of wait states for the memory configuration using the Bus Control Register (BCR). The BCR value combines the following bits for each feature: · Address Attribute area 0 wait states, Bits 0­4 = $0 · Address Attribute area 1 wait states, Bits 5­9 = $0 · Address Attribute area 2 wait states, Bits 10­12 = $1 · Address Attribute area 3 wait states, Bits 13­15 = $1 · Default address area wait states, Bits 16­20 = $0 · Bus state status, Bit 21 = 0 · Enable Bus Lock Hold, Bit 22 = 0 · Enable Bus Request Hold, Bit 23 =0 The value loaded into the BCR is $002400. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 32K × 8-bit Memory Based Designs · MA­MD bits select the DSP operating mode, Bits 0­3 = $0. · External Bus Disable bit disables the external bus controller for power conservation when external memory is not used, Bit 4 = $0. · Memory Switch Mode bit reconfigures internal memory spaces, Bit 7 = $0. · Transfer Acknowledge Synchronize Select bit selects the synchronization method for the Transfer Acknowledge (TA) pin, Bit 11 = $0. · Bus Release Timing bit selects between a fast and slow bus release of the BB pin, Bit 12 = $0. · Address Attribute Priority Disable bit allows the Address Attribute pins, AA0­AA3, to be used in any combination, Bit 14 = $1. · All other OMR bits are selected for their defaults of $000000. The value loaded into the OMR is $004000. Configure the memory mode of the DSP using the Status Register (SR). The SR value combines the following bits for each feature: · Sixteen-Bit Compatibility mode enables full compatibility to object code written for the DSP56000 DSP56000 family of DSPs, Bit 13 = $0. · Instruction Cache Enable bit enables the instruction cache controller and changes the last 1K of internal program memory into cache memory, Bit 19 = $1. · All other Status Register bits are selected for their defaults of $000000. The value loaded into the SR is $080000, which is the value loaded during reset. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Configure the operating mode and external memory controls using the Operating Mode Register. The OMR value combines the following bits for each feature: 32K × 8-bit Memory Based Designs Example 3-1. 32K × 24-bit `P' Space Fast SRAM Memory Exercise Program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Version 6.0.1.6 page ; ; ; ; ; ; 100000 108000 008000 ASRAM1.ASM 97-01-25 08:05:13 asram1.asm 132,60,3,3, - Simple program to test 32Kx24-bits of program memory using a DSP56303 DSP56303 The program uses Internal P:RAM to test External P:RAM from $100000 - $107FFF 107FFF @ 1w/s PMemStart PMemEnd PMemSize equ equ equ $100000 $108000 PMemEnd-PMemStart 000003 ;- Program Specific MEM_FAIL_ADDRESS equ MEM_FAIL_WROTE equ MEM_FAIL_READ equ MEM_PASS_COUNTER equ FFFFFB FFFFFD FFFFF6 FFFFF7 BCR PCTL AAR3 AAR2 000000 000000 000013 000000 000000 020000 040000 080000 0E0013 0E0013 ;- PCTL prediv lowdiv pllmul crystal disXTAL pllstop enpll disclk PCTL_value 000001 000000 000008 000000 000000 000000 000000 000900 100000 ;- AAR3 value = 0x100909 acctype3 equ 1 aahigh3 equ 0 aap3 equ $8 aax3 equ 0 aay3 equ 0 aswap3 equ 0 enpack3 equ 0 nadd3 equ $000900 msadd3 equ $100000 000000 000001 000002 100909 000001 000004 000008 000000 000000 000000 000000 000A00 000A00 104000 104A0D 104A0D 000000 000000 000400 002000 000000 Storage Locations (X DATA SPACE) $000000 $000001 $000002 $000003 ;- DSP56303 DSP56303 Control Registers (X I/O SPACE) equ $FFFFFB ; Bus Control Register equ $FFFFFD ; PLL Control Register equ $FFFFF6 ; Address Attribute Register #3 equ $FFFFF7 ; Address Attribute Register #2 value = 0x0E0013 equ 0 ; Pre-Divider = 1 equ 0 ; Low Power Divider = 1 equ 19 ; VCO Mult = 20; (19+1)*4.00MHz=80.00MHz equ 0 ; No, Crystal not less than 200kHz equ 0 ; No, do not disable crystal use equ $020000 ; Yes, PLL runs during STOP equ $040000 ; Yes, enable PLL operation equ $080000 ; Yes, disable CORE clock output equ ; External Memory access type = 0x1 ; Enable AA3 pin to be low when selected ; Yes, Enable AA3 pin on ext `P' accesses ; No, Enable AA3 pin on ext `X' accesses ; No, Enable AA3 pin on ext `Y' accesses ; No, Enable address bus swap ; No, Enable packing/unpacking logic ; Compare 9 address bits ; Most significant portion of address, ; $100000 - $107fff, to compare. ; (0001,0000,0xxx,xxxx,xxxx,xxxx) AAR3_value equ ;- AAR2 value = 0x104A0D acctype2 equ 1 aahigh2 equ $4 aap2 equ $8 aax2 equ 0 aay2 equ 0 aswap2 equ 0 enpack2 equ 0 nadd2 equ $000A00 000A00 msadd2 equ $104000 AAR2_value equ ; External Memory access type = 0x1 ; Enable AA2 pin to be high when selected ; Yes, Enable AA2 pin on ext `P' accesses ; No, Enable AA2 pin on ext `X' accesses ; No, Enable AA2 pin on ext `Y' accesses ; No, Enable address bus swap ; No, Enable packing/unpacking logic ; Compare 10 address bits ; Most significant portion of address, ; $104000 - $107fff, to compare. ; (0001,0000,01xx,xxxx,xxxx,xxxx) ;- BCR value = 0x002400 aaa0ws equ 0 aaa1ws equ 0 aaa2ws equ $000400 aaa3ws equ $002000 defws equ 0 ; ; ; ; ; Address Address Address Address Default Attribute Area 0 Attribute Area 1 Attribute Area 2 Attribute Area 3 Address Area w/s w/s w/s w/s w/s = 0 = = = = 0 0 0 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Motorola DSP56300 DSP56300 Assembler 75 76 77 78 79 80 81 82 83 84 85 86 000000 000000 000000 002400 busss enblh enbrh BCR_value P:000100 org 87 P:000102 88 P:000104 89 P:000106 90 P:000108 91 P:00010A 92 93 P:00010C 00010C 94 P:00010E 00010E 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 equ equ equ equ 0 ; Bus state status = 0 0 ; Enable Bus Lock Hold = 0 0 ; Enable Bus Request Hold = 0 ;-p:$100 ;Keep the program in internal RAM memtst P:000100 P:000110 P:000111 P:000112 P:000113 P:000114 P:000115 P:000116 08F4BD 08F4BD 0E0013 0E0013 05F43A 05F43A 004000 05F439 05F439 080000 08F4BB 08F4BB 002400 08F4B7 08F4B7 104A0D 104A0D 08F4B6 08F4B6 100909 05F420 05F420 FFFFFF 05F423 05F423 FFFFFF 20001B 20001B 000000 570000 570100 570200 570300 ; Initialization Section movep #PCTL_value,x:PCTL ; Set PLL Control Register movec #$004000,OMR ; Disable Address Attribute Priority movec #$080000,SR ; Enable 1K Cache movep #BCR_value,x:BCR ; Set external wait states movep #AAR2_value,x:AAR2 ; Set Address Attribute Reg2 movep #AAR3_value,x:AAR3 ; Set Address Attribute Reg3 move #-1,m0 ; Set LINEAR addressing mode move #-1,m3 clr nop move move move move b b,x:MEM_FAIL_ADDRESS b,x:MEM_FAIL_WROTE b,x:MEM_FAIL_READ b,x:MEM_PASS_COUNTER ; ; ; ; Initialize Initialize Initialize Initialize Failed Address -> $000000 Expected Data -> $000000 Data Read -> $000000 Pass Counter -> $000000 main ;-;- fill P:memory with initial pattern -;-move #PATT,r3 ; r3 points to Test Patterns P:000118 P:000119 63F400 63F400 000138 000000 000000 P:00011A 07DB84 07DB84 move p:(r3)+,x0 P:00011B 00011B 70F400 70F400 008000 move #PMemSize,n0 ; Get memory size P:00011D 00011D 60F400 60F400 100000 move #PMemStart,r0 ; Get starting address for fill P:00011F 00011F P:000120 06D820 06D820 075884 rep move n0 x0,p:(r0)+ ; Fill RAM with first pattern data P:000121 129 P:000123 130 131 132 133 134 P:000125 P:000126 135 136 137 138 139 140 141 P:000129 P:00012A P:00012B 00012B P:00012C 00012C P:00012D 00012D P:000127 nop nop ; Get the Write Pattern for P:MEM ;-;- Check for expected pattern data in each RAM location -;- and then replace with a new data pattern. -;- .This provides an address check. Since erroneous -;- .addressing will cause the data to be written into -;- .incorrect locations and this will be evident in -;- .the next read pass. -;-063890 DOR #PATTN,test_Pm ; Start Pattern Test Loop 00000D 00000D 60F400 60F400 move #PMemStart,r0 ; Get starting address of Test Memory 100000 200041 tfr x0,a ; Save the last test pattern -> a 07DB84 07DB84 move P:(r3)+,x0 ; Get the next test pattern -> x0 06D810 06D810 DOR 000006 07E085 07E085 move 200065 cmp 052409 bne 075884 move 000000 nop next_loc n0,next_loc P:(r0),x1 x1,a RAM Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 142 P:00012E 00012E 000000 nop ; Time to start next test pattern 143 144 test_Pm 145 146 ; One Pass Complete 147 ; All test patterns have been tried and passed in external RAM 148 P:00012F 00012F 518300 move x:MEM_PASS_COUNTER,b0 149 P:000130 000009 inc b ; Update pass loop counter 150 P:000131 000000 nop 151 P:000132 510300 move b0,x:MEM_PASS_COUNTER 152 153 P:000133 050FC3 050FC3 bra main ; Do it all over again 154 155 ;-156 ; ERR-handles error messaging with user 157 ; 158 ; Expected Data -> a 159 ; Read Data -> x1 160 ; Address of failure -> r0 161 162 ERR 163 P:000134 600000 move r0,x:MEM_FAIL_ADDRESS ; Save off address of failure 164 P:000135 560100 move a,x:MEM_FAIL_WROTE ; Save off expected data 165 P:000136 450200 move x1,x:MEM_FAIL_READ ; Save off data read 166 167 P:000137 050C00 050C00 bra * ; Dynamically HALT here 168 169 170 ; Memory Test Patterns 171 172 P:000138 PATT dc $000000,$FFFFFF,$AAAAAA,$555555,$2BAD2C 173 P:00013D 00013D dc $800000,$400000,$200000,$100000 174 P:000141 dc $080000,$040000,$020000,$010000 175 P:000145 dc $008000,$004000,$002000,$001000 176 P:000149 dc $000800,$000400,$000200,$000100 177 P:00014D 00014D dc $000080,$000040,$000020,$000010 178 P:000151 dc $000008,$000004,$000002,$000001 179 P:000155 dc $7FFFFF,$BFFFFF,$DFFFFF,$EFFFFF 180 P:000159 dc $F7FFFF,$FBFFFF,$FDFFFF,$FEFFFF 181 P:00015D 00015D dc $FF7FFF,$FFBFFF,$FFDFFF,$FFEFFF 182 P:000161 dc $FFF7FF,$FFFBFF,$FFFDFF,$FFFEFF 183 P:000165 dc $FFFF7F,$FFFFBF,$FFFFDF,$FFFFEF 184 P:000169 dc $FFFFF7,$FFFFFB,$FFFFFD,$FFFFFE 185 P:00016D 00016D dc $FEDCBA,$123456,$012345,$EDCBA9 186 187 000038 PATTN equ *-PATT-1 188 189 end memtst 0 Errors 0 Warnings Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 32K × 8-bit Memory Based Designs This section describes a 32K × 24-bit shared `P'/'X'/`Y' memory space, asynchronous Fast SRAM implementation using Motorola's MCM6206D MCM6206D device. Figure 3-7 shows the memory map layout, Figure 3-1 shows the block diagram, and Example 3-2 shows the example code. A shared memory space means that data written to one address in one memory space can be accessed by the same address in another memory space, (e.g., writing $012345 to P:$100000 could be read by X:$100000, Y:$100000 or P:$100000). The DSP core runs at 80 MHz, and the input frequency source is a 4.000 MHz crystal. The asynchronous Fast SRAM requires an access time equal to or less than 12.4 nS to satisfy the DSP's one wait state external memory requirements. Program X Data Internal I/O Internal I/O External External Bootstrap ROM Reserved Reserved External External External Shared External 32K SRAM Shared External 32K SRAM Shared External 32K SRAM External External Internal 2K SRAM Internal 2K SRAM $FFFFFF Reserved $FF00C0 FF00C0 $FF0000 FF0000 Y Data $FFFFC0 $FFF000 FFF000 $FF0000 FF0000 $108000 $100000 $001000 $000C00 000C00 External Internal 1K Cache Internal 3K SRAM $000000 $000800 $000000 Figure 3-6. 32K × 24-bit `P'/'X'/'Y' Fast SRAM Memory Map 3.3.1 DSP56303 DSP56303 Port A Timing Requirements and Register Settings For optimal use of the 32K × 24-bit `P'/'X'/`Y' space memory configuration, set up the following DSP control registers. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 3.3 32K × 24-bit `P'/'X'/`Y' Fast SRAM Example You must set the core speed of the DSP for optimum processor and memory performance using the DSP PLL and Clock Generation (PCTL) register. For this example, the DSP core runs at 80 MHz and the input frequency source is a 4.000 MHz crystal. The PCTL register value combines the following bits for each feature: · Desired Core Frequency = 80 MHz · Given the External Frequency = 4.000 MHz · Predivider value = 1, Bits 20­23 = $0 · Low-power Divider value = 1, Bits 12­14 = $0 · VCO Multiplication value = 20, Bits 0­11 = $013 · Crystal less than 200 kHz, Bit 15 = 0 · Disable XTAL drive output, Bit 16 = 0 · PLL runs during STOP, Bit 17 = 1 · Enable PLL operation, Bit 18 = 1 · Disable core clock output, Bit 19 = 1 The value loaded into the PCTL register is $0E0013 0E0013. Address Attribute Pin 3 enables, via Fast SRAM E, external 32K SRAM bank accesses in the address range from $100000 to $107FFF 107FFF during program space requests. Configure the memory address space requirements for the Address Attribute Pin 3 using Address Attribute Register 3 (AAR3). The AAR3 value combines the following bits for each feature: · Specify the external memory access type as asynchronous SRAM, Bits 0­1 = $1. · Pull the AA pin high when selected, Bit 2 = 0. · Activate the AA pin during external program space accesses, Bit 3 = 1. · Activate the AA pin during external X data space accesses, Bit 4 = 1. · Activate the AA pin during external Y data space accesses, Bit 5 = 1. · Move the eight least significant bits of the address to the eight most significant bits of the external address bus, Bit 6 = 0. · Enable the internal packing/unpacking logic during external DMA accesses, Bit 7 = 0. · Specify the number of address bits to compare, Bits 8­11 = $9 · Specify the most significant portion of the address to compare, Bits 12­23 = $100 The value loaded into the AAR3 is $100939. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs Address Attribute Pin 2 selects, via Fast SRAM A14, address line A14 in the external 32K SRAM bank during accesses in the address range from $104000 to $107FFF 107FFF during program space requests. Configure the memory address space requirements for the Address Attribute Pin 2 using the Address Attribute Register 2 (AAR2). The AAR2 value combines the following bits for each feature: · Specify the external memory access type as asynchronous SRAM, Bits 0­1 = $1. · Pull the AA pin high when selected, AAR Bit 2 = 1. · Activate the AA pin during external program space accesses, Bit 3 = 1. · Activate the AA pin during external X data space accesses, Bit 4 = 1. · Activate the AA pin during external Y data space accesses, Bit 5 = 1. · Move the eight least significant bits of the address to the eight most significant bits of the external address bus, Bit 6 = 0. · Enable the internal packing/unpacking logic during external DMA accesses, Bit 7 = 0. · Specify the number of address bits to compare, Bits 8­11 = $A · Specify the most significant portion of the address to compare, Bits 12­23 = $104 The value loaded into the AAR2 is $104A3D 104A3D. The value loaded into AAR0 and AAR1 is $000000. Select the proper number of wait states for the memory configuration using the Bus Control Register (BCR). The BCR value combines the following bits for each feature: · Address Attribute area 0 wait states, Bits 0­4 = $0 · Address Attribute area 1 wait states, Bits 5­9 = $0 · Address Attribute area 2 wait states, Bits 10­12 = $1 · Address Attribute area 3 wait states, Bits 13­15 = $1 · Default address area wait states, Bits 16­20 = $0 · Bus state status, Bit 21 = 0 · Enable Bus Lock Hold, Bit 22 = 0 · Enable Bus Request Hold, Bit 23 = 0 The value loaded into the BCR is $002400. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 32K × 8-bit Memory Based Designs · MA­MD bits specify the DSP operating mode, Bits 0­3 = $0. · External Bus Disable bit disables the external bus controller for power conservation when external memory is not used, Bit 4 = $0. · Memory Switch Mode bit reconfigures internal memory spaces Bit 7 = $0. · Transfer Acknowledge Synchronize Select bit selects the synchronization method for the Transfer Acknowledge (TA) pin, Bit 11 = $0. · Bus Release Timing bit selects between a fast and slow bus release of the BB pin, Bit 12 = $0. · Address Attribute Priority Disable bit allows the Address Attribute pins, AA0­AA3, to be used in any combination, Bit 14 = $1. · All other OMR bits are selected for their defaults of $000000. The value loaded into the OMR is $004000. Configure the memory mode of the DSP using the Status Register (SR). The SR value combines the following bits for each feature: · Sixteen-Bit Compatibility mode enables full compatibility to object code written for the DSP56000 DSP56000 family of DSPs, Bit 13 = $0. · Instruction Cache Enable bit enables the instruction cache controller and changes the last 1K of internal program memory into cache memory, Bit 19 = $1. · All other Status Register bits are selected for their defaults of $000000. The value loaded into the SR is $080000, which is the value loaded during reset. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Configure the operating mode and external memory controls using the Operating Mode Register (OMR). The OMR value is combines the following bits for each feature: 32K × 8-bit Memory Based Designs Motorola DSP56300 DSP56300 Assembler 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Version 6.0.1.6 page ; ; ; ; ; ; 100000 108000 008000 PMemStart PMemEnd PMemSize 97-01-25 08:05:18 asram2.asm 132,60,3,3, ASRAM2.ASM - Simple program to test 32Kx24-bits of Program/X-Data/Y-Data memory using a DSP56303 DSP56303 The program uses Internal P:RAM to test External P/X/Y:RAM from $100000 - $107FFF 107FFF @ 1w/s equ equ equ $100000 $108000 PMemEnd-PMemStart 000003 ;- Program Specific MEM_FAIL_ADDRESS equ MEM_FAIL_WROTE equ MEM_FAIL_READ equ MEM_PASS_COUNTER equ FFFFFB FFFFFD FFFFF6 FFFFF7 ;- DSP56303 DSP56303 Control Registers (X I/O SPACE) BCR equ $FFFFFB ; Bus Control Register PCTL equ $FFFFFD ; PLL Control Register AAR3 equ $FFFFF6 ; Address Attribute Register #3 AAR2 equ $FFFFF7 ; Address Attribute Register #2 000000 000000 000013 000000 000000 020000 040000 080000 0E0013 0E0013 ;- PCTL value = 0x0E0013 prediv equ 0 ; Pre-Divider = 1 lowdiv equ 0 ; Low Power Divider = 1 pllmul equ 19 ; VCO Mult = 20; (19+1)*4.00MHz=80.00MHz crystal equ 0 ; No, Crystal not less than 200kHz disXTAL equ 0 ; No, do not disable crystal use pllstop equ $020000 ; Yes, PLL runs during STOP enpll equ $040000 ; Yes, enable PLL operation disclk equ $080000 ; Yes, disable CORE clock output PCTL_value equ 000000 000001 000002 Storage Locations (X DATA SPACE) $000000 $000001 $000002 $000003 000001 000000 000008 000010 000020 000000 000000 000900 100000 ;- AAR3 value = 0x100939 acctype3 equ 1 aahigh3 equ 0 aap3 equ $8 aax3 equ $10 aay3 equ $20 aswap3 equ 0 enpack3 equ 0 nadd3 equ $000900 msadd3 equ $100000 100939 AAR3_value 000001 000004 000008 000010 000020 000000 000000 000A00 000A00 104000 ;- AAR2 value = 0x104A3D acctype2 equ 1 aahigh2 equ $4 aap2 equ $8 aax2 equ $10 aay2 equ $20 aswap2 equ 0 enpack2 equ 0 nadd2 equ $000A00 000A00 msadd2 equ $104000 104A3D 104A3D AAR2_value 000000 000000 000400 002000 ;- BCR value = 0x002400 aaa0ws equ 0 aaa1ws equ 0 aaa2ws equ $000400 aaa3ws equ $002000 ; External Memory access type = 0x1 ; Enable AA3 pin to be low when selected ; Yes, Enable AA3 pin on ext `P' accesses ; Yes, Enable AA3 pin on ext `X' accesses ; Yes, Enable AA3 pin on ext `Y' accesses ; No, Enable address bus swap ; No, Enable packing/unpacking logic ; Compare 9 address bits ; Most significant portion of address, ; $100000 - $107fff, to compare. ; (0001,0000,0xxx,xxxx,xxxx,xxxx) equ ; External Memory access type = 0x1 ; Enable AA2 pin to be high when selected ; Yes, Enable AA2 pin on ext `P' accesses ; Yes, Enable AA2 pin on ext `X' accesses ; Yes, Enable AA2 pin on ext `Y' accesses ; No, Enable address bus swap ; No, Enable packing/unpacking logic ; Compare 10 address bits ; Most significant portion of address, ; $104000 - $107fff, to compare. ; (0001,0000,01xx,xxxx,xxxx,xxxx) equ ; ; ; ; Address Address Address Address Attribute Attribute Attribute Attribute Area Area Area Area 0 1 2 3 w/s w/s w/s w/s = = = = 0 0 1 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Example 3-2. 32K × 24-bit `P'/'X'/`Y' Space Fast SRAM Memory Exercise Program 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 000000 000000 000000 000000 002400 defws busss enblh enbrh BCR_value P:000100 ;-org p:$100 ;Keep the program in internal RAM 0 ; Default Address Area w/s = 0 0 ; Bus state status = 0 0 ; Enable Bus Lock Hold = 0 0 ; Enable Bus Request Hold = 0 memtst ; Initialization Section P:000100 08F4BD 08F4BD movep #PCTL_value,x:PCTL; Set PLL Control Register 0E0013 0E0013 P:000102 05F43A 05F43A movec #$004000,OMR ; Disable Address Attribute Priority 004000 P:000104 05F439 05F439 movec #$080000,SR ; Enable 1K Cache 080000 P:000106 08F4BB 08F4BB movep #BCR_value,x:BCR ; Set external wait states 002400 P:000108 08F4B7 08F4B7 movep #AAR2_value,x:AAR2 ; Set Address Attribute Reg2 104A3D 104A3D P:00010A 08F4B6 08F4B6 movep #AAR3_value,x:AAR3 ; Set Address Attribute Reg3 100939 P:00010C 00010C 05F420 05F420 FFFFFF P:00010E 00010E 05F423 05F423 FFFFFF P:000110 P:000111 P:000112 P:000113 P:000114 P:000115 20001B 20001B 000000 570000 570100 570200 570300 move #-1,m0 ; Set LINEAR addressing mode move #-1,m3 clrb nop move move move move b,x:MEM_FAIL_ADDRESS b,x:MEM_FAIL_WROTE b,x:MEM_FAIL_READ b,x:MEM_PASS_COUNTER ; ; ; ; Initialize Initialize Initialize Initialize Failed Address -> $000000 Expected Data -> $000000 Data Read -> $000000 Pass Counter -> $000000 main ;-;- fill P:memory with initial pattern -;-P:000116 63F400 63F400 move #PATT,r3 ; r3 points to Test Patterns 000138 P:000118 000000 nop P:000119 000000 nop P:00011A 07DB84 07DB84 move p:(r3)+,x0 ; Get the Write Pattern for P:MEM P:00011B 00011B 70F400 70F400 008000 move #PMemSize,n0 ; Get memory size P:00011D 00011D 60F400 60F400 100000 move #PMemStart,r0 ; Get starting address for fill P:00011F 00011F 06D820 06D820 P:000120 075884 rep move n0 x0,p:(r0)+ ; Fill RAM with first pattern data P:000121 129 P:000123 130 131 132 133 134 P:000125 P:000126 135 136 137 138 139 140 equ equ equ equ equ ;-;- Check for expected pattern data in each RAM location -;- and then replace with a new data pattern. -;- .This provides an address check. Since erroneous -;- .addressing will cause the data to be written into -;- .incorrect locations and this will be evident in -;- .the next read pass. -;-063890 DOR #PATTN,test_Pm ; Start Pattern Test Loop 00000D 00000D 60F400 60F400 move #PMemStart,r0 ; Get starting address of Test Memory 100000 200041 tfr x0,a ; Save the last test pattern -> a 07DB84 07DB84 move P:(r3)+,x0 ; Get the next test pattern -> x0 ; Test this pattern through external RAM P:000127 06D810 06D810 DOR n0,next_loc ; Test all external RAM locations 000006 P:000129 07E085 07E085 move P:(r0),x1 ; Read RAM location P:00012A 200065 cmp x1,a ; Read data = last test pattern? P:00012B 00012B 052409 bne RAM P:00012D 00012D 000000 nop next_loc Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 141 142 P:00012E 00012E 000000 nop ; Time to start next test pattern 143 144 test_Pm 145 146 ; One Pass Complete 147 ; All test patterns have been tried and passed in external RAM 148 P:00012F 00012F 518300 move x:MEM_PASS_COUNTER,b0 149 P:000130 000009 inc b ; Update pass loop counter 150 P:000131 000000 nop 151 P:000132 510300 move b0,x:MEM_PASS_COUNTER 152 153 P:000133 050FC3 050FC3 bra main ; Do it all over again 154 155 ;-156 ; ERR - handles error messaging with user 157 ; 158 ; Expected Data -> a 159 ; Read Data -> x1 160 ; Address of failure -> r0 161 162 ERR 163 P:000134 600000 move r0,x:MEM_FAIL_ADDRESS ; Save off address of failure 164 P:000135 560100 move a,x:MEM_FAIL_WROTE ; Save off expected data 165 P:000136 450200 move x1,x:MEM_FAIL_READ ; Save off data read 166 167 P:000137 050C00 050C00 bra * ; Dynamically HALT here 168 169 170 ; Memory Test Patterns 171 172 P:000138 PATT dc $000000,$FFFFFF,$AAAAAA,$555555,$2BAD2C 173 P:00013D 00013D dc $800000,$400000,$200000,$100000 174 P:000141 dc $080000,$040000,$020000,$010000 175 P:000145 dc $008000,$004000,$002000,$001000 176 P:000149 dc $000800,$000400,$000200,$000100 177 P:00014D 00014D dc $000080,$000040,$000020,$000010 178 P:000151 dc $000008,$000004,$000002,$000001 179 P:000155 dc $7FFFFF,$BFFFFF,$DFFFFF,$EFFFFF 180 P:000159 dc $F7FFFF,$FBFFFF,$FDFFFF,$FEFFFF 181 P:00015D 00015D dc $FF7FFF,$FFBFFF,$FFDFFF,$FFEFFF 182 P:000161 dc $FFF7FF,$FFFBFF,$FFFDFF,$FFFEFF 183 P:000165 dc $FFFF7F,$FFFFBF,$FFFFDF,$FFFFEF 184 P:000169 dc $FFFFF7,$FFFFFB,$FFFFFD,$FFFFFE 185 P:00016D 00016D dc $FEDCBA,$123456,$012345,$EDCBA9 186 187 000038 PATTN equ *-PATT-1 188 189 end memtst 0 0 Errors Warnings Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 3.4 16K × 24-bit `P'/'X' and 16K × 24-bit `Y' Fast SRAM Example This section describes a 16K × 24-bit shared `P'/'X' and 16K × 24-bit `Y' memory space, asynchronous Fast SRAM implementation using Motorola's MCM6206D MCM6206D device. Figure 3-9 shows the memory map layout; Figure 3-1 shows the block diagram; and Example 3-3 shows the example code. The DSP core runs at 80 MHz and the input frequency source is a 4.000 MHz crystal. The asynchronous Fast SRAM requires an access time equal to or less than 12.4 nS to satisfy the DSP's one wait state external memory requirements. Program X Data Y Data Internal I/O Internal I/O External External Bootstrap ROM Reserved Reserved External External External Shared External 16K SRAM Shared External 16K SRAM External 16K SRAM $FFFFFF Reserved $FF00C0 FF00C0 $FF0000 FF0000 $FFFFC0 $FFF000 FFF000 $FF0000 FF0000 $104000 $100000 $001000 $000C00 000C00 External Internal 1K Cache Internal 3K SRAM $000000 External External Internal 2K SRAM Internal 2K SRAM $000800 $000000 Figure 3-7. 16K × 24-bit `P'/'X' and 16K × 24-bit `Y' Memory Map 3.4.1 DSP56303 DSP56303 Port A Timing Requirements and Register Settings For optimal use of the 16K × 24-bit `P'/'X' and 16K × 24-bit `Y' space memory configuration, set up the following DSP control registers. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs Set the core speed of the DSP for optimum processor and memory performance using the DSP PLL and Clock Generation register (PCTL). For this example, the DSP core runs at 80 MHz and the input frequency source is a 4.000 MHz crystal. The PCTL register value combines the following bits for each feature: · Desired Core Frequency = 80 MHz · External Frequency = 4.000 MHz · Predivider value = 1, Bits 20­23 = $0 · Low-power Divider value = 1, Bits 12­14 = $0 · VCO Multiplication value = 20, Bits 0­11 = $013 · Crystal less than 200 kHz, Bit 15 = 0 · Disable XTAL drive output, Bit 16 = 0 · PLL runs during STOP, Bit 17 = 1 · Enable PLL operation, Bit 18 = 1 · Disable core clock output, Bit 19 = 1 The value loaded into the PCTL register is $0E0013 0E0013. Address Attribute Pin 3 enables, via Fast SRAM E, external 32K SRAM bank accesses in the address range from $100000 to $103FFF 103FFF during program, X data and Y data space requests. Configure the memory address space requirements for the Address Attribute Pin 3 using Address Attribute Register 3 (AAR3). The AAR3 value combines the following bits for each feature: · Specify the external memory access type as asynchronous SRAM, bits 0­1 = $1. · Pull the AA pin high when selected, Bit 2 = 0. · Activate the AA pin during external program space accesses, Bit 3 = 1. · Activate the AA pin during external X data space accesses, Bit 4 = 1. · Activate the AA pin during external Y data space accesses, Bit 5 = 1. · Move the eight least significant bits of the address to the eight most significant bits of the external address bus, Bit 6 = 0. · Enable the internal packing/unpacking logic during external DMA accesses, Bit 7 = 0. · Specify the number of address bits to compare, Bits 8­11 = $A · Specify the most significant portion of the address to compare, Bits 12­23 = $100 The value loaded into the AAR3 is $100A39 100A39. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs Address Attribute Pin 2 selects, via Fast SRAM A14, address line A14 in the external 32K SRAM bank during accesses in the address range from $100000 to $103FFF 103FFF to differentiate program/X data space requests from Y data space requests. Configure the memory address space requirements for the Address Attribute Pin 2 using the Address Attribute Register 2 (AAR2). The AAR2 value combines the following bits for each feature: · Specify the external memory access type as asynchronous SRAM, Bits 0­1 = $1. · Pull the AA pin high when selected, Bit 2 = 1. · Activate the AA pin during external program space accesses, Bit 3 = 1. · Activate the AA pin during external X data space accesses, Bit 4 = 1. · Activate the AA pin during external Y data space accesses, Bit 5 = 0. · Move the eight least significant bits of the address to the eight most significant bits of the external address bus, Bit 6 = 0. · Enable the internal packing/unpacking logic during external DMA accesses, Bit 7 = 0. · Specify the number of address bits to compare, Bits 8­11 = $A · Specify the most significant portion of the address to compare, Bits 12­23 = $100 The value loaded into the AAR2 is $100A1D 100A1D. The value loaded into AAR0 and AAR1 is $000000. Select the proper number of wait states for the memory configuration using the Bus Control Register (BCR). The BCR value combines the following bits for each feature: · Address Attribute area 0 wait states, Bits 0­4 = $0 · Address Attribute area 1 wait states, Bits 5­9 = $0 · Address Attribute area 2 wait states, Bits 0­12]= $1 · Address Attribute area 3 wait states, Bits 13­15 = $1 · Default address area wait states, Bits 16­20 = $0 · Bus state status, Bit 21 = 0 · Enable Bus Lock Hold, Bit 22 = 0 · Enable Bus Request Hold, Bit 23 = 0 The value loaded into the BCR regiser is $002400 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 32K × 8-bit Memory Based Designs · MA­MD bits specify the DSP operating mode, Bits 0­3 = $0. · External Bus Disable bit disables the external bus controller for power conservation when external memory is not used, Bit 4 = $0. · Memory Switch Mode bit reconfigures internal memory spaces, Bit 7 = $0. · Transfer Acknowledge Synchronize Select bit selects the synchronization method for the Transfer Acknowledge (TA) pin, Bit 11 = $0. · Bus Release Timing bit selects between a fast and slow bus release of the BB pin, Bit 12 = $0. · Address Attribute Priority Disable bit allows the Address Attribute pins, AA0­AA3, to be used in any combination, Bit 14. = $1. · All other OMR bits are selected for their defaults of $000000. The value loaded into the OMR is $004000. Configure the memory mode of the DSP using the Status Register (SR). The SR value combines the following bits for each feature: · Sixteen-Bit Compatibility mode enables full compatibility to object code written for the DSP56000 DSP56000 family of DSPs, Bit 13 = $0. · Instruction Cache Enable bit enables the instruction cache controller and changes the last 1K of internal program memory into cache memory, Bit 19 = $1. · All other Status Register bits are selected for their defaults of $000000. The value loaded into the SR is $080000, which is the value loaded during reset. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Configure the operating mode and external memory controls using the Operating Mode Register (OMR). The OMR value combines the following bits for each feature: 32K × 8-bit Memory Based Designs Example 3-3. 16K `P'/'X' and 16K `Y' Space Fast SRAM Memory Exercise Program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Version 6.0.1.6 page ; ; ; ; ; ; 100000 104000 004000 000000 000001 000002 PMemStart PMemEnd PMemSize ASRAM3.ASM 97-01-25 08:05:22 asram3.asm 132,60,3,3, - Simple program to test 16Kx24-bits of Program/X-Data and 16Kx24-bits of Y-Data memory using a DSP56303 DSP56303 The program uses Internal P:RAM to test External P/X & Y:RAM from $100000 - $103FFF 103FFF @ 1w/s equ equ equ ;- Program Specific P_MEM_FAIL_ADDRESS equ P_MEM_FAIL_WROTE equ P_MEM_FAIL_READ equ $100000 $104000 PMemEnd-PMemStart Storage Locations (X DATA SPACE) $000000 $000001 $000002 000005 Y_MEM_FAIL_ADDRESS equ Y_MEM_FAIL_WROTE equ Y_MEM_FAIL_READ equ 000006 MEM_PASS_COUNTER equ FFFFFB FFFFFD FFFFF6 FFFFF7 ;- DSP56303 DSP56303 Control Registers (X I/O SPACE) BCR equ $FFFFFB ; Bus Control Register PCTL equ $FFFFFD ; PLL Control Register AAR3 equ $FFFFF6 ; Address Attribute Register #3 AAR2 equ $FFFFF7 ; Address Attribute Register #2 000000 00000 000013 000000 000000 020000 040000 080000 0E0013 0E0013 ;- PCTL value = 0x0E0013 prediv equ 0 ; Pre-Divider = 1 lowdiv equ 0 ; Low Power Divider = 1 pllmul equ 19 ; VCO Mult = 20; (19+1)*4.00MHz=80.00MHz crystal equ 0 ; No, Crystal not less than 200kHz disXTAL equ 0 ; No, do not disable crystal use pllstop equ $020000 ; Yes, PLL runs during STOP enpll equ $040000 ; Yes, enable PLL operation disclk equ $080000 ; Yes, disable CORE clock output PCTL_value equ 000003 000004 $000003 $000004 $000005 $000006 000001 000000 000008 000010 000020 000000 000000 000A00 000A00 100000 ;- AAR3 value = 0x100A39 acctype3 equ 1 aahigh3 equ 0 aap3 equ $8 aax3 equ $10 aay3 equ $20 aswap3 equ 0 enpack3 equ 0 nadd3 equ $000A00 000A00 msadd3 equ $100000 100A39 100A39 AAR3_value 000001 000004 000008 000010 000000 000000 000000 000A00 000A00 100000 ;- AAR2 value = 0x100A1D acctype2 equ 1 aahigh2 equ $4 aap2 equ $8 aax2 equ $10 aay2 equ 0 aswap2 equ 0 enpack2 equ 0 nadd2 equ $000A00 000A00 msadd2 equ $100000 ; External Memory access type = 0x1 ; Enable AA3 pin to be low when selected ; Yes, Enable AA3 pin on ext `P' accesses ; Yes, Enable AA3 pin on ext `X' accesses ; Yes, Enable AA3 pin on ext `Y' accesses ; No, Enable address bus swap ; No, Enable packing/unpacking logic ; Compare 10 address bits ; Most significant portion of address, ; $100000 - $103fff, to compare. ; (0001,0000,00xx,xxxx,xxxx,xxxx) equ ; ; ; ; ; ; ; ; ; ; ; External Memory access type = 0x1 Enable AA2 pin to be high when selected Yes, Enable AA2 pin on ext `P' accesses Yes, Enable AA2 pin on ext `X' accesses No, Enable AA2 pin on ext `Y' accesses No, Enable address bus swap No, Enable packing/unpacking logic Compare 10 address bits Most significant portion of address, $100000 - $103fff, to compare. (0001,0000,00xx,xxxx,xxxx,xxxx) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Motorola DSP56300 DSP56300 Assembler 32K × 8-bit Memory Based Designs 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 100A1D 100A1D AAR2_value 000000 000000 000400 002000 000000 000000 000000 000000 002400 ;- BCR value = 0x002400 aaa0ws equ 0 ; Address Attribute Area 0 w/s = aaa1ws equ 0 ; Address Attribute Area 1 w/s = aaa2ws equ $000400 ; Address Attribute Area 2 w/s = aaa3ws equ $002000 ; Address Attribute Area 3 w/s = defws equ 0 ; Default Address Area w/s = 0 busss equ 0 ; Bus state status = 0 enblh equ 0 ; Enable Bus Lock Hold = 0 enbrh equ 0 ; Enable Bus Request Hold = 0 BCR_value equ P:000100 ;-org p:$100 ;Keep the program in internal RAM 95 P:000102 96 P:000104 97 P:000106 98 P:000108 99 P:00010A 100 101 P:00010C 00010C 102 P:00010E 00010E 0 0 1 1 memtst P:000100 ; Initialization Section 08F4BD 08F4BD movep #PCTL_value,x:PCTL 0E0013 0E0013 05F43A 05F43A movec #$004000,OMR 004000 05F439 05F439 movec #$080000,SR 080000 08F4BB 08F4BB movep #BCR_value,x:BCR 002400 08F4B7 08F4B7 movep #AAR2_value,x:AAR2 100A1D 100A1D 08F4B6 08F4B6 movep AAR3_value,x:AAR3 100A39 100A39 05F420 05F420 FFFFFF 05F423 05F423 FFFFFF move #-1,m0 move ; Set PLL Control Register ; Disable Address Attribute Priority ; Enable 1K Cache ; Set external wait states ; Set Address Attribute Reg2 ; Set Address Attribute Reg3 ; Set LINEAR addressing mode #-1,m3 103 104 P:000110 20001B 20001B clr b 105 P:000111 000000 nop 106 P:000112 570000 move b,x:P_MEM_FAIL_ADDRESS ; Initialize P:Failed Address -> $000000 107 P:000113 570100 move b,x:P_MEM_FAIL_WROTE ; Initialize P:Expected Data -> $000000 108 P:000114 570200 move b,x:P_MEM_FAIL_READ ; Initialize P:Data Read -> $000000 109 P:000115 570300 move b,x:Y_MEM_FAIL_ADDRESS ; Initialize Y:Failed Address -> $000000 110 P:000116 570400 move b,x:Y_MEM_FAIL_WROTE ; Initialize Y:Expected Data -> $000000 111 P:000117 570500 move b,x:Y_MEM_FAIL_READ ; Initialize Y:Data Read -> $000000 112 P:000118 570600 move b,x:MEM_PASS_COUNTER ; Initialize Pass Counter -> $000000 113 114 main 115 ;-116 ;- fill P:memory with initial pattern -117 ;-118 P:000119 63F400 63F400 move #PATT,r3 ; r3 points to Test Patterns 00014A 119 P:00011B 00011B 000000 nop 120 P:00011C 00011C 000000 nop 121 122 P:00011D 00011D 07DB84 07DB84 move p:(r3)+,x0 ; Get the Write Pattern for P/X:MEM 123 P:00011E 00011E 07DB86 07DB86 move p:(r3)+,y0 ; Get the Write Pattern for Y:MEM 124 125 P:00011F 00011F 70F400 70F400 move #PMemSize,n0 ; Get memory size 004000 126 127 P:000121 60F400 60F400 move #PMemStart,r0 ; Get starting address for fill 100000 128 129 P:000123 06D820 06D820 rep n0 ; Fill P/X:RAM with first data pattern 130 P:000124 075884 move x0,p:(r0)+ 131 132 P:000125 60F400 60F400 move #PMemStart,r0 100000 133 P:000127 06D820 06D820 rep n0 ; Fill Y:RAM with first data pattern 134 P:000128 4E5800 4E5800 move y0,y:(r0)+ 135 136 ;-137 ;- Check for expected pattern data in each RAM location -138 ;- and then replace with a new data pattern. -139 ;- .This provides an address check. Since erroneous -140 ;- .addressing will cause the data to be written into -141 ;- .incorrect locations and this will be evident in - Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 equ 32K × 8-bit Memory Based Designs P:000129 145 P:00012B 00012B 146 147 148 149 150 151 152 P:00012D 00012D P:00012E 00012E P:00012F 00012F P:000130 P:000131 063890 000013 60F400 60F400 100000 200041 200059 07DB84 07DB84 07DB86 07DB86 06D810 06D810 00000A 07E085 07E085 200065 05240D 05240D 076084 ;- .the next read pass. -;-DOR #PATTN,test_Pm ; Start Pattern Test Loop move #PMemStart,r0 ; Get starting address of Test Memory tfr tfr move move x0,a y0,b P:(r3)+,x0 P:(r3)+,y0 ; ; ; ; Save the last P/X test pattern -> a Save the last Y test pattern -> b Get the next P/X test pattern -> x0 Get the next Y test pattern -> y0 ; Test this pattern through external RAM DOR n0,next_loc ; Test all external RAM locations 153 P:000133 move P:(r0),x1 ; Read P/X:RAM location 154 P:000134 cmp x1,a ; Read data = last test pattern? 155 P:000135 bne P/X:RAM 157 158 P:000137 4FE000 4FE000 move Y:(r0),y1 ; Read Y:RAM location 159 P:000138 20007D 20007D cmp y1,b ; Read data = last test pattern? 160 P:000139 05240D 05240D bne Y:RAM 162 P:00013B 00013B 000000 nop 163 next_loc 164 165 P:00013C 00013C 000000 nop ; Time to start next test pattern 166 167 test_Pm 168 169 ; One Pass Complete 170 ; All test patterns have been tried and passed in external RAM 171 P:00013D 00013D 518600 move x:MEM_PASS_COUNTER,b0 172 P:00013E 00013E 000009 inc b ; Update pass loop counter 173 P:00013F 00013F 000000 nop 174 P:000140 510600 move b0,x:MEM_PASS_COUNTER 175 176 P:000141 050F98 050F98 bra main ; Do it all over again 177 178 ;-179 ; PERR - handles P/X:RAM error messaging with user 180 ; 181 ; Expected Data -> a 182 ; Read Data -> x1 183 ; Address of failure -> r0 184 185 PERR 186 P:000142 600000 move r0,x:P_MEM_FAIL_ADDRESS ; Save off address of failure 187 P:000143 560100 move a,x:P_MEM_FAIL_WROTE ; Save off expected data 188 P:000144 450200 move x1,x:P_MEM_FAIL_READ ; Save off data read 189 190 P:000145 050C00 050C00 bra * ; Dynamically HALT here 191 192 ;-193 ; YERR - handles Y:RAM error messaging with user 194 ; 195 ; Expected Data -> b 196 ; Read Data -> y1 197 ; Address of failure -> r0 198 199 YERR 200 P:000146 600300 move r0,x:Y_MEM_FAIL_ADDRESS ; Save off address of failure 201 P:000147 570400 move b,x:Y_MEM_FAIL_WROTE ; Save off expected data 202 P:000148 470500 move y1,x:Y_MEM_FAIL_READ ; Save off data read 203 204 P:000149 050C00 050C00 bra * ; Dynamically HALT here 205 206 207 208 ; Memory Test Patterns 209 210 P:00014A PATT dc $000000,$FFFFFF,$AAAAAA,$555555,$2BAD2C 211 P:00014F 00014F dc $800000,$400000,$200000,$100000 212 P:000153 dc $080000,$040000,$020000,$010000 213 P:000157 dc $008000,$004000,$002000,$001000 214 P:00015B 00015B dc $000800,$000400,$000200,$000100 215 P:00015F 00015F dc $000080,$000040,$000020,$000010 216 P:000163 dc $000008,$000004,$000002,$000001 217 P:000167 dc $7FFFFF,$BFFFFF,$DFFFFF,$EFFFFF Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 142 143 144 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 0 0 P:00016B 00016B P:00016F 00016F P:000173 P:000177 P:00017B 00017B P:00017F 00017F dc dc dc dc dc dc $F7FFFF,$FBFFFF,$FDFFFF,$FEFFFF $FF7FFF,$FFBFFF,$FFDFFF,$FFEFFF $FFF7FF,$FFFBFF,$FFFDFF,$FFFEFF $FFFF7F,$FFFFBF,$FFFFDF,$FFFFEF $FFFFF7,$FFFFFB,$FFFFFD,$FFFFFE $FEDCBA,$123456,$012345,$EDCBA9 P:000183 P:000188 P:00018C 00018C P:000190 P:000194 P:000198 P:00019C 00019C P:0001A0 0001A0 P:0001A4 0001A4 P:0001A8 0001A8 P:0001AC 0001AC P:0001B0 0001B0 P:0001B4 0001B4 P:0001B8 0001B8 dc dc dc dc dc dc dc dc dc dc dc dc dc dc $000000,$FFFFFF,$AAAAAA,$555555,$2BAD2C $800000,$400000,$200000,$100000 $080000,$040000,$020000,$010000 $008000,$004000,$002000,$001000 $000800,$000400,$000200,$000100 $000080,$000040,$000020,$000010 $000008,$000004,$000002,$000001 $7FFFFF,$BFFFFF,$DFFFFF,$EFFFFF $F7FFFF,$FBFFFF,$FDFFFF,$FEFFFF $FF7FFF,$FFBFFF,$FFDFFF,$FFEFFF $FFF7FF,$FFFBFF,$FFFDFF,$FFFEFF $FFFF7F,$FFFFBF,$FFFFDF,$FFFFEF $FFFFF7,$FFFFFB,$FFFFFD,$FFFFFE $FEDCBA,$123456,$012345,$EDCBA9 equ (*-PATT)/2)-1 end memtst 000038 Errors Warnings PATTN Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 32K × 8-bit Memory Based Designs 128K × 8-bit Memory Based Designs 128K × 8-bit Memory Based Designs This section describes how to implement several different DSP memory space Fast SRAM designs using three 128K × 8-bit 3.3 V memories with a Motorola DSP56303 DSP56303 device. Using one hardware memory design based on three 128K × 8-bit 3.3 V memories, the DSP56303 DSP56303's Memory Expansion Port allows the 128K × 24-bit memory bank to be logically configured for use in various memory space arrangements. The configuration is accomplished by programmatically changing the Memory Expansion Port's Address Attribute Control Registers. Configuring and using one Memory Expansion Port Address Attribute Control Register, the 128K memory bank can accommodate seven different memory space arrangements. 1. 128K × 24-bit `P' Space Fast SRAM 2. 128K × 24-bit `X' Space Fast SRAM 3. 128K × 24-bit `Y' Space Fast SRAM 4. 128K × 24-bit `P'/'X' Space Fast SRAM 5. 128K × 24-bit `P'/'Y' Space Fast SRAM 6. 128K × 24-bit `X'/'Y' Space Fast SRAM 7. 128K × 24-bit `P'/'X'/'Y' Space Fast SRAM Configuring and using two Memory Expansion Port Address Attribute Control Registers, the 128K memory bank can accommodate thirteen different memory space arrangements. 1. 128K × 24-bit `P' Space Fast SRAM 2. 128K × 24-bit `X' Space Fast SRAM 3. 128K × 24-bit `Y' Space Fast SRAM 4. 128K × 24-bit `P'/'X' Space Fast SRAM 5. 128K × 24-bit `P'/'Y' Space Fast SRAM 6. 128K × 24-bit `X'/'Y' Space Fast SRAM 7. 128K × 24-bit `P'/'X'/'Y' Space Fast SRAM 8. 64K × 24-bit `P'/'X' and 64K x 24-bit `Y' Space Fast SRAM 9. 64K × 24-bit `P'/'Y' and 64K × 24-bit `X' Space Fast SRAM 10. 64K × 24-bit `P' and 64K × 24-bit `X'/'Y' Space Fast SRAM 11. 64K × 24-bit `P' and 64K × 24-bit `X' Space Fast SRAM 12. 64K × 24-bit `P' and 64K × 24-bit `Y' Space Fast SRAM 13. 64K × 24-bit `X' and 64K × 24-bit `Y' Space Fast SRAM All of these memory space configurations efficiently use the full capacity of the memory chips in the 128K × 24-bit memory bank. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 4 The memory configuration examples in the remainder of this chapter are based on one common hardware design that uses two Address Attribute Selectors and implements two of the most common configurations: 128K × 24-bit `P'/'X'/`Y' Space Fast SRAM configuration and a 64K × 24-bit 'X' and 64K × 24-bit `Y' Space Fast SRAM configuration (see Figure 4-4 for a schematic of the hardware design). 4.1 128K × 24-bit Common Fast SRAM Hardware Design This section describes an asynchronous Fast SRAM 128K × 24-bit memory bank implementation using Motorola's MCM6926 MCM6926 device (see Figure 4-1). Memory bank designs of this size and type allow for future application expandability in both size and speed. The 3.3 V devices also require less hardware, providing a glueless memory interface with the DSP. The memory bank design is implemented using two Address Attribute Selectors. However, for the 128K × 24-bit `P'/'X'/'Y' Space Fast SRAM configuration a one Address Attribute Selector design can be used-A16 substituted for AA2. The two Address Attribute Selector design demonstrates the ultimate flexibility of the Address Attribute Selectors. For this common hardware design, the DSP core runs at a maximum of 80 MHz, and the input frequency source is a 4.000 MHz crystal. The asynchronous Fast SRAM requires an access time equal to or less than 12.4 nS to satisfy the DSP's one-wait state external memory requirements. This 3.3 V device is organized as 128K × 8-bits. Therefore, three memory devices are used to achieve the 24-bit wide bus. D0­D7 D8­D15 D16­D23 Data DSP56303 DSP56303 Data Data MCM6926 MCM6926 MCM6926 MCM6926 MCM6926 MCM6926 Addr E Addr E Addr E A0­A15, AA2 AA3 Figure 4-1 128K × 24-bit Fast SRAM Memory Example 4.1.1 MCM6926-12 MCM6926-12 Memory Timing Requirements For the asynchronous Fast SRAM device to work properly, its timing requirements must be met. The sections that follow give the timing requirements for the MCM6926-12 MCM6926-12 128K × 8-bit 12 nS Fast SRAM. 4.1.1.1 Read Cycle Timing Table 4-1 shows the memory read timing values used in the memory read cycle timing diagram, Figure 4-2. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 128K × 8-bit Memory Based Designs 128K × 8-bit Memory Based Designs Read Cycle Parameter Symbol Min Max Read Cycle Time tAVAV 12 nS - Address Access Time tAVQV - 12 nS Enable Access Time tELQV - 12 nS Output Enable Access Time tGLQV - 6 nS Enable High to Output High-Z tEHQZ 0 nS 6 nS Output Enable High to Output High-Z tGHQZ 0 nS 6 nS tAVAV A0­A16 tELQV E (Chip Enable) tEHQZ G (Output Enable) tGHQZ tGLQV D0­D7 Valid Data (Data Out) tAVQV Figure 4-2. MCM6926 MCM6926 Memory Read Cycle Timing Diagram 4.1.1.2 Write Cycle Timing Table 4-2 shows the memory write timing values used in the memory write cycle timing diagram, Figure 4-3. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: DSP56301 DSP56301, DSP56303 DSP56303 Table 4-1. MCM6926-12 MCM6926-12 Memory Read Timing Specifications 128K × 8-bit Memory