DSP56005/D DSP56005 DSP56002 DSP56000 DSP56KFAMUM/AD DSP56005UM/AD BR1105/D - Datasheet Archive

 

by DSP56005/D Rev. 1 MOTOROLA SEMICONDUCTOR TECHNICAL DATA DSP56005 Advance Information 24-bit Digital Signal Processor The

 

Order this document by DSP56005/D DSP56005/D Rev. 1 MOTOROLA SEMICONDUCTOR TECHNICAL DATA DSP56005 DSP56005 Advance Information 24-bit Digital Signal Processor The DSP56005 DSP56005 is an MPU-style general purpose Digital Signal Processor (DSP), composed of an efficient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry. The 56000-Family-compatible DSP core is fed by a large program RAM, two independent data RAMs, and two data ROMs with sine and arc-tangent tables. Like the DSP56002 DSP56002, the DSP56005 DSP56005 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI), parallel Host Interface (HI), a 24-bit timer/event counter, and On-Chip Emulation (OnCETM) port. Features of the DSP56005 DSP56005 include the large on-chip program memory, five Pulse Width Modulators (PWM), a watchdog timer, and an address decode pin for external peripherals. This combination of features, illustrated in Figure 1, makes the DSP56005 DSP56005 a cost-effective, high-performance solution for many DSP and control applications, especially in high-performance motor control, optical disk drives and audio processing. 14 1 6 3 Watch- Pulse 24-bit Sync. Serial Host dog Width Timer / Serial Comm. Interface Timer Modul. Event (SSI) (SCI) (HI) (5) Counter or I/O or I/O or I/O 24-bit 56000 DSP Core X Data Memory 256 × 24 RAM 256 × 24 ROM Y Data Memory 256 × 24 RAM 256 × 24 ROM (boot) (sine) (arc-tangent) Interrupt Control Clock Program Decode Controller External Address Bus Switch GDB PDB XDB YDB OnCE Port External Data Bus Switch Program Address Generator Program Control Unit Gen. 5 Program Memory 4608 × 24 RAM 96 × 24 ROM PAB XAB YAB Address Generation Unit Internal Data Bus Switch PLL 16-bit Bus 24-bit Bus 15 4 Data ALU 24 × 24 + 56 56-bit MAC Two 56-bit Accumulators 5 IRQ Figure 1 DSP56005 DSP56005 Block Diagram This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. © MOTOROLA INC., 1995 Bus Control Address 16 Data 24 Control 6 Introduction DSP56005 DSP56005 Features DSP56005 DSP56005 Features Digital Signal Processing Core · Efficient, object code compatible, 24-bit 56000-Family DSP engine - - - - - - - - - - - - - Up to 25 Million Instructions per Second (MIPS) ­ 40 ns instruction cycle at 50 MHz Up to 150 Million Operations per Second (MOPS) at 50 MHz Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit Addition/subtraction in 1 instruction cycle Fractional arithmetic with support for multiprecision arithmetic Hardware support for block-floating point FFT Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories Memory · On-chip Harvard architecture permitting simultaneous accesses to program and two data memories · 4608 × 24-bit on-chip program RAM and 96 × 24-bit bootstrap ROM · Two 256 × 24-bit on-chip data RAMs · Two 256 × 24-bit on-chip data ROMs containing sine and arc-tangent tables · External memory expansion with 16-bit address and 24-bit data buses · Bootstrap loading from external data bus, Host Interface, or Serial Communications Interface Peripheral and Support Circuits · Byte-wide Host Interface (HI) with Direct Memory Access (DMA) support · Synchronous Serial Interface (SSI) to communicate with codecs and synchronous serial devices · Serial Communication Interface (SCI) for full-duplex asynchronous communications · Five Pulse Width Modulators (PWM) - Three with alternate outputs; two with open drain or TTL outputs - 9- to 16-bit data width - Alternate outputs independently selectable as active-high or active-low · 24-bit timer/event counter also generates and measures digital waveforms · 16-bit Watchdog timer 2 DSP56005 DSP56005 Data Sheet MOTOROLA Introduction DSP56005 DSP56005 Features Product Documentation · On-chip peripheral registers memory mapped in data memory space · Double buffered peripherals · Up to 25 general purpose I/O pins · Five external interrupt request pins · On-Chip Emulation (OnCE) port for unobtrusive, processor speed-independent debugging · Software-programmable, Phase-Locked Loop (PLL) based frequency synthesizer for the core clock · External peripheral address decode signal Miscellaneous Features · Power-saving Wait and Stop modes · Fully static, HCMOS design for operating frequencies from 50 MHz down to DC · 144-pin Thin Quad Flat Pack (TQFP) surface-mount package; 20 × 20 × 1.4 mm · 5 V Power supply Product Documentation More detailed documentation is available describing the DSP56005 DSP56005. The three documents listed in Table 1 are required for a complete description of the DSP56005 DSP56005 and are necessary to properly design with the part. Documentation is available from a local Motorola distributor or semiconductor sales office, or through a Motorola Literature Distribution Center. Table 1 Additional DSP56005 DSP56005 Documentation Document Name Description Order Number DSP56000 DSP56000 Family Manual Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set DSP56KFAMUM/AD DSP56KFAMUM/AD DSP56005 DSP56005 User's Manual Detailed description of memory, peripherals, and interfaces DSP56005UM/AD DSP56005UM/AD DSP56005 DSP56005 Data Sheet Electrical and timing specifications, and pin and package descriptions DSP56005/D DSP56005/D MOTOROLA DSP56005 DSP56005 Data Sheet 3 Introduction Product Documentation Related Documentation Table 2 lists additional documentation relevant to the DSP56005 DSP56005. Table 2 DSP56005 DSP56005 Related Documentation Document Name Description Order Number Motorola's 16-, 24-, and 32-bit Digital Signal Processing Families BR1105/D BR1105/D Digital Sine-Wave Synthesis Application Report. Uses the DSP56001 DSP56001 look-up table. APR1/D Digital Stereo 10-band Graphic Equalizer Application Report. Includes code and circuitry; features the DSP56001 DSP56001. APR2/D Fractional and Integer Arithmetic Application Report. Includes code. APR3/D Implementation of Fast Fourier Transforms Application Report. Comprehensive FFT algorithms and code for DSP56001 DSP56001, DSP56156 DSP56156, and DSP96002 DSP96002. APR4/D Implementation of PID Controllers Application Report. PWM using the SCI timer and three phase output using modulo addressing. APR5/D Convolutional Encoding and Viterbi Decoding with a V.32 Modem Trellis Example Application Report. Theory and code; features the DSP56001 DSP56001. APR6/D Implementing IIR/FIR Filters Application Report. Comprehensive example using the DSP56001 DSP56001. APR7/D Principles of Sigma-Delta Modulation for A-to-D Converters Application Report. Features the DSP56ADC16 DSP56ADC16; improving resolution with half-band filters APR8/D Full-Duplex 32-kbit/s CCITT ADPCM Speech Coding Application Report. Features the DSP56001 DSP56001 APR9/D DSP56001 DSP56001 Interface Techniques and Examples Application Report. Interfaces for pseudo static RAM, dynamic RAM, ISA bus, Host APR11/D APR11/D Twin CODEC Expansion Board for the DSP56000 DSP56000 ADS Application Report. Circuit, code, FIR filter design for two voice band CODECs connecting to the SSI APR12/D APR12/D Conference Bridging in the Digital Telecommunications Environment Application Report. Theory and code; features the DSP56001/002 DSP56001/002 APR14/D APR14/D Implementation of Adaptive Controllers 4 Overview of all of the DSP product families. Application Report. Adaptive control using reference models; generalized predictive control; includes code APR15/D APR15/D DSP56005 DSP56005 Data Sheet MOTOROLA Introduction Product Documentation Table 2 DSP56005 DSP56005 Related Documentation (Continued) Document Name Description Order Number Calculating Timing Requirements of External SRAM Application Report. Determination of SRAM speed for optimum performance APR16/D APR16/D PC Media Hardware Reference Design Version 4.0 Application Report. Audio, telephony, and entertainment board design APR19/D APR19/D Low Cost Controller for DSP56001 DSP56001 Application Report. Circuit and code to connect two DSP56001s to an MC68008 MC68008 APR402/D APR402/D G.722 Audio Processing Application Report. Theory and code using SB-ADPCM APR404/D APR404/D Minimal Logic DRAM Interface Application Report. 1M x 480 ns DRAM, 1 PAL, code APR405/D APR405/D Logarithmic/Linear Conversion Routines Application Report. µ-law and A-law companding routines for PCM mono-circuits ANE408/D ANE408/D Dr. BuB Bulletin Board Flyer. Motorola's electronic bulletin board where free DSP software is available BR297/D BR297/D DSP Development Tools Overview of Motorola's hardware and software development tools DSPTOOLSP/D Third Party Compendium Brochures from companies selling hardware and software that supports Motorola DSPs DSP3RDPTYPAK/D University Support Program Flyer. Motorola's program supporting Universities in DSP research and education BR382/D BR382/D Technical Training Schedule Technical Training Schedule BR348/D BR348/D Real Time Signal Processing Applications with Motorola's DSP56000 DSP56000 Family Textbook by Mohamed El-Sharkawy; 398+ pages. (This is a charge item.) Prentice-Hall, 1990; ISBN 0-13-767138-5 MOTOROLA DSP56005 DSP56005 Data Sheet 5 Introduction Contents Conventions Data Sheet Contents This data sheet contains: · · · · · Pin Descriptions . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . Pin-out and Package. . . . . . . . . . . . . . . . Design Considerations . . . . . . . . . . . . . . Ordering Information. . . . . . . . . . . . . . . 9 21 Left 77 87 Data Sheet Conventions This data sheet uses the following conventions: · OVERBARS are used to indicate a signal that is active when pulled to ground (see Table 3) e.g. the HREQ pin is active when pulled to ground. Therefore, references to the HREQ pin will always have an overbar. · The word "assert" (see Table 3) means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. · The word "deassert" (see Table 3) means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC. Table 3 High True / Low True Signal Conventions Signal/Symbol Logic State Signal State Voltage Ground PIN True Asserted PIN False Deasserted VCC PIN True Asserted VCC PIN False Deasserted Ground NOTES: 1. 2. Ground is an acceptable low voltage level. See the DC electrical specifications for the range of acceptable low voltage levels (typically a TTL logic low). 3. 6 PIN is a generic term for any pin on the chip. VCC is an acceptable high voltage level. See the DC electrical specifications for the range of acceptable high voltage levels (typically a TTL logic high). DSP56005 DSP56005 Data Sheet MOTOROLA Introduction Pin Groupings Pin Groupings The input and output signals of the DSP56005 DSP56005 are organized into function groups as shown in Table 4 and as illustrated in Figure 2. MOTOROLA DSP56005 DSP56005 Data Sheet 7 Introduction Pin Functions DSP56005 DSP56005 D0-D23 D0-D23 VCCD GNDD A0-A15 A0-A15 PS DS X/Y EXTP VCCA GNDA External Data Bus Host Interface (HI) External Address Bus Serial Communication Interface (SCI) RD WR VCCC GNDC H0-H7 HA0-HA2 HR/W HEN HREQ HACK VCCH GNDH RXD TXD SCLK VCCS GNDS External Bus Control Synchronous Serial Interface (SSI) SC0-SC2 SCK SRD STD Timer/ Event Counter Pulse Width Modulator A (PWMA0-2) PWB0, PWB1 PWBC PWBCLK VCCW GNDW Interrupt/ Mode Control DSI/OS0 DSCK/OS1 DSO DR PWAP0 - PWAP2 PWAN0 - PWAN2 PWAC0 - PWAC2 PWACLK Pulse Width Modulator B (PWMB0-1) MODA/IRQA MODB/IRQB MODC/NMI IRQC IRQD RESET VCCQ GNDQ TIO On-Chip Emulator (OnCE) Port EXTAL XTAL VCCCK GNDCK Phase-Locked Loop (PLL) Clock Oscillator PCAP PINIT CKOUT VCCP GNDP Figure 2 DSP56005 DSP56005 Pin Functions 8 DSP56005 DSP56005 Data Sheet MOTOROLA Pin Descriptions Address and Data Bus Bus Control Pin Descriptions Bus Control The DSP56005 DSP56005 is available in a 144 TQFP. The pins are organized into the functional groups indicated in Table 4. The signals are discussed in the paragraphs that follow. The bus control signals are three-stated during reset and may require pull-up resistors to prevent erroneous operation. All unused inputs should have pull-up resistors for two reasons: 1. floating inputs draw excessive power 2. floating input can cause erroneous operation For example, during reset, all signals are three-stated. A pull-up resistor in the 50 k range should be sufficient. Also, for future enhancements, all reserved "no connect" (NC), pins should be left unconnected. Address and Data Bus The Port A address and data bus signals control the access to external memory. These signals are three-stated during reset unless noted otherwise, and may require pull-up resistors to minimize power consumption and to prevent erroneous operation. A0­A15 (Address Bus) - three-state, outputs. A0-A15 A0-A15 specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 A0-A15 remain at their previous values. A0-A15 A0-A15 are three-stated during hardware reset. D0­D23 (Data Bus) - three-state, bidirectional input/outputs. Data for external memory I/O is presented on D0-D23 D0-D23. If there is no external bus activity, D0-D23 D0-D23 are three-stated. D0-D23 D0-D23 are also three-stated during hardware reset. MOTOROLA PS (Program Memory Select) - three-state, active low output This output is asserted only when external program memory is referenced (see Table 5). PS timing is the same as the A0-A15 A0-A15 address lines. If the external bus is not used during an instruction cycle, PS is driven high. PS is three-stated during hardware reset. DS (Data Memory Select) - three-state, active low output This three-state output is asserted only when external data memory is referenced (see Table 5). If the external bus is not used during an instruction cycle, DS is driven high. DS is three-stated during hardware reset. X/Y (X/Y Select) - three-state output. This three-state output selects which external data memory space (X or Y) is referenced by DS (see Table 5). X/Y is three-stated during hardware reset. RD (Read Enable) - three-state, active low output. This output is asserted during external memory read cycles. When RD is asserted, the data bus pins D0-D23 D0-D23 become inputs, and an external device is enabled onto the data bus. When RD is deasserted, the external data is latched inside the DSP. When RD is asserted, it qualifies the A0-A15 A0-A15, PS and DS pins. RD can be connected directly to the OE pin of a static RAM or ROM. RD is three-stated during hardware reset. DSP56005 DSP56005 Data Sheet 9 Pin Descriptions Bus Control HI WR (Write Enable) - three-state, active low output. This output is asserted during external memory write cycles. When WR is asserted, the data bus pins D0-D23 D0-D23 become outputs, and the DSP puts data on the bus. When WR is deasserted, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15 A0-A15, PS and DS pins. WR can be connected directly to the WE pin of a static RAM. WR is three-stated during hardware reset. EXTP (External Peripheral) - active low output. The EXTP pin is an output asserted whenever the external Y memory I/O space (Y:$FFC0-$FFFF) is accessed. This signal simplifies generating peripheral enable signals. No additional circuitry is needed if only one external peripheral is used. For most applications, no more than one decode chip is needed and, as a result, decode delays are minimized. Using the Y memory I/O space allows the MOVEP instruction to be used to send and to receive data. Using the MOVEP instruction may allow the entire I/O routine to fit in a fast interrupt. EXTP is three-stated during hardware reset. Host Interface The following paragraphs discuss the host interface signals, which provide a convenient connection to another processor. H0­H7 (Host Data Bus) - bidirectional. This bidirectional data bus is used to transfer data between the host processor and the DSP. This bus is an input unless enabled by a host processor read. It is high impedance when HEN is deasserted. H0-H7 may be programmed as Port B general purpose parallel I/O pins called PB0-PB7 when the Host Interface (HI) is not being used. These pins are configured as GPIO input pins during hardware reset. HA0­HA2 (Host Address) - input.* These inputs provide the address selection for each HI register and must be stable when HEN is asserted. HA0-HA2 may be programmed as Port B general purpose parallel I/O pins called PB8-PB10 PB8-PB10 when the HI is not being used. These pins are configured as GPIO input pins during hardware reset. *Note that these pins can be inputs or outputs when programmed as general purpose I/O. Table 5 Program and Data Memory Select Encoding External Memory Reference PS X/Y 1 1 1 No Activity 1 0 1 X Data Memory on Data Bus 1 0 0 Y Data Memory on Data Bus 0 1 1 Program Memory on Data Bus (Not an Exception) 0 1 0 External Exception Fetch: Vector or Vector +1 (Development Mode Only) 0 0 X Reserved 1 10 DS 1 0 Reserved DSP56005 DSP56005 Data Sheet MOTOROLA Pin Descriptions HI SCI HR/W (Host Read/Write) - input.* This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs, and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP when HEN is deasserted. When HEN is asserted, HR/W must be stable. HR/W may be programmed as a general purpose I/O pin called PB11 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. HEN (Host Enable) - active low input.* This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0-H7 becomes an output and DSP data may be latched by the host processor. When HEN is asserted and HR/W is low, H0-H7 is an input and host data is latched inside the DSP when HEN is deasserted. Normally a chip select signal derived from host address decoding and an enable clock is connected to the Host Enable. HEN may be programmed as a general purpose I/O pin called PB12 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. HREQ (Host Request) - active low output.* This open-drain output signal is used by the DSP to request service from the host processor. HREQ may be connected to a host processor interrupt request pin, a DMA controller transfer request pin, or a control input to external circuitry. HREQ is asserted when an enabled request occurs in the HI. HREQ is *Note that these pins can be inputs or outputs when programmed as general-purpose I/O. MOTOROLA deasserted when the enabled request is cleared or masked, DMA HACK is asserted, or the DSP is reset. HREQ may be programmed as a general purpose I/O pin (not open-drain) called PB13 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. HACK (Host Acknowledge) - active low input.* This input has two functions: · to provide a host acknowledge signal for DMA transfers · to control handshaking and to provide a host interrupt acknowledge compatible with MC68000 MC68000 family processors If programmed as a host acknowledge signal, HACK may be used as a data strobe for HI DMA data transfers. If programmed as an MC68000 MC68000 host interrupt acknowledge, HACK enables the HI Interrupt Vector Register (IVR) onto the host data bus H0-H7 if the Host Request HREQ output is asserted. In this case, all other HI control pins are ignored and the HI state is not affected. HACK may be programmed as a general purpose I/O pin called PB14 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. NOTE: HACK should always be pulled high when not in use. Serial Communication Interface (SCI) RXD (Receive Data) - input.* This input receives byte-oriented data and transfers the data to the SCI receive shift register. Input data is sampled on the DSP56005 DSP56005 Data Sheet 11 Pin Descriptions SCI SSI positive or the negative edge of the receive clock, depending on how the SCI control register is programmed. RXD may be programmed as a general-purpose I/O pin called PC0 when it is not being used as an SCI pin. This pin is configured as a GPIO input pin during hardware reset. TXD (Transmit Data) - output.* This output transmits serial data from the SCI transmit shift register. Data changes on the negative edge of the transmit clock. This output is stable on the positive or the negative edge of the transmit clock, depending on how the SCI control register is programmed. TXD may be programmed as a general-purpose I/O pin called PC1 when the SCI TXD function is not being used. This pin is configured as a GPIO input pin during hardware reset. SCLK (SCI Serial Clock) - bidirectional. This bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode, and from which data is transferred in the synchronous mode. SCLK may be programmed as a general-purpose I/O pin called PC2 when the SCI SCLK function is not being used. This pin is configured as a GPIO input pin during hardware reset. Synchronous Serial Interface (SSI) SC0 (Serial Control 0) - bidirectional. This bidirectional pin's function is de*These pins can be input or output when programmed as general-purpose I/O. 12 DSP56005 DSP56005 Data Sheet termined by whether the SSI is in synchronous or asynchronous mode. In synchronous mode, this pin is used for serial flag I/O. In asynchronous mode, this pin receives clock I/O. SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. SC0 may be programmed as a general-purpose I/O pin called PC3 when the SSI SC0 function is not used. This pin is configured as a GPIO input pin during hardware reset. SC1 (Serial Control 1) - bidirectional. The SSI uses this bidirectional pin to control flag or frame synchronization. This pin's function is determined by whether the SSI is in synchronous or asynchronous mode. In asynchronous mode, this pin is frame sync I/O. For synchronous mode with continuous clock, this pin is serial flag SC1 and operates like the SC0. SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. SC1 may be programmed as a general-purpose I/O pin called PC4 when the SSI SC1 function is not being used. This pin is configured as a GPIO input pin during hardware reset. SC2 (Serial Control 2) - bidirectional. The SSI uses this bidirectional pin to control frame synchronization only. As with SC0 and SC1, its function is defined by the SSI operating mode. SC2 may be programmed as a general-purpose I/O pin called PC5 when the SSI SC2 function is not being used. This pin is configured as a GPIO input pin during hardware reset. SCK (SSI Serial Clock) - bidirectional. This bidirectional pin provides the serial bit rate clock for the SSI when only one clock is being used. SCK may be MOTOROLA Pin Descriptions SSI TIMER PWMA programmed as a general-purpose I/O pin called PC6 when it is not needed as an SSI pin. This pin is configured as a GPIO input pin during hardware reset. SRD (SSI Receive Data) - input.* This input pin receives serial data into the SSI receive shift register. SRD may be programmed as a general-purpose I/O pin called PC7 when the SRD function is not being used. This pin is configured as a GPIO input pin during hardware reset. STD (SSI Transmit Data) - output.* This output pin transmits serial data from the SSI transmit shift register. STD may be programmed as a general-purpose I/O pin called PC8 when the STD function is not being used. This pin is configured as a GPIO input pin during hardware reset. Timer/Event Counter TIO (Timer/Event Counter Input/Output) - bidirectional. The TIO pin provides an interface to the Timer/Event Counter module. When the module functions as an external event counter or is used to measure an external pulse width/signal period, the TIO is used as an input. When the module functions as a timer, the TIO is an output and the signal on the TIO pin is the timer pulse. When not used by the timer module, the TIO can act as a general purpose I/O pin. Reset disables the TIO pin and causes it to be three-stated. Pulse Width Modulator A (PWMA) Pulse Width Modulator A is a set of three 16-bit signed two's complement fractional data pulse width modulators and has 10 dedicated external pins. These pulse width modulators are independent of the PWMB modulators. PWAP0 - PWAP2 (Pulse Width Modulator A Positive) - output. These three pins are the positive outputs for the three PWMA modulators (PWMA0, PWMA1, and PWMA2). When a positive two's complement number is loaded in one of the three PWMA Count Registers, an output signal will be generated on the respective pin (e.g., loading PWACR0 with a positive two's complement number will generate an output on PWAP0). When a negative two's complement number is loaded in a PWMA Count Register, PWAP0-PWAP2 will be at its inactive logic level (as defined by the polarity bits in the PWMA Control/Status Register 1). These pins are driven at their inactive logic level (as defined by the polarity bits in the Control/Status Register 1) when the individual PWM modulator (PWMA0, PWMA1, or PWMA2) is not enabled. During hardware reset, these pins are driven to a high logic level. PWAN0 - PWAN2 (Pulse Width Modulator A Negative) - output. These three pins are the negative outputs for the three PWMA modulators (PWMA0, PWMA1, and PWMA2). When a negative two's complement number is loaded in one of the three PWMA Count Registers, an output signal will be generated on the respective pin (e.g. loading PWACR0 with a negative two's * These pins can be input or output when programmed as general purpose I/O. MOTOROLA DSP56005 DSP56005 Data Sheet 13 Pin Descriptions PWMA PWMB complement number will generate an output on PWAN0). When a positive two's complement number is loaded in a PWMA Count Register, the N-output (PWAN0PWAN2) of this PWMA block will be at its inactive logic level (as defined by the polarity bits in the PWMA Control/Status Register 1). These pins are driven at their inactive logic level (as defined by the polarity bits in the Control/Status Register 1) when the individual PWM modulator (PWMA0, PWMA1, or PWMA2) is not enabled. During hardware reset, these pins are driven to a high logic level. PWAC0 - PWAC2 (Pulse Width Modulator A Carrier) - input. These three pins are inputs that provide the external carrier signals for the three PWMAs (PWMA0, PWMA1 and PWMA2). When the carrier source for the respective PWMA block is programmed to be external, the modulator starts operation at each rising edge of its carrier signal. While a PWMA block is either disabled, or is enabled and programmed to operate with the internal carrier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. PWACLK (Pulse Width Modulator A Clock) - input. This input increments the prescaler which connects to the three PWMA blocks and increments the counter in each these blocks. If all of the PWMA blocks are either disabled, or are programmed to use the internal clock, the internal input buffer is disconnected from the pin and no external pull-up is necessary. 14 Pulse Width Modulator B (PWMB) Pulse Width Modulator B is a pair 16-bit positive fractional data pulse width modulators and has four dedicated external pins. These two pulse width modulators are independent of the PWMA modulators. PWBC (Pulse Width Modulator B Carrier) - input. This pin is an input that provides the external carrier signals for the two PWMB blocks (PWMB0 and PWMB1). When the carrier source for these blocks is programmed to be external, these blocks start operation at each rising edge of this signal. While a PWMB block is either disabled, or is enabled and programmed to operate with the internal carrier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. PWB0-PWB1(Pulse Width Modulator B Output) - active low output. These two pins are the outputs for pulse width modulators PWMB0 and PWMB1. These pins are either open drain or driven at TTL levels depending on the programming of PWBCSR1 bit 14 (WBR0). These pins are also in the high-impedance state or in a high logic state (depending on the value of the bit WBO in PWBCSR1) when PWMB0 and PWMB1 are disabled. During hardware reset, these pins are in the high-impedance state. PWBCLK (Pulse Width Modulator B Clock) - input. This input increments the prescaler which increments the counter connected to the two PWMB blocks. While both PWMB blocks are disabled, the internal input buffer is disconnected from the pin and no external pull-up DSP56005 DSP56005 Data Sheet MOTOROLA Pin Descriptions PWMB OnCE Port out of the OnCE serial port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE serial port on the rising edge. If the DSCK/OS1 pin is an output and used in conjunction with the OS0 pin, it provides information about the chip status when the DSP is not in the debug mode. The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. The pin is three-stated when it is changing from input to output. During hardware reset, this pin is defined as an output and is driven low. is necessary. While the PWMB blocks are programmed to use the internal clock, the internal input buffer is disconnected from the pin and no external pull-up is necessary. On-Chip Emulation (OnCETM) Port The following paragraphs describe the pins associated with the OnCE Port controller and its serial interface. DSI/OS0 (Debug Serial Input/Chip Status 0) - bidirectional. The DSI/OS0 pin, when an input, is the pin through which serial data or commands are provided to the OnCE port controller. The data received on the DSI pin will be recognized only when the DSP has entered the debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSP is not in the debug mode, the DSI/OS0 pin provides information about the chip status if it is an output and used in conjunction with the OS1 pin. When switching from output to input, the pin is three-stated. During hardware reset, this pin is defined as an output and it is driven low. NOTE: To avoid possible glitches, an external pull-down resistor should be attached to this pin. DSO (Debug Serial Output) - output. The debug serial output provides the data contained in one of the OnCE port controller registers as specified by the last command received from the command controller. The most significant bit (MSB) of the data word is always shifted out of the OnCE serial port first. Data is clocked out of the OnCE Port serial port on the rising edge of DSCK. NOTE: To avoid possible glitches, an external pull-down resistor should be attached to this pin. DSCK/OS1(Debug Serial Clock/Chip Status 1) - bidirectional. The DSCK/OS1 pin, when an input, is the pin through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and MOTOROLA DSP56005 DSP56005 Data Sheet The DSO pin also provides acknowledge pulses to the external command controller. When the chip enters the debug mode, the DSO pin will be pulsed low to indicate (acknowledge) that the OnCE Port is waiting for commands. After receiving a read command, the DSO pin will be pulsed low to indicate that the requested data is available and the OnCE Port serial port is ready to receive clock pulses in order to deliver the data. After receiving a write command, the DSO pin will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; 15 Pin Descriptions OnCE Port Power and Ground after the data is written, another acknowledge pulse will be provided. During hardware reset and when idle, the DSO pin is held high. DR (Debug Request) - active low input. The debug request input provides a means of entering the debug mode of operation. This pin, when asserted, will cause the DSP to finish the current instruction being executed, to save the instruction pipeline information, to enter the debug mode, and to wait for commands to be entered from the debug serial input line. While the DSP is in the debug mode, the user can reset the OnCE Port controller by asserting DR, waiting for an acknowledge from DSO, and then deasserting DR. It may be necessary to reset the OnCE Port controller in cases where synchronization between the OnCE Port controller and external circuitry is lost. Asserting DR when the DSP is in the Wait or the Stop state, and keeping it asserted until an acknowledge pulse in the DSP is produced, sends the DSP into the debug mode. After receiving the acknowledge, DR must be deasserted before sending the first OnCE Port command. Power and Ground NOTE: To avoid possible glitches, an external pull-up resister should be attached to this pin The power and ground pins are presented in the following paragraphs. There are ten sets of power and ground pins (see Table 25). In accordance with good engineering practice, VCC should be bypassed to ground (as needed) by a 0.1 µF capacitor located as close as possible to the chip package. The two circuits where this bypassing is most important are the PLL and the core processor internal logic circuits. 16 Power These VCC pins provide power to the circuits listed in Table 25, "DSP56005 DSP56005 Power Supply Pins," on page 77. The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail. VCCP (PLL Circuit Power). This pin supplies a quiet power source to the Phase-Locked Loop (PLL) to provide greater frequency stability. The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail. VCCP should be bypassed to GNDP by a 0.1 µF capacitor located as close as possible to the chip package. Ground These pins provide grounds for the circuits listed in Table 25, "DSP56005 DSP56005 Power Supply Pins," on page 77. The pins should be provided with an extremely low impedance path to ground. GNDP (PLL Circuit Ground). This pin supplies a quiet ground source to the PLL to provide greater frequency stability. The pin should be provided with an extremely low impedance path to ground. VCCP should be bypassed to GNDP by a 0.1 µF capacitor located as close as possible to the chip package. Interrupt and Mode Control The interrupt and mode control pins select the chip's operating mode as it comes out of hardware reset and receive interrupt requests from external sources after reset. DSP56005 DSP56005 Data Sheet MOTOROLA Pin Descriptions Interrupt and Mode Control MODA/IRQA (Mode Select A/External Interrupt Request A) - input. This input pin has three functions: MODB/IRQB (Mode Select B/External Interrupt Request B) - input. This input pin has two functions: · to work with the MODB and MODC pins to select the chip's initial operating mode · to work with the MODA and MODC pins to select the chip's initial operating mode · to allow an external device to request a DSP interrupt after internal synchronization · to allow an external device to request a DSP interrupt after internal synchronization · to turn on the internal clock generator when the DSP in the Stop processing state, causing the chip to resume processing MODB is read and internally latched in the DSP when the processor exits the reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODB pin changes to the external interrupt request IRQB. The chip operating mode can be changed by software after reset. MODA is read and internally latched in the DSP when the processor exits the reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODA pin changes to the external interrupt request IRQA. The chip operating mode can be changed by software after reset. The IRQA input is a synchronized external interrupt request. It may be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases. While the DSP is in the Stop processing state, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to act as MODA. MOTOROLA The IRQB input is a synchronized external interrupt request. It may be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to act as MODB. MODC/NMI (Mode Select C/Non-Maskable Interrupt Request) - edge triggered input. This input pin has two functions: · to work with the MODA and MODB pins to select the chip's initial operating mode · to allow an external device to request a DSP interrupt after internal synchronization DSP56005 DSP56005 Data Sheet 17 Pin Descriptions Interrupt and Mode Control Clock, Oscillator, and PLL MODC is read and internally latched in the DSP when the processor exits the reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODC pin changes to the non-maskable interrupt request, NMI. The chip operating mode can be changed by software after reset. The NMI input is a negative-edge triggered external interrupt request. This is a level 3 interrupt that can not be masked out. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to act as MODC. IRQC (External Interrupt Request C) - edge triggered input. This negative edge triggered input allows an external device to request a DSP interrupt after internal synchronization. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQC will generate multiple interrupts also increases. IRQD (External Interrupt Request D) - edge triggered input. This negative edge triggered input allows an external device to request a DSP interrupt after internal synchronization. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQD will 18 generate multiple interrupts also increases. RESET (Reset) - input. This input is a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. When the reset pin is deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODC pins. The chip also samples the PINIT pin and writes its status into the PEN bit of the PLL Control Register. When the chip comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal. Clock, Oscillator, and PLL The following pins are dedicated to the PLL, clock, and oscillator operation. CKOUT (Output Clock) - output. This output pin provides a 50% duty cycle output clock synchronized to the internal processor clock when the PLL is enabled and locked. When the PLL is disabled, the output clock at CKOUT is derived from, and has the same frequency and duty cycle as, EXTAL. DSP56005 DSP56005 Data Sheet NOTE: If the PLL is enabled and the multiplication factor is less than or equal to 4, then CKOUT is synchronized to EXTAL. (For information on the DSP56005 DSP56005's PLL multiplication factor, see Section 3.5 - DSP56005 DSP56005 Phase-Locked Loop Configuration in the DSP56005 DSP56005 User's Manual. MOTOROLA Pin Descriptions Clock, Oscillator, and PLL EXTAL (External Clock/Crystal) - input. This pin may be used in one of two ways: · driven from an external clock · interface the internal crystal oscillator input to an external crystal circuit If the PLL is enabled, this pin is internally connected to the on-chip PLL. The PLL can multiply the frequency on the EXTAL pin to generate the internal DSP clock. The PLL output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two PLL output clock periods. If the PLL is disabled, EXTAL is divided by two to produce the four-phase instruction cycle clock. XTAL (Crystal) - output. This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL should not be connected. It may be disabled through MOTOROLA software control using the XTLD bit in the PLL control register. PCAP (PLL Filter Capacitor) - input. This input is used to connect a high quality external capacitor needed for the PLL filter. The capacitor should be as close as possible to the chip with heavy, short traces connecting one terminal of the capacitor to PCAP and the other terminal to VCCP. PINIT (PLL Initialization) - input. During the assertion of hardware reset, the value at the PINIT input pin is written into the PEN bit of the PLL control register. When high, the PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output. When the bit is clear, the PLL is disabled and the chip's internal clocks are derived from the clock connected to the EXTAL pin. After hardware reset is deasserted, the PINIT pin is ignored. DSP56005 DSP56005 Data Sheet 19 Pin Descriptions 20 DSP56005 DSP56005 Data Sheet MOTOROLA Electrical Characteristics Electrical Specifications The preliminary DC/AC electrical specifications are generated from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. The DSP56005 DSP56005 is fabricated in high density CMOS with TTL compatible inputs and outputs. Table 6 Maximum Ratings (GND = 0Vdc) Rating Symbol Value Unit Supply Voltage VCC -0.3 to +7.0 V All Input Voltages VIN GND - 0.5 to VCC + 0.5 V I 10 mA TJ -40 to +105 °C Tstg -55 to +150 °C Current Drain per Pin Excluding VCC and GND Operating Temperature Range Storage Temperature Table 7 Thermal Characteristics of the TQFP Package Thermal Resistance Symbol Value Rating Junction to Ambient JA 49 °C/W Junction to Case JC 8 °C/W NOTE: This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). MOTOROLA DSP56005 DSP56005 Data Sheet 21 DC Electrical Characteristics DC Electrical Characteristics VCC = 5.0 Vdc ± 10%; TJ = -40° to +105°C Table 8 DC Electrical Characteristics Characteristics Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V VIH VIHC VIHR VIHM 2.0 4.0 2.5 3.5 - - - - VCC VCC VCC VCC V V V V VIL VILC VILM -0.5 -0.5 -0.5 - - - 0.8 0.6 2.0 V V V IIN -1 - 1 µA Three-State (Off-State) Input Current (@ 2.4V / 0.4V) ITSI -10 - 10 µA Output High Voltage (IOH = -0.4 mA) VOH 2.4 - - V Output Low Voltage (IOL = 3.2 mA; HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA) VOL - - 0.4 V ICCI ICCW ICCS - - - 125 25 2 TBD TBD TBD mA mA µA PLL Supply Current (See Note 4) - TBD TBD mA Clockout Supply Current (See Note 5) - TBD TBD mA - 10 - pF Supply Voltage Input High Voltage · Except EXTAL, RESET, MODA, MODB, MODC · EXTAL · RESET · MODA, MODB, MODC Input Low Voltage · Except EXTAL, MODA, MODB, MODC · EXTAL · MODA, MODB, MODC Input Leakage Current EXTAL, RESET, MODA/IRQA, MODB/IRQB, MODC/NMI Internal Supply Current 5.5 V, 50 MHz (See Note 3) · in Wait Mode (See Note 1) · in Stop Mode (See Note 1) Input Capacitance (See Note 2) CIN NOTES: 1. 2. 3. 4. 5. 22 In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Periodically sampled and not 100% tested Power Consumption in the Design Considerations section describes how to calculate the external supply current. Values given are for PLL enabled. Values given are for CKOUT enables. DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Internal Clocks AC Electrical Characteristics The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5V and a VIH minimum of 2.4V for all pins, except EXTAL, RESET, MODA, MODB, and MODC. These five pins are tested using the input levels set forth in DC Electrical Characteristics. AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. DSP56005 DSP56005 output levels are measured on the production test machine with VOL and VOH reference levels set at 0.8V and 2.0V respectively. Internal Clocks For each occurrence of TH, TL, TC or ICYC substitute with the numbers given in Table 9: Table 9 Internal Clocks Characteristics Symbol Internal Operation Frequency Expression f Internal Clock High Period TH - with PLL disabled ETH - with PLL enabled and MF 4 (Min) 0.48 x ETC x DF/MF (Max) 0.52 x ETC x DF/MF (See Note 2) - with PLL enabled and MF > 4 (Min) 0.467 x ETC x DF/MF (Max) 0.533 x ETC x DF/MF Internal Clock Low Period (See Note 1) TL - with PLL disabled ETL - with PLL enabled and MF 4 (Min) 0.48 x ETC x DF/MF (Max) 0.52 x ETC x DF/MF - with PLL enabled and MF > 4 (Min) 0.467 x ETC x DF/MF (See Note 1) (Max) 0.533 x ETC x DF/MF Internal Clock Cycle Time Instruction Cycle Time TC ICYC ETC x DF/MF (See Note 1) 2 x TC NOTES: 1. 2. The "E" in ETH, ETL, and ETC means external. MF is the PCTL Multiplication Factor bits (MF0 - MF11). DF is the PCTL Division Factor bits (DF0 - DF3). MOTOROLA DSP56005 DSP56005 Data Sheet 23 AC Electrical Characteristics Clock Clock The DSP56005 DSP56005 system clock may be derived from the on-chip crystal oscillator as shown in Figure 3, or it may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected (see Figure 4) to the board or socket. The rise and fall time of this external clock should be 3 ns maximum. When using a crystal to provide a clock input, the frequency must be greater than 500 kHz. This restriction does not apply when providing an external clock to the EXTAL pin. XTAL EXTAL EXTAL XTAL R R2 R1 C1 C XTAL1 C L1 C2 XTAL1* C3 3rd Overtone Crystal Oscillator Fundamental Frequency Crystal Oscillator Suggested Component Values R = 680 k ± 10% C = 20 pF ± 20% Suggested Component Values R1 = 470 k ± 10% R2 = 330 ± 10% C1 = 0.1 µF ± 20% C2 = 26 pF ± 20% C3 = 20 pF ± 10% L1 = 2.37 µH ± 10% XTAL = 50 MHz, AT cut, 20 pF load, 50 max series resistance NOTES: NOTES: 1. The suggested crystal source is ICM, # 433163 - 4.00 (4 MHz fundamental, 20 pF load) 2. To reduce system cost, a ceramic resonator may be used instead of the crystal. Suggested source: Murata-Erie #CST4.00MGW040 00MGW040 (4 MHz fundamental) 1. *3rd overtone crystal. 2. The suggested crystal source is ICM, # 471163 - 50.00 (50 MHz 3rd overtone, 20 pF load). 3. R2 limits crystal current. 4. Reference Benjamin Parzen, The Design of Crystal and Other Harmonic Oscillators, John Wiley & Sons, 1983. Figure 3 Crystal Oscillator Circuits 24 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Clock VILC EXTAL Midpoint VIHC ETH ETL 1 2 3 ETC 4 NOTE: The midpoint is VILC + 0.5 (VIHC - VILC). Figure 4 External Clock Timing Table 10 Clock Operation 50 MHz Num Characteristics Symbol Unit Min 1 Clock Input High Clock Input Low MHz ETH 9.34 8.5 235500 ns ns ETL 9.34 8.5 235500 ns ns 20 20 409600 ns ns ICYC 40 40 819200 ns ns Clock Cycle Time · with PLL disabled · with PLL enabled 4 50 (See Note) · with PLL disabled (46.7% - 53.3% duty cycle) · with PLL enabled (42.5% - 57.5% duty cycle) 3 0 (See Note) · with PLL disabled (46.7% - 53.3% duty cycle) · with PLL enabled (42.5% - 57.5% duty cycle) 2 f ETC Frequency of Operation (EXTAL Pin) Max Instruction Cycle Time = ICYC = 2 × TC (See Note) · with PLL disabled · with PLL enabled NOTE: External Clock Input High and External Clock Input Low are measured at 50% of the input transition. MOTOROLA DSP56005 DSP56005 Data Sheet 25 AC Electrical Characteristics PLL Phase-Locked Loop (PLL) Table 11 Phase-Locked Loop Characteristics Characteristics VCO frequency when PLL enabled PLL external capacitor (PCAP pin to VCCP) Expression Min Max Unit MF x Ef (See Notes 1,2) 10 f (See Note 3) MHz MF × 340 MF × 380 MF × 480 MF × 970 pF MF × Cpcap (See Note 4) @ MF < 4 @ MF > 4 NOTES: 1. 2. 3. 4. 26 The "E" in Ef, ETH, ETL, and ETC means external. MF is the PCTL Multiplication Factor bits (MF0 - MF11). DF is the PCTL Division Factor bits (DF0 - DF3). The maximum VCO frequency is limited to the internal operation frequency. Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF=1. The recommended value for Cpcap is 400 pF for MF 4 and 540 pF for MF > 4. DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing Reset, Stop, Mode Select, and Interrupt Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Loads WS = Number of wait states (1 WS = TC) programmed into external bus access using BCR (WS = 0 - 15) Table 12 Reset, Stop, Mode Select, and Interrupt Timing 50 MHz Num Characteristics Unit Min Max - 26 ns 75000 × TC 25 × TC 2500 × TC - - - ns ns ns 8 × TC 9 × TC + 20 ns 8.5 TC ns 8 × TC 8 × TC + 6 ns 9 Delay from RESET Assertion to Address High Impedance (periodically sampled and not 100% tested) 10 Minimum Stabilization Duration · Internal Oscillator PLL Disabled (See Note 1) · External Clock PLL Disabled (See Note 2) · External Clock PLL Enabled (See Note 2) 11 Delay from Asynchronous RESET Deassertion to First External Address Output (Internal Reset Deassertion) 12 Synchronous Reset Setup Time from RESET Deassertion to CKOUT Falling Edge 13 Synchronous Reset Delay Time from the CKOUT Falling Edge to the First External Address Output 14 Mode Select Setup Time 21 - ns 15 Mode Select Hold Time 0 - ns 16 Minimum Edge-Triggered Interrupt Request Assertion Width 13 - ns 16a Minimum Edge-Triggered Interrupt Request Deassertion Width 13 - ns Delay from IRQA, IRQB, NMI Assertion to External Memory Access Address Out Valid · Caused by First Interrupt Instruction Fetch · Caused by First Interrupt Instruction Execution 5 × TC + TH 9 × TC + TH - - ns ns Delay from IRQA, IRQB, NMI Assertion to General Purpose Transfer Output Valid caused by First Interrupt Instruction Execution 11 × TC + TH - ns - 2 TC + TL + (TC × WS) - 23 ns - 2TC + (TC × WS) - 21 ns - - 2 × TC - 21 TC + TL + (TC × WS) - 21 ns ns 17 18 19 Delay from Address Output Valid caused by First Interrupt Instruction Execute to Interrupt Request Deassertion for Level Sensitive Fast Interrupts (See Note 3) 20 Delay from RD Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts (See Note 3) 21 Delay from WR Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts · WS = 0 · WS > 0 (See Note 3) MOTOROLA DSP56005 DSP56005 Data Sheet 27 AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing Table 12 Reset, Stop, Mode Select, and Interrupt Timing (continued) 50 MHz Num Characteristics Unit Min Max Delay from General-Purpose Output Valid to Interrupt Request Deassertion for Level Sensitive Fast Interrupts If Second Interrupt Instruction is: · Single Cycle · Two Cycles (See Note 3) - - TL - 31 (2 × TC) + TL - 31 ns ns 23 Synchronous Interrupt Setup Time from IRQA, IRQB, NMI Assertion to the CKOUT transition #2 10 TC ns 24 Synchronous Interrupt Delay Time from the CKOUT transition #2 to the First External Address Output Valid caused by the First Instruction Fetch after coming out of Wait State 13 × TC + TH 13 × TC + TH + 6 ns 12 - ns 65548 × TC 20 × TC 13 × TC - - - ns ns ns Duration of Level Sensitive IRQA Assertion to ensure interrupt service (when exiting `Stop') · Internal Crystal Oscillator Clock, OMR bit 6 = 0 · Stable External Clock, OMR bit 6 = 1 · Stable External Clock, PCTL bit 17 = 1 (See Note 1) 65534 × TC + TL 6 × TC + TL 12 - - - ns ns ns Delay from Level Sensitive IRQA Assertion to Fetch of First Interrupt Instruction (when exiting `Stop') · Internal Crystal Oscillator Clock, OMR bit 6 = 0 · Stable External Clock, OMR bit 6 = 1 · Stable External Clock, PCTL bit 17= 1 (See Note 1) 65548 × TC 20 × TC 13 × TC - - - ns ns ns 22 25 Duration for IRQA Assertion to Recover from Stop State 26 Delay from IRQA Assertion to Fetch of First Interrupt Instruction (when exiting `Stop') · Internal Crystal Oscillator Clock, OMR bit 6 = 0 · Stable External Clock, OMR bit 6 = 1 · Stable External Clock, PCTL bit 17 = 1 (See Note 1) 27 28 NOTES: 1. A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: · after power-on reset, and · when recovering from Stop mode. During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 × TC is typically allowed to assure that the oscillator is stable before executing programs. 2. Circuit stabilization delay is required during reset when using an external clock in two cases: · after power-on reset, and · when recovering from Stop mode. 3. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deassertive edge-triggered mode is recommended when using fast interrupt. Long interrupts are recommended when using level-sensitive mode. 28 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing VIHR RESET 10 11 9 A0-A15 A0-A15 First Fetch Figure 5 Reset Timing CKOUT 12 RESET 13 A0-A15 A0-A15, DS, PS X/Y Figure 6 Synchronous Reset Timing VIHR RESET 14 15 VIHM MODA, MODB MODC VIH VILM VIL IRQA, IRQB, NMI Figure 7 Operating Mode Select Timing MOTOROLA DSP56005 DSP56005 Data Sheet 29 AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing IRQA, IRQB NMI 16 IRQA, IRQB NMI 16A Figure 8 External Interrupt Timing (Negative Edge-Triggered) A0-A15 A0-A15 First Interrupt Instruction Execution/Fetch RD 20 WR 21 19 17 IRQA IRQB NMI a) First Interrupt Instruction Execution General Purpose I/O 22 18 IRQA IRQB NMI b) General Purpose I/O Figure 9 External Level-Sensitive Fast Interrupt Timing 30 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing T0, T2 CKOUT T1, T3 23 IRQA, IRQB NMI 24 A0-A15 A0-A15, DS PS, X/Y Figure 10 Synchronous Interrupt from Wait State Timing 25 IRQA 26 First Instruction Fetch A0-A15 A0-A15, DS PS, X/Y Figure 11 Recovery from Stop State Using IRQA IRQA 27 28 A0-A15 A0-A15, DS PS, X/Y First IRQA Interrupt Instruction Fetch Figure 12 Recovery from Stop State Using IRQA Interrupt Service MOTOROLA DSP56005 DSP56005 Data Sheet 31 AC Electrical Characteristics Host I/O Timing Host I/O Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Load Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications. Table 13 Host I/O Timing 50 MHz Num Characteristics Unit Min 31 HEN/HACK Assertion Width (See Note 1) · CVR, ICR, ISR, RXL Read · IVR, RXH/M Read · Write Max TC + 31 26 13 - - - ns 13 2 × TC + 31 2 × TC + 31 - - - ns ns ns 32 33 Host Data Input Setup Time Before HEN/HACK Deassertion 4 - ns 34 Host Data Input Hold Time After HEN/HACK Deassertion 3 - ns 35 HEN/HACK Assertion to Output Data Active from High Impedance 0 - ns 36 HEN/HACK Assertion to Output Data Valid - 26 ns 37 HEN/HACK Deassertion to Output Data High Impedance (See Note 5) - 18 ns 38 Output Data Hold Time After HEN/HACK Deassertion (See Note 6) 2.5 - ns 39 HR/W Low Setup Time Before HEN Assertion 0 - ns 40 HR/W Low Hold Time After HEN Deassertion 3 - ns 41 HR/W High Setup Time to HEN Assertion 0 - ns 42 HR/W High Hold Time After HEN/HACK Deassertion 3 - ns 43 HA0-HA2 Setup Time Before HEN Assertion 0 - ns 44 HA0-HA2 Hold Time After HEN Deassertion 3 - ns 45 32 HEN/HACK Deassertion Width (See Note 1) · Between Two TXL Writes (See Note 2) · Between Two CVR, ICR, ISR, RXL Reads (See Note 3) DMA HACK Assertion to HREQ Deassertion (See Note 4) 3 45 ns DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Host I/O Timing Table 13 Host I/O Timing (Continued) 50 MHz Num Characteristics Unit Min 46 DMA HACK Deassertion to HREQ Assertion (See Notes 4, 5) · for DMA RXL Read · for DMA TXL Write · all other cases Max TL + TC + TH TL + TC 0 - - - ns ns ns 47 Delay from HEN Deassertion to HREQ Assertion for RXL Read (See Notes 4, 5) TL + TC + TH - ns 48 Delay from HEN Deassertion to HREQ Assertion for TXL Write (See Notes 4, 5) TL + TC - ns 49 Delay from HEN Assertion to HREQ Deassertion for RXL Read, TXL Write (See Notes 4, 5) 3 58 ns NOTES: 1. 2. 3. 4. 5. 6. See Host Port Use Considerations in the Design Considerations section of this data sheet. This timing must be adhered to only if two consecutive Writes to the TXL are executed without polling TXDE or HREQ. This timing must be adhered to only if two consecutive reads from one of these registers are executed without polling the corresponding status bits or HREQ. HREQ is pulled up by a 1k resistor. Specifications are periodically sampled and not 100% tested. May decrease to 0 ns for future versions. MOTOROLA DSP56005 DSP56005 Data Sheet 33 AC Electrical Characteristics Host I/O Timing HREQ (Output) 32 31 HACK (Input) 42 41 HR/W (Input) 37 36 35 H0-H7 (Output) 38 Data Valid Figure 13 Host Interrupt Vector Register (IVR) Read 34 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Host I/O Timing HREQ (Output) 49 RXM Read (Input) Data Valid 43 Data Valid 44 Address Valid (Input) Address Valid 32 31 HA2-HA0 RXL Read Address Valid RXH Read HEN 47 42 41 HR/W (Input) 36 H0-H7 (Output) 37 35 38 Data Valid Figure 14 Host Read Cycle (Non-DMA Mode) MOTOROLA DSP56005 DSP56005 Data Sheet 35 AC Electrical Characteristics Host I/O Timing HREQ (Output) 49 TXH Write HEN (Input) TXL TXM 32 31 44 43 Address Valid HA2-HA0 (Input) 48 Address Valid Address Valid 39 40 HR/W (Input) 33 34 H0-H7 (Input) Data Valid Data Valid Data Valid Figure 15 Host Write Cycle (Non-DMA Mode) HREQ (Output) 45 RXH Read RXM Read 36 RXL Read 37 35 H0-H7 (Output) 46 32 31 HACK (Input) 46 46 38 Data Valid Data Valid Data Valid Figure 16 Host DMA Read Cycle 36 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Host I/O Timing HREQ (Output) 45 46 31 HACK (Input) 46 32 TXH Write TXM Write TXL Write 33 34 H0-H7 (Input) Data Valid Data Valid Data Valid Figure 17 Host DMA Write Cycle MOTOROLA DSP56005 DSP56005 Data Sheet 37 AC Electrical Characteristics SCI Timing Serial Communication Interface (SCI) Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Load, tSCC = Synchronous Clock Cycle Time (for internal clock, tSCC is determined by the SCI clock control register and TC). The minimum tSCC value is 8 × TC. Table 14 SCI Synchronous Mode Timing 50 MHz Num Characteristics Unit Min Max 8 × TC - ns 55 Synchronous Clock Cycle - tSCC 56 Clock Low Period tSCC/2 - 10.5 - ns 57 Clock High Period tSCC/2 - 10.5 - ns 58 < intentionally blank > 59 Output Data Setup to Clock Falling Edge (Internal Clock) 60 - - - tSCC/4 + TL - 26 - ns Output Data Hold After Clock Rising Edge (Internal Clock) tSCC/4 -TL - 8 - ns 61 Input Data Setup Time Before Clock Rising Edge (Internal Clock) tSCC/4 + TL + 23 - ns 62 Input Data Not Valid Before Clock Rising Edge (Internal Clock) - tSCC/4 + TL - 5.5 ns 63 Clock Falling Edge to Output Data Valid (External Clock) - 32.5 ns 64 Output Data Hold After Clock Rising Edge (External Clock) TC + 3 - ns 65 Input Data Setup Time Before Clock Rising Edge (External Clock) 16 - ns 66 Input Data Hold Time After Clock Rising Edge (External Clock) 21 - ns Table 15 SCI Asynchronous Mode Timing - 1X Clock 50 MHz Num Characteristics Unit Min Max 64 × TC - ns 67 68 Clock Low Period tACC/2 -11 - ns 69 Clock High Period tACC/2 -11 - ns 70 < intentionally blank > - - - 71 Output Data Setup to Clock Rising Edge (Internal Clock) tACC/2 -51 - ns 72 38 Asynchronous Clock Cycle - tACC Output Data Hold After Clock Rising Edge (Internal Clock) tACC/2 -51 - ns DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics SCI Timing Internal Clock 55 57 56 SCLK (Output) 59 60 TXD Data Valid 61 62 Data Valid RXD External Clock 55 57 SCLK (Input) 56 63 64 TXD Data 65 RXD Valid 66 Data Valid Figure 18 SCI Synchronous Mode Timing MOTOROLA DSP56005 DSP56005 Data Sheet 39 AC Electrical Characteristics SCI Timing 67 69 68 1X SCLK (Output) 72 71 TXD NOTE: Data Valid In the wire-OR mode, TXD can be pulled up by 1 K Figure 19 SCI Asynchronous Mode Timing 40 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics SSI Timing Synchronous Serial Interface (SSI) Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°CL = 50 pF + 2 TTL Load, tSSICC = SSI clock cycle time TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) = Receive Frame Sync i ck = Internal Clock x ck = External Clock g ck = Gated Clock i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (Synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length Table 16 SSI Timing 50 MHz Num Characteristics Case Unit - - i ck x ck ns Min Max 4 × TC 3 × TC 80 Clock Cycle-tSSICC (See Note 1) 81 Clock High Period tSSICC/2 - 10.8 TC + TL - - i ck x ck ns 82 Clock Low Period tSSICC/2 - 10.8 TC + TL - - i ck x ck ns 83 < intentionally blank > - - - - 84 SRD Rising Edge to FSR Out (bl) High - - 40.8 25.8 x ck i ck a ns 85 SRD Rising Edge to FSR Out (bl) Low - - 35.8 25.8 x ck i ck a ns 86 SRD Rising Edge to FSR Out (wl) High - - 35.8 20.8 x ck i ck a ns 87 RXC Rising Edge to FSR Out (wl) Low - - 35.8 20.8 x ck i ck a ns MOTOROLA DSP56005 DSP56005 Data Sheet 41 AC Electrical Characteristics SSI Timing Table 16 SSI Timing (Continued) 50 MHz Num Characteristics Case Min Unit Max 88 Data In Setup Time Before RXC (SCK in Synchronous Mode) Falling Edge 3.3 15.8 13 - - - x ck i ck a i ck s ns 89 Data In Hold Time After RXC Falling Edge 18 3.3 - - x ck i ck ns 90 FSR Input (bl) High Before RXC Falling Edge 0.8 17.4 - - x ck i ck a ns 91 FSR Input (wl) High Before RXC Falling Edge 3.3 18.3 - - x ck i ck a ns 92 FSR Input Hold Time After RXC Falling Edge 18.3 3.3 - - x ck i ck ns 93 Flags Input Setup Before RXC Falling Edge 0.8 16.7 - - x ck i ck s ns 94 Flags Input Hold Time After RXC Falling Edge 18.3 3.3 - - x ck i ck s ns 95 TXC Rising Edge to FST Out (bl) High - - 31.6 15.8 x ck i ck ns 96 TXC Rising Edge to FST Out (bl) Low - - 33.3 18.3 x ck i ck ns 97 TXC Rising Edge to FST Out (wl) High - - 30.8 18.3 x ck i ck ns 98 TXC Rising Edge to FST Out (wl) Low - - 33.3 18.3 x ck i ck ns 99 TXC Rising Edge to Data Out Enable from High Impedance 33.3 + TH 20.8 x ck i ck ns - 33.3 + TH 22.4 x ck i ck ns - 100 TXC Rising Edge to Data Out Valid 101 TXC Rising Edge to Data Out High Impedance (See Note 2) - - 35.8 20.8 x ck i ck ns 101A TXC Falling Edge to Data Out High Impedance (See Note 2) - TC + TH g ck ns FST Input (bl) Setup Time Before TXC Falling Edge 0.8 18.3 x ck i ck ns - FST Input (wl) to Data Out Enable from High Impedance - 30.8 102 103 42 DSP56005 DSP56005 Data Sheet ns MOTOROLA AC Electrical Characteristics SSI Timing Table 16 SSI Timing (Continued) 50 MHz Num Characteristics Case Min Unit Max 104 FST Input (wl) Setup Time Before TXC Falling Edge 0.8 20.0 - - x ck i ck ns 105 FST Input Hold Time After TXC Falling Edge 18.3 3.3 - - x ck i ck ns 106 Flag Output Valid After TXC Rising Edge - - 32.5 20.8 x ck i ck ns NOTES: 1. 2. For Internal Clock, External Clock Cycle is defined by ICYC and SSI control register. Periodically sampled, and not 100% tested. MOTOROLA DSP56005 DSP56005 Data Sheet 43 AC Electrical Characteristics SSI Timing 80 81 82 TXC (Input/Output) 95 96 FST (Bit) Out 97 98 FST (Word) Out 100 101A 100 101 99 Data Out First Bit Last Bit 102 105 FST (Bit) In 103 105 104 FST (Word) In 106 (See Note) Flags Out NOTE: In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. Figure 20 SSI Transmitter Timing 44 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics SSI Timing 80 81 82 SRD (Input/Output) 84 85 FSR (Bit) Out 86 87 FSR (Word) Out 88 89 First Data In Bit Last Bit 92 90 FSR (Bit) In 91 92 93 94 FSR (Word) In Flags In Figure 21 SSI Receiver Timing MOTOROLA DSP56005 DSP56005 Data Sheet 45 AC Electrical Characteristics External Bus Asynchronous Timing External Bus Asynchronous Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Load WS = Number of Wait States, Determined by BCR Register (WS = 0 to 15) Capacitance Derating The DSP56005 DSP56005 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15 A0-A15, D0-D23 D0-D23, PS, DS, RD, WR, X/Y, EXTP) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications. Table 17 External Bus Asynchronous Timing 50 MHz Num Characteristics Unit Min 120 TL-6 TC-6 ns - - ns - ns - - ns TH-7 TH-2.5 ns (See Note 1) (See Note 2) WR Assertion Width · WS = 0 · WS > 0 TC WS x TC+TL 122 WR Deassertion to Address Not Valid 123 WR Assertion to Data Out Active · WS = 0 From High Impedance · WS > 0 124 125 Data Out Hold Time from WR Deassertion (the maximum specification is periodically sampled, and not 100% tested) TH-6 TH-4 0 Data Out Setup Time to WR Deassertion · WS = 0 · WS > 0 TL-0.8 WS x TC+TL-0.8 126 RD Deassertion to Address Not Valid 127 Address Valid to RD Deassertion · WS = 0 · WS > 0 128 46 - - Address Valid to WR Assertion · WS = 0 · WS > 0 121 Max TH ns - ns - ns - ns TC+TL-6 (WS+1)x TC)+TL-6 Input Data Hold Time to RD Deassertion DSP56005 DSP56005 Data Sheet 0 MOTOROLA AC Electrical Characteristics External Bus Asynchronous Timing Table 17 External Bus Asynchronous Timing (Continued) 50 MHz Num Characteristics Unit Min 130 Max - - TC+TL-9.5 (WS+1) x TC)+TL-9.5 TL-6 - - - TC-7.5 (WS+1) x TC)7.5 Address Valid to Input Data Valid ns · WS = 0 · WS > 0 131 Address Valid to RD Assertion 132 RD Assertion to Input Data Valid ns ns · WS = 0 · WS > 0 133 WR Deassertion to RD Assertion TC-7 - ns 134 RD Deassertion to RD Assertion TC-4 - ns 135 WR Deassertion to WR Assertion - - ns ns - ns ns · WS = 0 · WS > 0 136 TC-4 TC+TH-4 RD Deassertion to WR Assertion TC-4 TC+TH-4 · WS = 0 · WS > 0 NOTES: 1. 2. WR Deassertion to the end of valid data. WR Deassertion to data high impedance. MOTOROLA DSP56005 DSP56005 Data Sheet 47 AC Electrical Characteristics External Bus Asynchronous Timing A0-A15 A0-A15, DS, PS, X/Y (See Note) 127 131 126 134 129 RD 120 122 135 133 121 WR 136 132 130 123 128 125 D0-D23 D0-D23 NOTE: 124 Data Out Data In During Read-Modify-Write instructions, the address lines do not change state. Figure 22 External Bus Asynchronous Timing 48 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics External Bus Synchronous Timing External Bus Synchronous Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Load Capacitance Derating The DSP56005 DSP56005 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15 A0-A15, D0-D23 D0-D23, PS, DS, RD, WR, X/Y, EXTP) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications. Table 18 External Bus Synchronous Timing 50 MHz Num Characteristics Unit Min Max - 6.2 ns · WS=0 (See Note 1) · WS>0 - - 4.4 TH+4.4 ns ns 142 CKOUT Rising Edge to WR Deassertion 1.3 9.1 ns 143 CKOUT Rising Edge to RD Assertion - 3.9 ns 144 CKOUT Rising Edge to RD Deassertion 0 3.4 ns 145 CKOUT Falling Edge to Data-Out Valid - 5.4 ns 146 CKOUT Falling Edge to Data-Out Invalid (See Note 3) 0 - ns ns 147 Data-In Valid To CKOUT Rising Edge (Setup) 3.4 - ns 148 CKOUT Rising Edge to Data-In Invalid (Hold) 0 - ns 149 CKOUT Falling Edge to Address Invalid (See Note 3) 0 - ns 170 EXTAL to CKOUT - PLL Disabled EXTAL to CKOUT - PLL Enabled and MF < 5 3 0.3 9.7 3.7 ns ns 140 CKOUT Falling Edge to Address Valid 141 CKOUT Rising Edge to WR Assertion NOTES: 1. 2. 3. 4. AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. WS are Wait state values specified in the BCR. CKOUT Falling Edge to data-out invalid (specification T146) and CKOUT Falling Edge to address invalid (specification T149) indicate the time after which data/address are no longer guaranteed to be valid. Timings are given from CKOUT midpoint to VOL or VOH of the corresponding pin(s). MOTOROLA DSP56005 DSP56005 Data Sheet 49 AC Electrical Characteristics External Bus Synchronous Timing T0 T1 T2 T3 T0 T1 T2 T3 T0 CKOUT A0-A15 A0-A15 DS, PS EXTP, X/Y 140 149 143 144 RD 141 142 WR 147 148 D0-D23 D0-D23 Data Out Data In 145 146 EXTAL 170 NOTE: During Read-Modify-Write Instructions, the address lines do not change states. Figure 23 Synchronous Bus Timing 50 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics OnCE Port Timing OnCETM Port Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Loads Table 19 OnCE Port Timing 50 MHz Num Characteristics Unit Min Max 230 DSCK Low 40 - ns 231 DSCK High 40 - ns 232 DSCK Cycle Time 200 - ns 233 DR Asserted to DSO (ACK) Asserted 5TC - ns 234 DSCK High to DSO Valid - 42 ns 235 DSCK High to DSO Invalid 3 - ns 236 DSI Valid to DSCK Low (Setup) 15 - ns 237 DSCK Low to DSI Invalid (Hold) 3 - ns 238 Last DSCK Low to OS0-OS1, ACK Active 3TC + TL - ns 239 DSO (ACK) Asserted to First DSCK High 2TC - ns 240 DSO (ACK) Assertion Width 4TC + TH - 3 5TC + 7 ns 241 DSO (ACK) Asserted to OS0-OS1 High Impedance (See Note 2) - 0 ns 242 OS0-OS1 Valid to CKOUT Rising Edge TC - 21 - ns 243 CKOUT Rising Edge to OS0-OS1 Invalid 0 - ns 244 Last DSCK Low of Read Register to First DSCK High of Next Command 7TC + 10 - ns 245 Last DSCK Low to DSO Invalid (Hold) 3 - ns 246 DR Assertion to CKOUT Rising Edge for Wake Up from Wait State 12 TC ns 247 CKOUT Rising Edge to DSO After Wake Up from Wait State 17TC 248 DR Assertion Width · to recover from Wait · to recover from Wait and enter DEBUG mode 249 MOTOROLA DR Assertion to DSO (ACK) Valid (Enter Debug Mode) after Asynchronous Recovery from Wait State DSP56005 DSP56005 Data Sheet ns 15 13TC+15 12TC - 15 - ns 17TC - ns 51 AC Electrical Characteristics OnCE Port Timing Table 19 OnCE Port Timing (Continued) 50 MHz Num Characteristics Unit Min 250A Max 15 15 15 65548TC 65548TC + TL 20TC + TL 13TC + TL ns 65549TC 65549TC + TL 21TC + TL 14TC + TL - - - ns 65553TC 65553TC + TL 25TC + TL 18TC + TL - - - DR Assertion Width to Recover from Stop · Stable External Clock, OMR bit 6 = 0 · Stable External Clock, OMR bit 6 = 1 · Stable External Clock, PCTL bit 17= 1 (See Note 1) 250B DR Assertion Width to Recover from Stop and Enter Debug Mode · Stable External Clock, OMR bit 6 = 0 · Stable External Clock, OMR bit 6 = 1 · Stable External Clock, PCTL bit 17= 1 (See Note 1) 251 DR Assertion to DSO (ACK) Valid (Enter Debug Mode) after Recovery from Stop State · Stable External Clock, OMR bit 6 = 0 · Stable External Clock, OMR bit 6 = 1 · Stable External Clock, PCTL bit 17= 1 (See Note 1) ns NOTES: 1. 2. 52 A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: · after power-on reset · when recovering from stop mode During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 x TC is typically allowed to assure that the oscillator is stable before executing programs. While it is possible to set OMR bit 6 = 1 when using the internal crystal oscillator, it is not recommended and these specifications do not guarantee timings for that case. The maximum specified is periodically sampled and not 100% tested. DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics OnCE Port Timing 230 DSCK (Input) 231 232 Figure 24 OnCE Serial Clock Timing DR (Input) 233 DSO (Output) (ACK) Figure 25 OnCE Acknowledge Timing DSCK (Input) DSO (Output) (OS1) (Last) (ACK) 236 237 238 (OS0) DSI (Input) (See Note) NOTE: High Impedance, external pull-down resistor Figure 26 OnCE Data I/O To Status Timing MOTOROLA DSP56005 DSP56005 Data Sheet 53 AC Electrical Characteristics OnCE Port Timing DSCK (Input) (Last) (See Note) 234 235 245 DSO (Output) NOTE: High Impedance, external pull-down resistor Figure 27 OnCE Read Timing 239 OS1 (Output) (See Note) 241 (DSCK Input) 240 DSO (Output) (DSO Output) (DSI Input) OS0 (Output) 241 (See Note) 236 237 NOTE: High Impedance, external pull-down resistor Figure 28 OnCE Data I/O To Status Timing 54 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics OnCE Port Timing CKOUT 242 OS0-OS1 (Output) (See Note) 243 NOTE: High Impedance, external pull-down resistor Figure 29 OnCE CKOUT To Status Timing DSCK (Input) (Next Command) 244 Figure 30 OnCE Read Register to Next Command Timing CKOUT T0, T2 T1, T3 248 DR (Input) 246 247 DSO (Output) Figure 31 Synchronous Recovery from Wait State MOTOROLA DSP56005 DSP56005 Data Sheet 55 AC Electrical Characteristics OnCE Port Timing 248 DR (Input) 249 DSO (Output) Figure 32 Asynchronous Recovery from Wait State DR (Input) 250 251 DSO (Output) Figure 33 Asynchronous Recovery from Wait State 56 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics Timer Timing Timer Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Loads Table 20 Timer Timing 50 MHz Num Characteristics Unit Min Max 260 TIO Low 2TC+7 - ns 261 TIO High 2TC+7 - ns 262 Synchronous Timer Setup Time from TIO (input) Asssertion to CKOUT Rising Edge 10 TC ns 263 Synchronous Timer Delay Time from CKOUT Rising Edge to the External Memory Access Address Out Valid Caused by First Interrupt Instruction Execution 5TC+TH - ns 264 CKOUT Rising Edge to TIO (output) Assertion 0 8 ns 265 CKOUT Rising Edge to TIO (output) Deassertion 0 8 ns 266 CKOUT Rising Edge to TIO (General Purpose Output) 0 8 ns TIO 261 260 Figure 34 TIO Timer/ Event Input Restrictions MOTOROLA DSP56005 DSP56005 Data Sheet 57 AC Electrical Characteristics Timer Timing CKOUT TIO (Input) 262 ADDRESS 263 First Interrupt Instruction Execution Figure 35 Timer Interrupt Generation CKOUT TIO (Output) 264 265 Figure 36 External Pulse Generation fetch the instruction MOVE X0,X:(R0) ; X0 contains the new value of TIO 266 ; and R0 contains the address of TCSR CKOUT A0-A15 A0-A15 PS, DS EXTP, X/Y TIO (Output) Figure 37 GPIO Output Timing 58 DSP56005 DSP56005 Data Sheet MOTOROLA AC Electrical Characteristics PWM Timing Pulse Width Modulator (PWM) Timing VCC = 5.0 Vdc ± 10%, TJ = -40° to +105°C, CL = 50 pF + 2 TTL Load WPS WCN ick xck = = = = PWM Prescale Factor PWM Count Internal Clock External Clock Table 21 PWM Timing 50 MHz Num Characteristics Case Min Unit Max 280 PWM External Clock Low (TWL) TC + 3 - ns 281 PWM External Clock High (TWH) TC + 3 - ns 282 PWM External Clock Cycle (TWC) 2 x TC + 6 - ns 283 PWM External Carrier Low 2 x TC + 3 x WPS x TC + 14 3 x TC + TWC + TWL +14 3 x TC + 1.5 x WPS x TWC + 14 - - - 284 PWM External Carrier High 15 - ns 285 PWM Clock Rising Edge to PWM Output Assertion - 2 x TC+TL+35 ns 286 PWM Carrier Rising Edge to PWM Output Assertion 3 x TC 3 x TC 3 x TC 287 PWM Clock Rising Edge to PWM Output Deassertion - 2 x TC + TL + 35 ns ns 288 PWM Output Assertion Time (See Note) 2 x WCN x WPS x TC - 3 WCN x WPS x TWC - TC - 3 2 x WCN x WPS x TC + 3 WCN x WPS x TWC + TC + 3 ick xck ns 289 Synchronous PWM Rising Edge Clock Setup Time to CKOUT Falling Edge 12 TC - 3 ns 290 Synchronous PWM Carrier Setup Time to CKOUT Rising Edge 14 TC - 2 ns 291 CKOUT Rising Edge to PWM Output Assertion for Synchronous Operation 2 x TC+WPS × TC + 3 2 x TC + TWL + 3 2 x TC + .5 x WPS x TWC + 3 292 PWM Output Assertion Time In Synchronous Operation WCN x WPS x TWC - 3 NOTE: ick xck WPS = 1 xck WPS > 1 ick 2 x TC + 3 x WPS x TC + 35 xck WPS = 1 3 x TC + TWC + TWL + 35 xck WPS > 1 3 x TC + 1.5 x WPS x TWC + 35 TC + 3 x WPS x TC + 26 ick TC + TWC + TWL + 26 xck WPS = 1 TC + 1.5 x WPS x TWC + 26 xck WPS > 1 WCN x WPS x TWC + 3 ns ns ns ns ns If WCN=0 then the Output is not asserted at all. MOTOROLA DSP56005 DSP56005 Data Sheet 59 Electrical Characteristics PWM Timing PWACLK PWBCLK 281 280 282 Figure 38 PWM Clock Input Restrictions PWACn PWBC 284 283 Figure 39 PWM Carrier Input Restrictions PWACLK PWBCLK PWACn PWBC 285 287 PWAPn PWBm 286 288 Figure 40 PWM Output Asynchronous Operation 60 DSP56005 DSP56005 Data Sheet MOTOROLA Electrical Characteristics PWM Timing CKOUT 289 PWACLK PWBCLK PWACn PWBC 290 PWAPn PWBm 291 292 Figure 41 PWM Output Synchronous Operation MOTOROLA DSP56005 DSP56005 Data Sheet 61 Pin-out and Package 144-pin TQFP Top View Pin-out and Package Information 109 Orientation Mark (Top View) 1 37 MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET PINIT VCCP PCAP GNDP XTAL EXTAL HA2/PB10 HA2/PB10 GNDH VCCQ GNDQ HA1/PB9 HA0/PB8 HACK/PB14 HACK/PB14 VCCH HEN/PB12 HEN/PB12 GNDH HR/W/PB11 HR/W/PB11 HREQ/PB13 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5 H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 WR RD SRD/PC7 SC1/PC4 GNDS STD/PC8 SC2/PC5 SCK/PC6 VCCS SC0/PC3 TXD/PC1 GNDS RXD/PC0 SCLK/PC2 TIO PWAP0 PWAN0 VCCQ GNDQ PWAC0 GNDW PWAP1 PWAN1 PWAC1 VCCW PWAP2 PWAN2 PWAC2 GNDW PWACLK PWB0 PWB1 PWBC PWBCLK IRQC nc A15 A14 GNDA A13 VCCA A12 A11 A10 GNDA A9 A8 A7 A6 GNDA VCCA A5 GNDQ VCCQ A4 A3 A2 GNDA A1 A0 PS VCCA DS GNDA X/Y EXTP DSI/OS0 DSO DR GNDC DSCK/OS1 VCCC 73 D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7 D8 D9 GNDD D10 D11 VCCD D12 D13 GNDD VCCQ GNDQ D14 D15 D16 D17 GNDD D18 D19 VCCD D20 D21 GNDD D22 D23 IRQD Top and bottom views of the Thin Quad Flat Package (TQFP) are shown in Figure 42 and Figure 43 with their pin-outs. NOTES: 1. "nc" are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. Figure 42 Top View of the DSP56005 DSP56005 144-pin Plastic Thin Quad Flat Package (TQFP) 62 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package 109 Orientation Mark (on Top side) (Bottom View) 1 37 A15 A14 GNDA A13 VCCA A12 A11 A10 GNDA A9 A8 A7 A6 GNDA VCCA A5 GNDQ VCCQ A4 A3 A2 GNDA A1 A0 PS VCCA DS GNDA X/Y EXTP DSI/OS0 DSO DR GNDC DSCK/OS1 VCCC nc IRQC PWBCLK PWBC PWB1 PWB0 PWACLK GNDW PWAC2 PWAN2 PWAP2 VCCW PWAC1 PWAN1 PWAP1 GNDW PWAC0 GNDQ VCCQ PWAN0 PWAP0 TIO SCLK/PC2 RXD/PC0 GNDS TXD/PC1 SC0/PC3 VCCS SCK/PC6 SC2/PC5 STD/PC8 GNDS SC1/PC4 SRD/PC7 RD WR MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET PINIT VCCP PCAP GNDP XTAL EXTAL HA2/PB10 HA2/PB10 GNDH VCCQ GNDQ HA1/PB9 HA0/PB8 HACK/PB14 HACK/PB14 VCCH HEN/PB12 HEN/PB12 GNDH HR/W/PB11 HR/W/PB11 HREQ/PB13 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5 H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 73 IRQD D23 D22 GNDD D21 D20 VCCD D19 D18 GNDD D17 D16 D15 D14 GNDQ VCCQ GNDD D13 D12 VCCD D11 D10 GNDD D9 D8 D7 D6 GNDD D5 D4 VCCD D3 D2 GNDD D1 D0 144-pin TQFP Bottom View NOTES: 4. "nc" are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 5. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 6. To simplify locating the pins, each fifth pin is shaded in the illustration. Figure 43 Bottom View of the DSP56005 DSP56005 144-pin Plastic Thin Quad Flat Package (TQFP) MOTOROLA DSP56005 DSP56005 Data Sheet 63 Pin-out and Package Shipping Tray Orientation Marks Top View 5 x 12 Figure 44 DSP56005 DSP56005 144-pin TQFP Shipping Tray 64 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package By General Purpose I/O MOTOROLA DSP56005 DSP56005 Data Sheet 65 Pin-out and Package By Pin Number 66 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package By Pin Number MOTOROLA DSP56005 DSP56005 Data Sheet 67 Pin-out and Package By Pin Number 68 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package By Signal Name MOTOROLA DSP56005 DSP56005 Data Sheet 69 Pin-out and Package By Signal Name 70 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package By Signal Name MOTOROLA DSP56005 DSP56005 Data Sheet 71 Pin-out and Package By Signal Name 72 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package Power Supply Pins MOTOROLA DSP56005 DSP56005 Data Sheet 73 Pin-out and Package Power Supply Pins 74 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package MOTOROLA DSP56005 DSP56005 Data Sheet 75 Pin-out and Package 76 DSP56005 DSP56005 Data Sheet MOTOROLA Pin-out and Package Table 25 DSP56005 DSP56005 Power Supply Pins "005PV 005PV" 144-pin TQFP Pin Power Supply 113 VCCA Circuit Supplied 123 134 111 GNDA Address Bus Buffers 117 122 130 136 144 VCCC 142 GNDC 67 VCCCK 69 GNDCK 79 Bus Control Buffers VCCD Clock 92 103 76 82 GNDD Data Bus Buffers 89 95 100 106 MOTOROLA DSP56005 DSP56005 Data Sheet 77 Pin-out and Package Table 25 DSP56005 DSP56005 Power Supply Pins (Continued) "005PV 005PV" 144-pin TQFP Pin Power Supply 41 VCCH 52 39 GNDH Circuit Supplied Host Interface Buffers 45 50 58 18 57 88 VCCQ 126 Internal Logic 19 56 GNDQ 87 125 64 VCCP 62 GNDP 25 VCCW 21 29 9 GNDW 78 Pulse Width Modulator VCCS 5 12 PLL GNDS DSP56005 DSP56005 Data Sheet Serial Port MOTOROLA Pin-out and Package MOTOROLA DSP56005 DSP56005 Data Sheet 79 Pin-out and Package S 0.204 (0.008) M T L S - M S N S N S A 0.508 (0.020) M T L S - M S PIN 1 IDENT J1 -L-, -M-, -N- J1 109 144 1 108 Z VIEW Y 3 PL NOTES: B V VIEW Y 36 73 37 72 0.508 (0.020) M T L S - M N S 0.204 (0.008) M T L S - M E S S N S -H- C 0.102 (0.004) -T- SEATING G 140 PL W PLANE PLATING VIEW P F J B1 1. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 2. Controlling dimension: millimeter. 3. Datum plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. Datums -L-, -M- and -N- to be determined at datum plane -H-. 5. Dimensions S and V to be determined at seating plane -T-. 6. Dimensions A and B do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are determined at datum plane -H-. 7. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 (0.003) total in excess of the Ddimension at maximum material condition. DIM MILLIMETERS MIN MAX INCHES MIN MAX A 0.13 (0.005) M T L-M S 0.791 1.400 1.600 0.056 0.062 0.170 0.280 0.0067 0.0110 1.350 1.450 0.054 0.057 0.160 0.270 0.063 0.011 G 0.500 BSC 0.197 BSC J 0.007 0.018 0.029 21.900 22.100 0.863 0.870 21.900 22.100 0.863 0.870 W 0.050 0.150 0.002 0.006 Z R2 0.005 0.750 V -H- 0.180 0.450 S R1 0.130 K 1 SEATING PLANE 0.783 F A1 20.100 E 12° 2 PL SECTION J1-J1 144 PL (ROTATED 90°) 0.791 19.900 D NS 0.783 C BASE METAL 20.100 B D 19.900 0.250 BSC A1 0.100 B1 0.100 C1 VIEW P K C1 R1 2 0.0098 BSC 0.004 0.150 1.000 REF 0.004 0.006 0.039 REF 0.150 REF 0.006 REF 0.250 0.006 0.010 05 85 05 85 2 DSP56005 DSP56005 Data Sheet 0.150 1 80 R2 05 85 05 85 MOTOROLA Pin-out and Package Figure 45 DSP56005 DSP56005 144-pin TQFP Mechanical Information MOTOROLA DSP56005 DSP56005 Data Sheet 81 Design Considerations Heat Dissipation Design Considerations outside ambient (CA). These terms are related by the equation: Heat Dissipation The average chip junction temperature, TJ, in °C, can be obtained from: TJ = TA + (PD × JA) (1) Where: TA = ambient temperature, °C JA = package thermal resistance, junction-to-ambient, °C/W PD = PINT + PI/O PINT = ICC × VCC watts - chip internal power PI/O = power dissipation on input and output pins - user determined For most applications PI/O < PINT and PI/O can be neglected. An appropriate relationship between PD and TJ (if PI/O is neglected) is: PD = K/(TJ + 273) (2) Solving equations (1) and (2) for K gives: K = PD × (TA + 273) + PD × JA (3) JA = JC + CA (4) JC is device-related and cannot be influenced by the user. However, CA is user-dependent and can be minimized by thermal management techniques such as heat sinks, ambient air cooling, and thermal convection. Thus, good thermal management can significantly reduce CA so that JA approximately equals JC. Values for thermal resistance presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, "Thermal Resistance Measurement Method for MC68XX MC68XX Microcomponent Devices", and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup. User-derived values for thermal resistance may differ. Note: Table 7, "Thermal Characteristics of the TQFP Package," on page 21 contains the package thermal values for this chip. Where: K is a constant pertaining to the particular package K can be determined from equation (2) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the MOTOROLA DSP56005 DSP56005 Data Sheet 77 Design Considerations Power, Ground, and Noise Power Consumption Power, Ground, and Noise Each DSP56005 DSP56005 VCC pin should be provided with a low-impedance path to the board's supply. Each DSP56005 DSP56005 GND pin should also be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip as shown in Table 25, "DSP56005 DSP56005 Power Supply Pins," on page 77. The VCC power supply should be bypassed to GND using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and GND should be less than 0.5" per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on this DSP have fast rise and fall times. Printed Circuit Board (PCB) trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the RD, WR, IRQA, IRQB, IRQC, IRQD, NMI, HEN, and HACK pins. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. Power Consumption Power dissipation is a key issue in portable DSP applications. This section describes some factors which affect current consumption. This current consumption is described by the formula: I = C×V×f where: C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle For example, for a Port A address pin loaded with a 50 pF capacitance and operating at 5.5V with a 40 MHz clock, toggling at its maximum possible rate (which is 10 MHz), the current consumption is: I = 50 × 10-12 × 5.5 × 10 × 106 = 2.75 mA The Maximum Internal Current value (ICCI-max), reflects the maximum possible switching of the internal buses, which is not necessarily a real application case. The Typical Internal Current value (ICCI-typ) reflects the average switching of the internal buses. The following steps are recommended for applications requiring very low current consumption: 1. minimize external memory accesses; use internal memory accesses instead 2. minimize the number of pins which are switching 3. minimize the capacitive load on the pins 4. connect the unused inputs to pull-up or pull-down resistors 78 DSP56005 DSP56005 Data Sheet MOTOROLA Design Considerations Host Programming Considerations Current consumption test code: org p:RESET jmp org movep move move move move nop rep move rep mov clr move rep mac move jmp TP1 nop jmp 2. Overwriting Transmit Byte Registers The host program should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register. MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #$00FF,m0 #$00FF,m4 #256 3. Synchronization of Status Bits from DSP to Host r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 y:(r4)+,y0 a,p:(r5) TP1 MAIN Host Port Considerations Careful synchronization is required when reading multi-bit registers that are written by