DSP56000/ DSP56001 DSP56000/DSP56001 DSP56000/56001 00000E 0000FF 00A000 2468AC - Datasheet Archive
APPENDIX A INSTRUCTION SET DETAILS Freescale Semiconductor, Inc. This appendix contains detailed information about each
Freescale Semiconductor, Inc. APPENDIX A INSTRUCTION SET DETAILS Freescale Semiconductor, Inc. This appendix contains detailed information about each instruction in the DSP56000/ DSP56000/ DSP56001 DSP56001 instruction set. An instruction guide is presented first to help understand the individual instruction descriptions. This guide is followed by sections on notation and addressing modes. Since parallel moves are allowed with many of the instructions, they are discussed before the instructions. The instructions are then discussed in alphabetical order. A.1 INSTRUCTION GUIDE The following information is included in each instruction description with the goal of making each description self-contained: 1. Name and Mnemonic: The mnemonic is highlighted in bold type for easy reference. 2. Assembler Syntax and Operation: For each instruction syntax, the corresponding operation is symbolically described. If there are several operations indicated on a single line in the operation field, those operations do not necessarily occur in the order shown but are generally assumed to occur in parallel. If a parallel data move is allowed, it will be indicated in parenthesis in both the assembler syntax and operation fields. If a letter in the mnemonic is optional, it will be shown in parenthesis in the assembler syntax field. 3. Description: A complete text description of the instruction is given together with any special cases and/or condition code anomalies of which the user should be aware when using that instruction. 4. Example: An example of the use of the instruction is given. The example is shown in DSP56000/DSP56001 DSP56000/DSP56001 assembler source code format. Most arithmetic and logical instruction examples include one or two parallel data moves to illustrate the many types of parallel moves that are possible. The example includes a complete explanation, which discusses the contents of the registers referenced by the instruction (but not those referenced by the parallel moves) both before and after the execution of the instruction. Most examples are designed to be easily understood without the use of a calculator. 5. Condition Codes: The status register is depicted with the condition code bits which can be affected by the instruction highlighted in bold type. Not all bits in the status register are used. Those which are reserved are indicated with a double asterisk and are read as zeros. 6. Instruction Format: The instruction fields, the instruction opcode, and the instruction extension word are specified for each instruction syntax. When the extension MOTOROLA DSP56000/DSP56001 DSP56000/DSP56001 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com A-1 word is optional, it Freescale Semiconductor, be assumed by each of the is so indicated. The values which can Inc. variables in the various instruction fields are shown under the instruction field's heading. Note that the symbols used in decoding the various opcode fields of an instruction are completely arbitrary. Furthermore, the opcode symbols used in one instruction are completely independent of the opcode symbols used in a different instruction. Freescale Semiconductor, Inc. 7. Timing: The number of oscillator clock cycles required for each instruction syntax is given. This information provides the user a basis for comparison of the execution times of the various instructions in oscillator clock cycles. Refer to Table A-1 and A.7 INSTRUCTION TIMING for a complete explanation of instruction timing, including the meaning of the symbols ``aio'', ``ap'', ``ax'', ``ay'', ``axy'', ``ea'', ``jx'', ``mv'', ``mvb'', ``mvc'', ``mvm'', ``mvp'', ``rx'', ``wio'', ``wp'', ``wx'', and ``wy''. 8. Memory: The number of program memory words required for each instruction syntax is given. This information provides the user a basis for comparison of the number of program memory locations required for each of the various instructions in 24bit program memory words. Refer to Table A-1 and A.7 INSTRUCTION TIMING for a complete explanation of instruction memory requirements, including the meaning of the symbols ``ea'' and ``mv''. A.2 NOTATION Each instruction description contains symbols used to abbreviate certain operands and operations. Table A-1 lists the symbols used and their respective meanings. Depending on the context, registers refer to either the register itself or the contents of the register. A.3 ADDRESSING MODES The addressing modes are grouped into three categories: register direct, address register indirect, and special. These addressing modes are summarized in Table A-2. All address calculations are performed in the address ALU to minimize execution time and loop overhead. Addressing modes, which specify whether the operands are in registers, in memory, or in the instruction itself (such as immediate data), provide the specific address of the operands. The register direct addressing mode can be subclassified according to the specific register addressed. The data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0, A, and B. The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR. Address register indirect modes use an address register Rn (R0R7) to point to locations in X, Y, and P memory. The contents of the Rn address register (Rn) is the effective address (ea) of the specified operand, except in the ``indexed by offset'' mode where the effective address (ea) is (Rn+Nn). Address register indirect modes use an address modifier register Mn to specify the type of arithmetic to be used to update the address register Rn. If an addressing mode specifies an address offset register Nn, the given address offset register is used to update the corresponding address register Rn. The Rn address register may only use the corresponding address offset register Nn and the corresponding address modifier register Mn. For example, the address register R0 may only use the A-2 DSP56000/DSP56001 DSP56000/DSP56001 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table A-1 Instruction Description Notation Data ALU Registers Operands Input Register X1 or X0 (24 Bits) Yn Input Register Y1 or Y0 (24 Bits) An Accumulator Registers A2, A1, A0 (A2 - 8 Bits, A1 and A0 - 24 Bits) Bn Accumulator Registers B2, B1, B0 (B2 - 8 Bits, B1 and B0 - 24 Bits) X Freescale Semiconductor, Inc. Xn Input Register X = X1: X0 (48 Bits) Y Input Register Y = Y1: Y0 (48 Bits) A Accumulator A = A2: A1: A0 (56 Bits)* B Accumulator B = B2: B1: B0 (56 BIts)* AB Accumulators A and B = A1: B1 (48 Bits)* BA Accumulators B and A = B1: A1 (48 Bits)* A10 Accumulator A = A1: A0 (48 Bits) B10 Accumulator B= B1:B0 (48 bits) * NOTE: In data move operations, shifting and limiting are performed when this register is specified as a source operand. When specified as a destination operand, sign extension and possibly zeroing are performed. Address ALU Registers Operands Rn Address Registers R0 - R7 (16 Bits) Nn Address Offset Registers N0 - N7 (16 Bits) Mn Address Modifier Registers M0 - M7 (16 Bits) N0 address offset register and the M0 address modifier register during actual address computation and address register update operations. This unique implementation is extremely powerful and allows the user to easily address a wide variety of DSP-oriented data structures. All address register indirect modes use at least one set of address registers (Rn, Nn, and Mn), and the XY memory reference uses two sets of address registers, one for the X memory space and one for the Y memory space. The special addressing modes include immediate and absolute addressing modes as well as implied references to the program counter (PC), the system stack (SSH or SSL), and program (P) memory. Addressing modes may also be categorized by the ways in which they may be used. MOTOROLA DSP56000/DSP56001 DSP56000/DSP56001 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com A-3 Freescale Semiconductor, Inc. Table A-1 Instruction Description Notation (Continued) Program Controller Registers Operands Program Counter Register (16 Bits) MR Mode Register (8 Bits) CCR Condition Code Register (8 Bits) SR Status Register = MR:CCR (16 Bits) OMR Operating Mode Register (8 Bits) LA Freescale Semiconductor, Inc. PC Hardware Loop Address Register (16 Bits) LC Hardware Loop Counter Register (16 Bits) SP System Stack Pointer Register (6 Bits) SSH Upper Portion of the Current Top of the Stack (16 Bits) SSL Lower Portion of the Current Top of the Stack (16 Bits) SS System Stack RAM = SSH: SSL (15 Locations by 32 Bits) Address Operands ea Effective Address eax Effective Address for X Bus eay Effective Address for Y Bus xxxx Absolute Address (16 Bits) xxx Short Jump Address (12 Bits) aa Absolute Short Address (6 Bits, Zero Extended) pp I/O Short Address (6 Bits, Ones Extended) Specifiies the Contents of the Specified Address X: X Memory Reference Y: Y Memory Reference L: Long Memory Reference = X:Y P: Program Memory Reference Table A-3 shows the various categories to which each addressing mode belongs. The following classifications will be used in the instruction descriptions. Table A-3. DSP56000/DSP56001 DSP56000/DSP56001 Addressing Mode Encoding These addressing mode categories may be combined so that additional, more restrictive classifications may be defined. For example, the instruction descriptions may use a A-4 DSP56000/DSP56001 DSP56000/DSP56001 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table A-1 Instruction Description Notation (Continued) Miscellaneous Operands Source Operand Register D, Dn Destination Operand Register D [n] Bit n of D Destination Operand Register #n Immediate Short Data (5 Bits) #xx Freescale Semiconductor, Inc. S, Sn Immediate Short Data (8 Bits) #xxx Immediate Short Data (12 Bits) #xxxxxx Immediate Data (24 Bits) Unary Operators - Negation Operator - Logical NOT Operator PUSH Push Specified Value onto the System Stack (SS) Operator PULL Pull Specified Value from the System Stack (SS) Operator READ Read the Top of the System Stack (SS) Operator PURGE Delete the Top Value on the System Stack (SS) Operator | Absolute Value Operator | Binary Operators + Addition Operator - Subtraction Operator * Multiplication Operator ÷, / Division Operator + Logical Inclusive OR Operator · Logical AND Operator Logical Exclusive OR Operator ² "Is Transferred To" Operator : Concatenation Operator memory alterable classification, which refers to addressing modes that are both memMOTOROLA DSP56000/DSP56001 DSP56000/DSP56001 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com A-5 Freescale Semiconductor, Inc. Table A-1 Instruction Description Notation (Continued) Addressing Mode Operators I/O Short Addressing Mode Force Operator < Short Addressing Mode Force Operator > Long Addressing Mode Force Operator # Immediate Addressing Mode Operator #> Freescale Semiconductor, Inc.