DS90CF383 TIA/EIA-644 DS100033-1 DS90CF383MTD MTD56 DS100033 DS100033-4 - Datasheet Archive

 

DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description Features The DS90CF383

 

DS90CF383 DS90CF383 DS90CF383 DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description Features The DS90CF383 DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. n n n n n n n n n n n n n n n 20 to 65 MHz shift clock support Single 3.3V supply Chipset (Tx + Rx) power consumption < 250 mW (typ) Power-down mode ( < 0.5 mW total) Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Up to 227 Megabytes/sec bandwidth Up to 1.8 Gbps throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package Falling edge data strobe Transmitter Compatible with TIA/EIA-644 TIA/EIA-644 LVDS standard ESD rating > 7 kV Block Diagrams DS90CF383 DS90CF383 DS100033-1 DS100033-1 Order Number DS90CF383MTD DS90CF383MTD See NS Package Number MTD56 MTD56 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1997 National Semiconductor Corporation DS100033 DS100033 www.national.com DS90CF383 DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz July 1997 Absolute Maximum Ratings Package Derating: DS90CF383 DS90CF383 ESD Rating (HBM, 1.5 k, 100 pF) (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. 12.5 mW/°C above +25°C > 7 kV Recommended Operating Conditions Supply Voltage (VCC) -0.3V to +4V CMOS/TTL Input Voltage -0.3V to (VCC + 0.3V) LVDS Driver Output Voltage -0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150°C Storage Temperature -65°C to +150°C Lead Temperature (Soldering, 4 sec) +260°C Maximum Package Power Dissipation Capacity @ 25°C MTD56 MTD56 (TSSOP) Package: DS90CF383 DS90CF383 1.63 W Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (V Min 3.0 Nom 3.3 Max 3.6 Units V -10 0 +25 +70 2.4 °C V 100 mVPP CC) Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units V CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 VOH High Level Output Voltage IOH = -0.4 mA VOL Low Level Output Voltage IOL = 2 mA VCL Input Clamp Voltage ICL = -18 mA IIN Input Current V IOS Output Short Circuit Current 2.7 VOUT = 0V 3.3 V V V ± 5.1 ± 10 µA -60 = VCC, GND, 2.5V or 0.4V 0.3 -1.5 -120 mA 345 450 mV 35 OUT 0.1 -0.79 V mV LVDS DC SPECIFICATIONS VOD Differential Output Voltage VOD Change in V OD between complimentary output states VOS Offset Voltage (Note 4) VOS Change in V OS between complimentary output states RL = 100 250 1.125 IOS Output Short Circuit Current V Output TRI-STATE ® Current VTH Differential Input High Threshold I IN Input Current mA ± 10 µA +100 Differential Input Low Threshold -5 ±1 mV VCM = +1.2V VTL OUT = 0V, RL = 100 V mV -3.5 Power Down = 0V, VOUT = 0V or VCC 1.375 35 IOZ 1.25 -100 V IN V IN mV ± 10 ± 10 = +2.4V, VCC = 3.6V = 0V, VCC = 3.6V µA µA TRANSMITTER SUPPLY CURRENT ICCTW ICCTG ICCTZ Transmitter Supply Current Worst Case Transmitter Supply Current 16 Grayscale Transmitter Supply Current Power Down www.national.com RL = 100, CL = 5 pF, Worst Case Pattern (Figures 1, 3) f = 32.5 MHz 31 45 mA f = 37.5 MHz 32 50 mA f = 65 MHz 37 55 mA RL = 100, CL = 5 pF, 16 Grayscale Pattern (Figures 2, 3) f = 32.5 MHz 23 35 mA f = 37.5 MHz 28 40 mA f = 65 MHz 31 45 mA 10 55 µA Power Down = Low Driver Outputs in TRI-STATE ® under Power Down Mode 2 Electrical Characteristics (Continued) Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and V OD). Note 4: VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Typ Max Units LLHT Symbol LVDS Low-to-High Transition Time (Figure 3 ) Parameter Min 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 3 ) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 4 ) TCCS TxOUT Channel-to-Channel Skew (Figure 5 ) TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 ) f = 65 MHz -0.4 0 0.3 ps TPPos1 Transmitter Output Pulse Position for Bit 1 f = 65 MHz 1.8 2.2 2.5 ns TPPos2 Transmitter Output Pulse Position for Bit 2 f = 65 MHz 4.0 4.4 4.7 ns TPPos3 Transmitter Output Pulse Position for Bit 3 f = 65 MHz 6.2 6.6 6.9 ns TPPos4 Transmitter Output Pulse Position for Bit 4 f = 65 MHz 8.4 8.8 9.1 ns TPPos5 Transmitter Output Pulse Position for Bit 5 f = 65 MHz 10.6 11 11.3 ns TPPos6 Transmitter Output Pulse Position for Bit 6 f = 65 MHz 12.8 13.2 13.5 ns TCIP TxCLK IN Period (Figure 6) 15 T 50 ns TCIH TxCLK IN High Time (Figure 6) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 6) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN (Figure 6) f = 65 MHz 2.5 ns THTC TxIN Hold to TxCLK IN (Figure 6) f = 65 MHz 0 ns 5 250 ns ps TCCD TxCLK IN to TxCLK OUT Delay 25°C, VCC = 3.3V (Figure 7 ) 5.5 ns TPLLS Transmitter Phase Lock Loop Set (Figure 8 ) 10 ms TPDD Transmitter Power Down Delay (Figure 11) 100 ns 3 AC Timing Diagrams DS100033-4 DS100033-4 FIGURE 1. "Worst Case" Test Pattern 3 www.national.com AC Timing Diagrams (Continued) DS100033-5 DS100033-5 FIGURE 2. "16 Grayscale" Test Pattern (Notes 5, 6, 7, 8) Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 8: Recommended pin to signal mapping. Customer may choose to define differently. DS100033-6 DS100033-6 FIGURE 3. DS90CF383 DS90CF383 (Transmitter) LVDS Output Load and Transition Times DS100033-8 DS100033-8 FIGURE 4. DS90CF383 DS90CF383 (Transmitter) Input Clock Transition Time www.national.com 4 AC Timing Diagrams (Continued) DS100033-9 DS100033-9 Measurements at Vdiff = 0V TCCS measured between earliest and latest LVDS edges TxCLK Differential Low High Edge FIGURE 5. DS90CF383 DS90CF383 (Transmitter) Channel-to-Channel Skew and Pulse Width DS100033-10 DS100033-10 FIGURE 6. DS90CF383 DS90CF383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) DS100033-12 DS100033-12 FIGURE 7. DS90CF383 DS90CF383 (Transmitter) Clock In to Clock Out Delay 5 www.national.com AC Timing Diagrams (Continued) DS100033-14 DS100033-14 FIGURE 8. DS90CF383 DS90CF383 (Transmitter) Phase Lock Loop Set Time DS100033-16 DS100033-16 FIGURE 9. Seven Bits of LVDS in Once Clock Cycle DS100033-17 DS100033-17 FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.com 6 AC Timing Diagrams (Continued) DS100033-18 DS100033-18 FIGURE 11. Transmitter Power Down Delay DS100033-26 DS100033-26 FIGURE 12. Transmitter LVDS Output Pulse Position Measurement DS90CF383 DS90CF383 Pin Description-FPD Link Transmitter I/O No. TxIN Pin Name I 28 Description TxOUT+ O 4 Positive LVDS differentiaI data output. TxOUT- O 4 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT- O 1 Negative LVDS differential clock output. PWR DOWN I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down. VCC I 4 Power supply pins for TTL inputs. TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines-FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). 7 www.national.com DS90CF383 DS90CF383 Pin Description-FPD Link Transmitter I/O No. GND Pin Name I 4 (Continued) Ground pins for TTL inputs. Description PLL VCC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS VCC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. Applications Information and receiver devices. This change may enable the removal of a 5V supply from the system, and power may be supplied from an existing 3V power source. The DS90CF383 DS90CF383 and DS90CF384 DS90CF384 are backward compatible with the existing 5V FPD Link transmitter/receiver pair (DS90CF583 DS90CF583 and DS90CF584 DS90CF584). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC of both the transmitter 2. The DS90CF383 DS90CF383 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant. Pin Diagram DS90CF383 DS90CF383 DS100033-23 DS100033-23 Application DS100033-3 DS100033-3 www.national.com 8 9 DS90CF383 DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF383MTD DS90CF383MTD NS Package Number MTD56 MTD56 LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. 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