DS80C390 - Datasheet Archive

 

SEMICONDUCTOR ERRATA SHEET DS80C390 Revision A1 8/30/99 Revision A1 may be identified by the date/revision brand yywwA1, where yy

 

DALLAS SEMICONDUCTOR ERRATA SHEET DS80C390 DS80C390 Revision A1 8/30/99 Revision A1 may be identified by the date/revision brand yywwA1, where yy and ww are the year and workweek of manufacture, respectively. This errata sheet is valid only when used in conjunction with the most current version of the data sheet available from Dallas Semiconductor via the Internet. This document contains the following types of information: Errata: These are design errors which deviate from published specifications. Errata are intended to be fixed in subsequent revisions of the device. Specification Modifications: These are changes to the published specifications and will be reflected in the next update of the documentation and apply to all subsequent revisions of the device. Documentation Changes: This information includes typographical mistakes, errors, omissions or clarifications of device operation. Items listed in this section will be reflected in the next update of the documentation. ERRATA 1. Devices exhibit a sensitivity to latchup when overshoot currents exceed 10 mA. Work Around: Do not allow overshoot currents to exceed 10 mA. 2. Device will not operate from an external crystal. Work Around: Use an external clock oscillator to provide a timebase for the device. 3. System clock is not output on XTAL2, instead XTAL2 presents an inverted XTAL1 in enhanced hooks mode. This prevents high-speed and PLL emulation. Work Around: None, but initial emulation requirement of 16 MHz should be possible. 4. RST input has internal pull-up. Work Around: Pin must be overdriven or tied low. 5. RSTOL output inverted Work Around: Use external hardware to adjust logic level as needed. Page 1 of 3 6. R0, R1 working registers can only be modified from the current bank. For example, if the RS0=RS1=0 (working bank 0 selected), do not modify scratchpad RAM locations 08h, 09h (R0, R1 working bank 1), 10h, 11h (R0, R1 working bank 2), or 18h, 19h (R0, R1 working bank 3). Work Around: None. 7. The ring oscillator and associated features do not function. Work Around: None. 8. Registers associated with the Serial ports (SCON0, SCON1, SBUF1, SBUF0.2) can not be modified for at least 1 serial port clock period after the TI or RI bits are set by internal hardware. The documentation implies that these bits can be modified at any time. Work Around: The incorporation of a software delay can ensure a successful modification of the above mentioned registers. After reading the RI or TI bits in a logic 1 state, wait the following delay period, based on the serial port baud rate, before modifying the register: é ù 1 Delay = ê seconds ë baud _ rate ·16 Work Around: None. 9. Setting any of the PDCE3-0 bits will cause the device to malfunction. Work Around: None. 10. Using the CAN Bus in conjunction with PMM, Stop, or Idle modes will result in unexpected operation and should be avoided. Work Around: None. 11. CJNE instructions involving any register associated with the data pointers will not work correctly. Work Around: Avoid using these instructions. 12. Interrupts during MOVX instructions will push incorrect data onto the stack. Work Around: Disable interrupts prior to MOVX instructions, and enable afterwards. 13. Simultaneous interrupts at different priority levels will vector to incorrect locations. Work Around: Do not enable the high priority or PFI interrupts. Page 2 of 3 14. The JMP @A+DPTR does not calculate the correct jump address in 24-bit paged mode. Work Around: None. Do not use this instruction in 24-bit paged mode. 15. Use of the watchdog reset function while the CTM bit is set will cause unpredictable device operation. Work Around: Do not use the watchdog reset function in conjunction with the crystal clock multiplier. This erratum will be fixed in the next revision of the device. 16. Serial Port 0 will not operate correctly under the following conditions: 1. Timer 2 is used as the timebase (RCLK=TCLK=1), and 2. The SMOD bit for serial port 0 is cleared, and 3. Timer 1 is running (TR1=1). Work Around: Ensure that these conditions never occur simultaneously while using Serial Port 0. The easiest way is to use the serial port with the serial port doubler bit set (SMOD=1) SPECIFICATION MODIFICATIONS 1. The tRLAZ maximum AC timing specification will be replaced with a note stating "Address is held in a weak latch until overdriven by external memory." DOCUMENTATION CHANGES 1. NONE Page 3 of 3