DS70030E DS70118B DS70046B 0X4101 0X4105 ISO/TS-16949 11F-3 DK-2750 B505A - Datasheet Archive
dsPIC30F2010 Rev. A0 Silicon Errata dsPIC30F2010 (Rev. A0) Silicon Errata 3. The dsPIC30F2010 (Rev. A0) samples you have received
dsPIC30F2010 dsPIC30F2010 Rev. A0 Silicon Errata dsPIC30F2010 (Rev. A0) Silicon Errata 3. The dsPIC30F2010 (Rev. A0) samples you have received conform to the specifications and functionality described in the following documents: · DS70030E DS70030E dsPIC30F Programmer's Reference Manual · DS70118B DS70118B dsPIC30F2010 Data Sheet · DS70046B DS70046B dsPIC30F Family Reference Manual The exceptions to the specifications in the documents listed above are described in this section. dsPIC30F2010 Rev A0 silicon is identified by performing a "Reset and Connect" operation to the device using MPLAB® ICD 2 within the MPLAB IDE. The following text is visible under the MPLAB ICD 2 section in the Output window within MPLAB IDE: MPLAB ICD 2 Ready Connecting to MPLAB ICD 2 .Connected Setting Vdd source to target Target Device dsPIC30F2010 found, revision = 0x0 .Reading ICD Product ID Running ICD Self Test .Passed MPLAB ICD 2 Ready When a device reset occurs while an RTSP operation is in progress, code execution may lead into an Address Error trap. 4. 5. 1. Run-Time Self Programming (RTSP) of Program Flash Memory RTSP operations need to be timed by the application software. Self-timed write operations are not supported. 2. Write/Erase of Data EEPROM Y-Space Data Dependency When an instruction that writes to a location in the address range of Y-data memory is immediately followed by a MAC-type DSP instruction that reads a location also resident in Y-data memory, the operations will not be performed as specified. 6. IPC2 SFR Write Sequence A specific write sequence for IPC2 (Interrupt Priority Control 2) SFR is required. 7. Interrupting a REPEAT Loop When a REPEAT loop is interrupted by two or more interrupts in a nested fashion an Address Error Trap may be caused. 8. 32-bit General Purpose Timers The 32-bit General Purpose Timers do not function as specified for prescaler ratios other than 1:1. 9. The following list summarizes the errata described in further detail through the remainder of this document: Data EEPROM Speed Data EEPROM is operational at a device throughput of up to 25 MIPS. The errata described in this document will be fixed in future revisions of dsPIC30F2010 silicon. Silicon Errata Summary Reset during Run-Time Self Programming (RTSP) of Program Flash Memory 10-bit A/D Converter Sequential Sampling Sampling multiple channels sequentially using any conversion trigger other than the auto-convert feature requires SAMC bits to be non-zero. 10. Power-down Current, IPD The device exhibits IPD less than 0.1 µA. However, certain workarounds are required to achieve IPD in this range. The following sections will describe the errata and work around to these errata, where they may apply. Write/Erase operations performed on Data EEPROM need to be timed by the application software. Self-timed write operations are not supported. 2004 Microchip Technology Inc. Advance Information DS80178D-page 1 dsPIC30F2010 1. Module: RTSP of Program Flash Memory When performing Run Time Self Programming (RTSP) operations on Program Flash Memory or write operations on Data EEPROM, the device automatically times the erase/write operation. For this revision of silicon, this method of timing the erase/write operation is not supported. Note that this erratum does not affect programming Flash Memory using a device programmer, such as MPLAB® ICD 2 or PRO MATE®. Work around When updating Program Flash the programming cycle time must be controlled using an on-chip timer resource. Setting the TWRI(NVMCON) bit to a logic `1' enables the Program Flash programming cycle time to be terminated by the next acknowledged interrupt source. Therefore, the user must ensure that a single timer is configured to generate a CPU recognized interrupt and terminate the programming cycle. The timer cycle should be set for a value greater than 2 milliseconds but less than 5 milliseconds. Example 1 demonstrates this work around for a programming operation. A similar work around may be applied for an erase operation. EXAMPLE 1: ;The following code example assumes that the ;Write-latches have been pre-loaded and ;Timer1 has been set up to interrupt at the ;end of the programming cycle. CLR MyFlag ;Clear a flag CLR TMR1 ;Clear Timer1 BSET T1CON, #TON ;Turn Timer1 On DISI #8 MOV #0X4101 0X4101, W0 ;Load NVMCON with MOV W0, NVMCON ;bit8 set MOV #0X55, W0 ;Perform Unlock MOV W0, NVMKEY ;sequence MOV #0XAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR ;Set the WR bit NOP ;CPU stalls until NOP ;next interrupt L1: BTSS MyFlag, #0 ;Optionally wait BRA L1 ;for flag set ;by Timer1 ISR BCLR T1CON, #TON ;Turn off Timer1 . ;Continue _T1Interrupt: SETM MyFlag BCLR IFS0, #T1IF RETFIE DS80178D-page 2 ;Timer1 ISR ;Set a flag ;Clear T1IF and ;return from ISR 2. Module: Write/Erase of Data EEPROM When performing write/erase operations on Data EEPROM, the device automatically times the write/erase operation. For this revision of silicon, this method of timing the erase/write operation is not supported. Note that this erratum does not affect writing to Data EEPROM using a device programmer, such as MPLAB ICD 2 or PRO MATE. Work around When updating Data EEPROM the write cycle time must be controlled using an on-chip timer resource. Setting the TWRI(NVMCON) bit to a logic `1' enables the Data EEPROM write cycle time to be terminated by the next acknowledged interrupt source. Therefore, the user must ensure that a single timer is configured to generate a CPU recognized interrupt and terminate the write cycle. The timer cycle should be set for a value greater than 2 milliseconds but less than 5 milliseconds. Example 2 demonstrates this work around. A similar work around may be applied for an erase operation. EXAMPLE 2: ;The following code example assumes that the ;Write-latches have been pre-loaded and ;Timer1 has been set up to interrupt at the ;end of the write/erase cycle. CLR MyFlag ;Clear a flag CLR TMR1 ;Clear Timer1 BSET T1CON, #TON ;Turn Timer1 On DISI #8 MOV #0X4105 0X4105, W0 ;Load NVMCON with MOV W0, NVMCON ;bit8 set MOV #0X55, W0 ;Perform Unlock MOV W0, NVMKEY ;sequence MOV #0XAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR ;Set the WR bit NOP NOP L1: BTSS MyFlag, #0 ;Optionally, wait BRA L1 ;for flag set ;by Timer1 ISR BCLR T1CON, #TON ;Turn off Timer1 . ;Continue _T1Interrupt: SETM MyFlag BCLR IFS0, #T1IF RETFIE Advance Information ;Timer1 ISR ;Set a flag ;Clear T1IF and ;return from ISR 2004 Microchip Technology Inc. dsPIC30F2010 3. Module: Reset During RTSP of Program Flash Memory If a device reset occurs while an RTSP operation is in progress, code execution after the reset may lead to an Address Error Trap. Work around The user should define an Address Error Trap service routine as shown in Example 3 in order to resume normal code execution. 5. Module: Y-Space Data Dependency When an instruction that writes to a location in the address range of Y-data memory (addresses between 0x0900 and 0x09FF) is immediately followed by a MAC-type DSP instruction that reads a location also resident in Y-data memory, the two operations will not be executed as specified. This is demonstrated in Example 4. EXAMPLE 4: MOV EXAMPLE 3: _AddressError: bclr RCON, #TRAPR bclr reset ;Clear the Trap ;Reset Flag Bit INTCON1, #ADDRERR ;Clear the ;Address Error ;trap flag bit ;Software reset 4. Module: Data EEPROM Speed #0x090A, W0 ;Load address > = ;0x900 into W0 MOV #0x09B0, W10 ;Load address >= ;0x900 into W10 MOV W2, [W0+] ;Perform indirect ;write via W0 to ;address >= 0x900 MAC W4*W5, A, [W10]+=2, W5 ;Perform ;read operation ;using Y-AGU :Unexpected Results! Work around At device throughput greater than 25 MIPS, read operations performed on Data EEPROM may not function correctly. Work around When reading data from Data EEPROM, the application should perform a clock-switch operation to lower the frequency of the system clock so that the throughput is less than 25 MIPS. This may be easily performed at any time via the Oscillator Postscaler bits, POST (OSCCON), that allow the application to divide the system clock down by a factor of 4, 16 or 64. Work around 1: Insert a NOP between the two instructions as shown in Example 5. EXAMPLE 5: MOV #0x090A, W0 ;Load address > = ;0x900 into W0 MOV #0x09B0, W10 ;Load address >= ;0x900 into W10 MOV W2, [W0+] ;Perform indirect ;write via W0 to ;address >= 0x900 NOP ;No operation MAC W4*W5, A, [W10]+=2, W5 ;Perform ;read operation ;using Y-AGU :Correct Results! Work around 2: If Work around #1 is not feasible due to application real-time constraints, the user may take precautions to ensure that a write operation performed on a location in Y-data memory is not immediately followed by a DSP MAC-type instruction that performs a read operation of a location in Y-data memory. 2004 Microchip Technology Inc. Advance Information DS80178D-page 3 dsPIC30F2010 7. Module: Interrupting a REPEAT loop 6. Module: Interrupt Controller A specific write sequence for IPC2 (Interrupt Priority Control 2) SFR is required to prevent possible data corruption in the IEC2 (Interrupt Enable Control 2) SFR. Interrupts must be disabled during this IPC2 SFR write sequence. Work around An example of this write sequence is shown in Example 6. EXAMPLE 6: mov #IPC2, w0 mov #0x4444, w1 disi #2 mov mov w1, IPC2 #IPC2, w0 ;Point w0 to IPC2 ;Write data to go to IPC2 ;Disable interrupts for ;next two cycles ;Write the data to IPC2 ;Target w1 to keep IPC2 ;address on bus When coding in C, the write sequence shown above can be implemented using inline assembly instructions. The equivalent write sequence using the C30 compiler is shown in Example 7. EXAMPLE 7: asm volatile( "push.d w0\n\t" "mov #IPC2,w0\n\t" "mov #0x4444,w1\n\t" "disi #2\n\t" "mov w1, IPC2\n\t" "mov #IPC2, w0\n\t" "pop.d w0"); //Note: There are no commas between // the quoted strings in the code // segment above. When interrupt nesting is enabled (or NSTDIS (INTCON1) bit is `0'), the following sequence of events will lead to an Address Error Trap: 1. REPEAT-loop is active 2. An interrupt is generated during the execution of the REPEAT-loop. 3. The CPU executes the Interrupt Service Routine (ISR) of the source causing the interrupt. 4. Within the ISR, when the CPU is executing the first instruction cycle of the 3-cycle RETFIE (Return-from-interrupt) instruction, a second interrupt is generated by a source with a higher interrupt priority. Work around Processing of Interrupt Service Routines should be disabled while the RETFIE instruction is being executed. This may be accomplished in two different ways: 1. Place a DISI instruction immediately before the RETFIE instruction in all interrupt service routines of interrupt sources that may be interrupted by other higher priority interrupt sources (with priority levels 1 through 6). This is shown in Example 8 in the Timer1 ISR. In this example, a DISI instruction inhibits level 1 through level 6 interrupts for 2 instruction cycles, while the RETFIE instruction is executed. EXAMPLE 8: _T1Interrupt: ;Timer1 ISR PUSH W0 ;This line optional . BCLR IFS0, #T1IF POP W0 ;This line optional DISI #1 RETFIE ;Another interrupt occurs ;here and it is processed ;correctly 2. Immediately prior to executing the RETFIE instruction, increase the CPU priority level by modifying the IPL (SR) bits to `111' as shown in Example 9. This will disable all interrupts between priority levels 1 through 7. EXAMPLE 9: _T1Interrupt: ;Timer1 ISR PUSH W0 . BCLR IFS0, #T1IF MOV.B #0xE0, W0 MOV.B WREG, SR POP W0 RETFIE ;Another interrupt occurs ;here and it is processed ;correctly DS80178D-page 4 Advance Information 2004 Microchip Technology Inc. dsPIC30F2010 8. Module: 32-bit General Purpose Timers 10. Module: IPD Sleep Current The device exhibits IPD of approximately 100 µA. Pairs of 16-bit timers may be combined to form 32-bit timers. For example, Timer2 and Timer3 are combined into a single 32-bit timer. For this release of silicon, when a 32-bit timer is prescaled by ratios other than 1:1, unexpected results may occur. Work around None. The application may only use the 1:1 prescaler for 32-bit timers. Work around If the application does not use the on-chip A/D converter, it is possible to reduce the IPD to values below 0.1 µA. The following additional measures need to be taken in these circumstances: 1. 2. 9. Module: 10-bit A/D Converter Sequential Samping Sampling multiple channels sequentially using any conversion trigger source other than the autoconvert feature requires SAMC bits to be nonzero. Thus, if the following conditions are all satisfied, the module may not operate as specified: - Multiple S/H channels are sampled sequentially CHPS(ADCON2) is not equal to `00' and SIMSAM(ADCON1) = 0 - Auto-convert option is not chosen as the conversion trigger SSRC(ADCON1) is not equal to `111' - SAMC(ADCON3) is equal to `00000' In the application hardware, the VREF+/RB0 pin (Pin 2) on the dsPIC30F2010 should be connected to the circuit ground (GND). In the application software, the code sequence shown in Example 10 should be executed to bring the device into the power-saving Sleep mode. EXAMPLE 10: .include "p30f2010.inc" . BCLR ADCON1, #ADON ;Required code MOV #0x2000, W0 ;sequence for MOV W0, ADCON2 ;low power-down BCLR PMD1, #ADCMD ;current. PWRSAV #SLEEP_MODE ;Device enters ;SLEEP mode here APPENDIX A: REVISION HISTORY Revision A (1/2004) Original version of the document. Work around Set the value of the SAMC bits to anything other than `00000'. The module will now operate as specified. Revision B (2/2004) Document status was updated from "Confidential" to "Advance Information" designation. Clarifications/Corrections to dsPIC30F Datasheets were removed. Revision C (2/2004) Changes were made to the C code example under Errata #5. Revision D (4/2004) Errata #8, "Motor Control PWM: Configuration Fuse Bits" was removed. Added Errata #3 and #9. 2004 Microchip Technology Inc. Advance Information DS80178D-page 5 dsPIC30F2010 NOTES: DS80178D-page 6 Advance Information 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. 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