SP8855E DS4239 SP8852E SP8854E SP8855D SP8855 INPUT13 - Datasheet Archive

 

2.8GHz Parallel Load Professional Synthesiser Advance Information DS4239 The SP8855E is one of a family of parallel load

 

SP8855E SP8855E 2.8GHz Parallel Load Professional Synthesiser Advance Information DS4239 DS4239 The SP8855E SP8855E is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other devices in the series are the SP8852E SP8852E which is a fully programmable device requiring two 16 bit words to set the RF and reference counters, and the SP8854E SP8854E which has hard wired reference counter programming and requires a single bit word to program the RF divider. The SP8855E SP8855E replaces the existing SP8855D SP8855D. The SP8855E SP8855E is intended for applications where a fixed synthesiser frequency is required although it can also be used where frequency selection is set by switches. In general the device will be programmed by connecting the programming pins to either VCC or ground. Additional hard wired inputs can be used to control the Fpd and Fref outputs set the control direction of the loop and select the phase detector gain. Another input may be used to disable the phase detector output. The device is available in both plastic (HP) and ceramic (HC) J-leaded 44-lead chip carrier. Ambient temperature ranges available are shown in the ordering information. ISSUE 3.0 March 1999 PIN 1 HC44 OPTIONAL PIN 1 REFERENCE Features · 2.8GHz Operating Frequency (IG GRADE) · Single 5V Supply Operation · High Comparison Frequency 50MHz · High Gain Phase Detector 1mA/rad · Programmable Phase Detector Gain · Zero "Dead Band" Phase Detector · Wide range of RF and Reference Divide Ratios · Programming by Hard Wired Inputs · Low cost plastic package option · GPS HI-REL level a screened option HP44 Absolute Maximum Ratings Supply voltage Storage temperature Operating temperature Prescaler & reference Input Voltage Data Inputs Junction temperature -0.3V to 6V -65 °C to +150°C -55°C to +100°C 2.5V p-p VCC +0.3V VEE -0.3V + 175°C (HC package) + 150°C (HP package) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Input bus bit 10 Input bus bit 9 Input bus bit 8 Input bus bit 7 Input bus bit 6 Input bus bit 5 Input bus bit 4 Input bus bit 3 Input bus bit 2 Input bus bit 1 Input bus bit 0 0V (prescaler) RF input RF input VCC + 5V (prescaler) VEE 0V Lock detect output C-lock detect Rset Charge pump output Charge pump ref. Fref/Fpd enable Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Description Control Direction Fpd* Fref* +5V Ref. osc capacitor Ref in/XTAL Reference bit 9 Reference bit 8 Reference bit 7 Reference bit 6 Reference bit 5 Reference bit 4 Reference bit 3 Reference bit 2 Reference bit 1 Reference bit 0 Phase Detect Enable Phase Detect Gain 1 Phase Detect Gain 0 Input bus bit 13 Input bus bit 12 Input bus bit 11 *Fpd and Fref outputs are reversed using the Control Direction input. The table above is correct when pin 23 is high. Figure 1 - Pin connections - top view 2 26 +5V 26 VEE 0V 27 28 REFERENCE REFERENCE CRYSTAL CAPACITOR 0V PRESCALER RF INPUT Vcc + 5V PRESCALER 10 B2 9 10 BIT REFERENCE DIVIDER 3 BIT A COUNTER 11 B0 8 B3 7 6 3 2 Fref 11 BIT M COUNTER 5 4 Figure 2 - SP8855E SP8855E block diagram 38 37 36 35 34 33 32 31 30 29 BIT 0 BIT 9 REFERENCE DIVIDER PROGRAMMING ÷ 8/9 MODULS CONTROL RF DIVIDER PROGRAMMING 1 Fpd PHASE DETECTOR 39 41 40 23 25 22 24 18 20 21 17 19 PHASE DETECTOR ENABLE PHASE DETECTOR GAIN 0 PHASE DETECTOR GAIN 1 CONTROL DIRECTION Fpd / Fref ENABLE Fref * Fpd * C - LOCK DETECT LOCK DET O/P R set CHARGE PUMP REFERENCE CHARGE PUMP OUTPUT * Fpd and Fref outputs are reversed using the Control Direction input. Diagram is correct when pin 23 is high. 44 43 42 B13 SP8855E SP8855E Advance Information Advance Information SP8855E SP8855E PIN Description PIN Description 1,2,3,4,5,6,7,8,9,10,11,42,43,44 These pins are the data inputs used to set the RF divider ratio (M.N+A). Open circuit = 1 (high) on these pins. Inputs are transparent into the data buffers. 13, 14 (RF INPUT) Balanced inputs to the RF pre-amplifier. For single ended operation the signal is AC coupled into pin 13 with pin 14 AC decoupled to ground (or vice -versa). Pins 13 and 14 are internally DC biased. 17 (LOCK DETECT INPUT) A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give an external indication of phase lock. 18 (C-LOCK DETECT) A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indicator. 19 (Rset) An external resistor from Pin 19 to V CC sets the charge pump output current 20 (CP OUTPUT) The phase detector output is a single ended charge pump sourcing or sinking current to the inverting input of an external loop filter. 21 (CP REF) Connected to the non-inverting input of the loop filter to set the optimum DC bias. 22 (Fref /Fpd ENABLE Part of the data input bus. When this pin is logic HI the F ref and Fpd outputs are enabled. Open circuit = HI 23 (CONTROL DIRECTION) This pin controls charge pump output direction. For Pin 23 HI the output sinks current when F pd > Fref or when the RF phase leads Ref phase. For Pin 23 LO the relationship is reversed. (see table 2). Changing the state of pin 23 reverses the pins on which Fref and Fpd output occur. See pin 24 and Pin 25 below for details. Open circuit = HI. 24 = Fpd if Pin 23 is HI = Fref if Pin 23 is LO RF divider output pulses. Fpd = RF input frequency /(M.N+A). Pulse width = 8 RF input cycles (1 cycle of the divide by 8 prescaler output). 25 = Fref if Pin 223 is HI Reference divider output pulses. Fref = Reference input frequency/R. Pulse width = high period of Ref input. 27 (Reference Oscillator Capacitor) Leave open circuit if an external reference is used. See fig. 5 for typical connection for use as an onboard crystal oscillator. 28 (Ref IN/XTAL) This pin is the input buffer amplifier for an external reference signal. This amplifier provides the active element if an onboard crystal oscillator is used. 29,30,31,32,33,34,35,36,37,38 These pins set the Reference divider ratio R. Open circuit = HI. 39 (Phase Detector ENABLE) When this pin is HI the phase detector output is enable. Open circuit = HI. 40, 41 (PD Gain) These pins set the charge pump current multiplication factor (see table 1). Open circuit = HI. 3 SP8855E SP8855E Advance Information Electrical Characteristics Guaranteed over the full temperature and supply voltage range (unless otherwise stated) Temperature Tamb for IG parts -40°C and +85°, Temperature Tcase for Temperature Tamb for KG parts -55°C and +100°C, MA part -55°C and +125°C Supply Voltage = 4.75V and 5.25V Characteristics Pin Value Units Min RF input sensitivity Typ Max 180 Supply current15, 26 240 Conditions mA 13, 14 -5.0 +7.0 13,14,24 56 16383 Reference division ratio 28, 25 1 1023 Comparison frequency 28,24,25 RF division ratio dBm 100MHz to 2.8/2.7GHz See Fig. 3 50 Reference input frequency 28 Reference input voltage 28 630 100 10 1200 MHz MHz 2000 mV p-p Sine Wave 10-100MHz Reference division ratio 2 at frequencies >50MHz also see Note 1. Fref/F pd output voltage high 24, 25 - 0.8 Vwrt VCC 2.2K to 0V Fred/Fpd output voltage low 24, 25 - 1.4 Vwrt VCC 2.2K to 0V Lock detect output voltage 17 300 500 mV IOUT = 3mA Charge pump current at multiplication factor = 1 19,20,21 ±1.4 ±1.5 ±1.7 mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Charge pump current at multiplication factor = 1.5 19,20,21 ±2.0 ±2.3 ±2.5 mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Charge pump current at multiplication factor = 2.5 19,20,21 ±3.4 ±3.8 ±4.6 mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Charge pump current at multiplication factor = 4.0 19,20,21 ±5.4 ±6.1 ±6.5 mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Input bus high logic level 1-11, 22 23, 29-44 3.5 Input bus low logic level 1-11, 22 23,29-44 Input bus current source 1-11,22 23,29-44 Input bys current sink 1-11, 22 23,29-44 Up down current matching V 1 V µA VIN = 0V 10 µA VIN = VCC 20 ±5 % Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Charge pump reference voltage 21 VCC-0.5 V Ipin 19 =1.6mA current multiplication factor = 1 Charge pump reference voltage 21 Rset current 19 Rset Voltage 19 -200 VCC-1.6 V Ipin 19 =1.6mA current multiplication factor = 4 0.5 2 1.6 V mA See Note 2 Ipin 19 = 1.6mA Notes: 1. Lower reference frequencies may be used if slew rates are maintained. 2. Pin 19 current x multiplication factor must be less than 5mA if charge pump accuracy is to be maintained. 4 Advance Information SP8855E SP8855E TYPICAL OVERLOAD +20 +10 +7 OPERATING AREA FOR 'IG' PARTS ONLY GUARANTEED OPERTAING WINDOW -5 -10 -20 TYPICAL SENSITIVITY -30 2.7GHz 2.8GHz 2GHz 1GHz 100MHz 10GHz INPUT DRIVE REQUIREMENTS Figure 3 - SP8855E SP8855E +j1 +j0.5 +j2 Zo = 50 +j0.2 0 0.2 0.5 1 50MHz 1.1GHz 2.5GHz -j0.2 -j0.5 -j2 -j1 Figure 4 - R.F. input impedance 5 SP8855E SP8855E Advance Information +5V VCC * 40 41 42 1 2 3 4 5 6 43 REFERENCE COUNTER PROGRAMMING 1k 44 RF COUNTER PROGRAMMING VALUES DEPEND ON APPLICATION VCC 7 39 8 38 9 35 13 1n 36 11 12 VCO 37 10 33 34 14 32 15 31 16 30 17 APPLICATION USING CRYSTAL REFERENCE 29 LOOP FILTER * * 28 27 25 26 24 23 22 21 2k2 20 28 18 27 19 SP8855 SP8855 Fpd Fref * - 33p + 100p 10MHz CRYSTAL 1n 10n *100n 1µ +30V OP27 ETC 1n 10n 100n Ref in Figure 5 - Typical application diagram Description Prescaler and AM counter Phase Comparator and Charge pump The programmable divider chain is of AM counter construction and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which performs the bulk multi-modulus division. A programmable divider of this construction has a division ratio of MN+A and a minimum integer steppable division ratio of N(N-1), where N is the prescaler ratio. The SP8855E SP8855E has a digital phase/frequency comparator driving a charge pump with programmable current output. The charge pump current level at the minimum gain setting is approximately equal to the current fed into the Rset input pin 19 and can be increased by programming pins 40 and 41 according to Table 1 by up to 4 times. Programming The device is programmed by connecting the programming pins to either VCC or ground. The programming inputs will go high if left open circuit but for best noise immunity a wired connection to VCC is preferable. The programming inputs can be driven from TTL or CMOS logic levels if required. Reference input The reference source can be either driven from an external sine or square wave source of up to 100MHz or a crystal can be connected as shown in Fig. 5. 6 Pin 40 Pin 41 Current Multiplication Factor 0 0 1 1 0 1 0 1 1.0 1.5 2.5 4.0 Table 1 SP8855E SP8855E Advance Information Pin 19 current . VCC - 1.6V Rset Phase detector gain = Ipin 19 (mA) X multiplication factor mA/radian 2 To allow for control direction changes introduced by the design of the PLL, pin 23 can be programmed to reverse the control direction of the loop by transposing the Fpd and Fref connections. In order that any external phase detector will also be reversed by this function, the Fpd and Fref outputs are also interchanged as shown in Table 2. The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pumps output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pull-up resistor is used in place of the LED. A small capacitor connected from the C-lock detector pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. The phase detector can be disabled by pulling pin 39 to logic low. Output for RF Phase Lag Control direction pin 23 pin 20 1 Current Source 0 Current Sink 29 30 31 32 33 34 35 36 37 38 29 28 27 26 25 24 23 22 21 20 PIN TEN BIT REFERENCE COUNTER Table 2 REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION The Fpd and Fref signals to the phase detector are available on pin 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. When the Fpd/Fref outputs are to be used at high frequencies, an external pull down resistor of minimum value 330 may be used connected to ground to reduce the fall time of the output pulse. 40 41 2 3 4 5 6 7 8 9 10 11 213 212 211 210 29 42 43 44 1 28 27 26 25 24 23 22 21 20 M COUNTER PHASE DETECTOR GAIN CONTROL see Table 1 PIN 3 BIT A COUNTER REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION RF Figure 6 - Programming data format 7 SP8855E SP8855E Advance Information Vcc Vcc 40k 40k 325 325 4k 5k 5k RF INPUT13 INPUT13 500 INPUT 500 RF INPUT 14 50µA 3mA 0V 3k 0V Figure 7a - RF and reference divider programming bits, Fpd/Fref enable, control direction and phase detector gain control inputs Figure 7b - RF inputs C-LOCK DETECT (HIGH WHEN LOCKED) 18 Vcc 3k Vcc 2k5 2k5 3k LOW WHEN LOCKED 3k 50k 3k V REF 4.7V 17 LOCK DETECT OUTPUT 400µA 1k 100 100 100µA 20µA 11 0V 0V Figure 7c - Lock detect decouple Figure 7d - Lock detect output CHARGE PUMP OUTPUT R set REFERENCE Vcc 20 21 19 450 450 Vcc CHARGE PUMP CURRENT SOURCES 83 UP 83 Vcc DOWN 130 2mA Figure 7e - Rset pin 8 Figure 7f - Charge pump circuit Figure 7 - Interface circuit diagrams Advance Information SP8855E SP8855E Vcc 296 24, 25 Fpd, Fref, OUTPUTS 3.3mA 0V 3k 3k 40k OSCILLATOR OSCILLATOR CAPACITOR CRYSTAL 296 Vcc 296 40k 28 27 60k 60k 50µA 100µA Figure 7g - Fpd, and Fref outputs 50µA 100µA 0V 100µA Figure 7h - Reference oscillator Applications RF inputs RF Layout The prescaler has a differential input amplifier to improve input sensitivity. Generally the input drive will be single ended and the RF signal should be AC coupled to either of the inputs using a chip capacitor. The remaining input should be decoupled to ground , again using a chip capacitor. The inputs can be driven differentially but the input circuit should not provide DC path between inputs or to ground. The SP8855E SP8855E can operate with input frequencies up to 2.8GHz but to obtain optimum performance, good RF layout practices should be used. A suitable layout technique is to use double sided printed circuit board with through plated holes. Wherever possible the top surface on which the SP8855E SP8855E is mounted should be left as a continuous sheet of copper to form a low impedance earth plane. The ground pins 12 and 16 should be connected directly to the earth plane. Pins such as Vcc and the unused RF input should be decoupled with chip capacitors mounted as close to the device pin as possible with a direct connection to the earth plane, suitable values are 10nF for the power supplies and