DS3065W DS3065W-100 J-STD-020C DS1265W E99151 - Datasheet Archive
3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock The DS3065W consists of a static RAM, a nonvolatile (NV) controller, a year
Rev 0; 4/05 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock The DS3065W DS3065W consists of a static RAM, a nonvolatile (NV) controller, a year 2000-compliant real-time clock (RTC), and an internal rechargeable manganese lithium (ML) battery. These components are encased in a surface-mount module with a 256-ball BGA footprint. Whenever VCC is applied to the module, it recharges the ML battery, powers the clock and SRAM from the external power source, and allows the contents of the clock registers or SRAM to be modified. When VCC is powered down or out-of-tolerance, the controller writeprotects the memory contents and powers the clock and SRAM from the battery. The DS3065W DS3065W also contains a power-supply monitor output (RST), as well as a user-programmable interrupt output (IRQ/FT). Applications Features Single-Piece, Reflowable, 27mm x 27mm BGA Package Footprint Internal Manganese Lithium Battery and Charger Integrated Real-Time Clock Unconditionally Write-Protects the Clock and SRAM when VCC is Out-of-Tolerance Automatically Switches to Battery Supply when VCC Power Failures Occur Reset Output can be Used as a CPU Supervisor Interrupt Output can be Used as a CPU Watchdog Timer RAID Systems and Servers Gaming POS Terminals Fire Alarms Industrial Temperature Range (-40°C to + 85°C) Industrial Controllers PLCs UL Recognized Data-Acquisition Systems Routers/Switches Ordering Information PART DS3065W-100 DS3065W-100 TEMP RANGE PIN-PACKAGE SPEED SUPPLY VOLTAGE (%) -40°C to +85°C 256-ball 27mm x 27mm BGA Module 100ns 3.3V ±0.3V Typical Operating Circuit CE CE WR WE RD OE CS CS DS3065W DS3065W MICROPROCESSOR OR DSP DATA 8 BITS DQ07 ADDRESS 20 BITS A019 INT IRQ/FT INT 1024k x 8 NV SRAM AND RTC RST Pin Configuration appears at end of data sheet. _ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 DS3065W DS3065W General Description DS3065W DS3065W 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground.-0.3V to +4.6V Operating Temperature Range .-40°C to +85°C Storage Temperature Range .-40°C to +85°C Soldering Temperature Range .See IPC/JEDEC J-STD-020C J-STD-020C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP 3.3 MAX UNITS Supply Voltage VCC 3.0 3.6 V Input Logic 1 VIH 2.2 VCC V Input Logic 0 VIL 0.0 0.4 V MAX UNITS µA DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±0.3V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP Input Leakage Current IIL -1.0 +1.0 I/O Leakage Current IIO CE = CS = VCC -1.0 +1.0 Output-Current High IOH At 2.4V -1.0 mA IOL At 0.4V 2.0 mA At 0.4V (Note 1) 8.0 mA IOL IRQ/FT At 0.4V (Note 1) 7.0 mA Output-Current Low Output-Current Low RST Output-Current Low IRQ/FT Standby Current Operating Current Write Protection Voltage IOL RST ICCS1 CE = CS = 2.2V 0.5 7 ICCS2 CE = CS = VCC - 0.2V 0.2 5 ICCO1 tRC = 200ns, outputs open µA mA 50 mA 2.8 VTP 2.9 3.0 V MIN TYP MAX UNITS PIN CAPACITANCE (TA = +25°C.) PARAMETER Input Capacitance Input/Output Capacitance 2 SYMBOL CONDITIONS CIN Not production tested 15 pF COUT Not production tested 15 pF _ 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock (VCC = 3.3V ±0.3V, TA = -40°C to +85°C.) PARAMETER Read Cycle Time Access Time OE to Output Valid SYMBOL CONDITIONS tRC DS3065W-100 DS3065W-100 MIN MAX 100 UNITS ns tACC 100 ns tOE 50 ns ns RTC OE to Output Valid tOEC 60 CE or CS to Output Valid tCO 100 OE or CE or CS to Output Active tCOE Output High Impedance from Deselection tOD Output Hold from Address tWP Address Setup Time 40 tAW ns ns (Note 2) tWC Write Pulse Width 5 tOH Write Cycle Time (Note 2) ns 5 ns 100 ns 75 ns 0 ns (Note 3) tWR1 (Note 4) 5 tWR2 (Note 5) 20 Output High Impedance from WE tODW (Note 2) Output Active from WE tOEW (Note 2) 5 ns tDS (Note 6) 40 ns tDH1 (Note 4) 0 tDH2 (Note 5) 20 Write Recovery Time Data Setup Time Data Hold Time Chip-to-Chip Setup Time ns 40 tCCS ns ns 40 ns POWER-DOWN/POWER-UP TIMING (TA = -40°C to +85°C.) PARAMETER VCC Fail Detect to CE, CS, and WE Inactive SYMBOL tPD CONDITIONS MIN TYP UNITS 1.5 (Note 7) MAX µs VCC Slew from VTP to 0V tF 150 µs VCC Slew from 0V to VTP tR 150 µs VCC Valid to CE, CS, and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms VCC Fail Detect to RST Active tRPD (Note 1) VCC Valid to RST Inactive tRPU (Note 1) 3.0 40 350 µs 525 ms _ 3 DS3065W DS3065W AC ELECTRICAL CHARACTERISTICS DS3065W DS3065W 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock DATA RETENTION (TA = +25°C.) PARAMETER Expected Data-Retention Time (Per Charge) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: 4 SYMBOL tDR CONDITIONS (Notes 7, 8) MIN TYP 2 3 MAX UNITS years IRQ/FT and RST are open-drain outputs and cannot source current. External pullup resistors should be connected to these pins to realize a logic-high level. These parameters are sampled with a 5pF load and are not 100% tested. tWP is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. tWP is measured from the latter of the two related edges going low to the earlier of the two related edges going high. tWR1 and tDH1 are measured from WE going high. tWR2 and tDH2 are measured from CE going high for SRAM writes or CS going high for RTC writes. tDS is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for RTC writes. In a power-down condition, the voltage on any pin may not exceed the voltage on VCC. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. Minimum expected data-retention time is based upon a maximum of two +230°C convection reflow exposures, followed by a fully charged cell. Full charge occurs with the initial application of VCC for a minimum of 96 hours. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. WE is high for any read cycle. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. If the CE or CS low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output buffers remain in a high-impedance state during this period. _ 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock tRC VIH VIH VIH VIL ADDRESSES VIL VIL tOH tACC CE OR CS VIH VIH tCO VIL tOEC tOE VIH OE tOD VIH VIL tOD tCOE tCOE DOUT VOH VOL OUTPUT DATA VALID VOH VOL (SEE NOTE 9.) _ 5 DS3065W DS3065W Read Cycle 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock DS3065W DS3065W Write Cycle 1 tWC ADDRESSES VIH VIL VIH VIL VIH VIL tAW CE OR CS VIL VIL tWP WE VIH tWR1 VIL VIH VIL tOEW tODW HIGH IMPEDANCE DOUT tDS tDH1 VIH VIH DIN DATA IN STABLE VIL VIL (SEE NOTES 2, 3, 4, 6, 1013.) Write Cycle 2 tWC ADDRESSES VIH VIL tAW CE OR CS VIH VIH VIL VIL tWR2 tWP VIH VIH VIL VIL VIL VIH WE VIL VIL tODW tCOE DOUT tDH2 tDS VIH VIH DIN DATA IN STABLE VIL (SEE NOTES 2, 3, 5, 6, 1013.) 6 _ VIL 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock VCC VTP tDR ~2.5V tF tR tREC tPD tPU SLEWS WITH VCC CE, WE AND CS VIH BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY tRPU tRPD RST VOL VOL (SEE NOTES 1, 7.) Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (mA) 5 4 5MHz ADDRESSACTIVATED 100% DUTY CYCLE 3 2 1MHz CE-ACTIVATED 50% DUTY CYCLE 0 3.0 3.1 3.2 3.3 VCC (V) 900 800 700 500 3.4 3.5 3.6 8 DS3065W DS3065W toc03 VCC = CE = 3.3V, VBAT = VCHARGE, OSC = ON 600 1MHz ADDRESSACTIVATED 100% DUTY CYCLE 1 DS3065W DS3065W toc02 5MHz CE-ACTIVATED 50% DUTY CYCLE SUPPLY CURRENT (µA) TA = +25°C 6 1000 DS3065W DS3065W toc01 7 BATTERY CHARGER CURRENT vs. BATTERY VOLTAGE BATTERY CHARGER CURRENT, ICHARGE (mA) SUPPLY CURRENT vs. OPERATING FREQUENCY VCC = CE = 3.3V 7 6 5 4 3 2 1 VCHARGE = 2.86V 0 3.0 3.1 3.2 3.3 VCC (V) 3.4 3.5 3.6 0 0.2 0.4 0.6 0.8 1.0 DELTA V BELOW VCHARGE (V) _ 7 DS3065W DS3065W Power-Down/Power-Up Condition Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) WRITE PROTECTION VOLTAGE vs. TEMPERATURE WRITE PROTECT, VTP (V) 0.5 0 -0.5 3.5 VCC = 3.3V 3.3 2.95 VOH (V) VCC = 3.3V, VBAT = VCHARGE DS3065W DS3065W toc05 3.00 DS3065W DS3065W toc04 1.0 DQ OUTPUT-VOLTAGE HIGH vs. DQ OUTPUT-CURRENT HIGH 2.90 -40 -15 10 35 2.85 2.7 2.5 -40 85 60 3.1 2.9 2.80 -1.0 DS3065W DS3065W toc06 VCHARGE PERCENT CHANGE vs. TEMPERATURE VCHARGE PERCENT CHANGE FROM 25°C (%) -15 10 35 85 60 -5 -4 -3 TEMPERATURE (°C) TEMPERATURE (°C) -2 IOH (mA) DQ OUTPUT-VOLTAGE LOW vs. DQ OUTPUT-CURRENT LOW IRQ/FT OUTPUT-VOLTAGE LOW vs. OUTPUT-CURRENT LOW VCC = 3.3V DS3065W DS3065W toc08 6 DS3065W DS3065W toc07 4 5 3 VOL (V) VOL (V) 4 2 3 2 1 1 0 0 1 2 3 4 0 5 0 5 10 20 15 IOL (mA) IOL (mA) RST OUTPUT-VOLTAGE LOW vs. OUTPUT-CURRENT LOW RST VOLTAGE vs. VCC DURING POWER-UP 4 3 2 1 TA = +25°C 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0 5 10 15 20 0 0.5 1.0 IOL (mA) 8 DS3065W DS3065W toc10 5 4.0 RST VOLTAGE W/PULLUP RESISTOR (V) DS3065W DS3065W toc09 6 VOL (V) DS3065W DS3065W 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock _ 1.5 2.0 2.5 VCC POWER-UP (V) 3.0 3.5 4.0 -1 0 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock BALLS A1, A2, A3, A4 B1, B2, B3, B4 NAME GND DESCRIPTION Ground Interrupt/Frequency Test IRQ/FT Output BALLS NAME DESCRIPTION N17, N18, N19, N20 A5 Address Input 5 P17, P18, P19, P20 A4 Address Input 4 R17, R18, R19, R20 A3 Address Input 3 C1, C2, C3, C4 A15 Address Input 15 T17, T18, T19, T20 A2 Address Input 2 D1, D2, D3, D4 A16 Address Input 16 U17, U18, U19, U20 A1 Address Input 1 E1, E2, E3, E4 RST Reset Output V17, V18, V19, V20 A0 Address Input 0 F1, F2, F3, F4 VCC Supply Voltage W17, W18, W19, W20 GND G1, G2, G3, G4 WE Write Enable Input Y17, Y18, Y19, Y20 GND Ground H1, H2, H3, H4 OE Output Enable Input A5, B5, C5, D5 N.C. No Connection CE J1, J2, J3, J4 Ground SRAM Chip Enable Input A6, B6, C6, D6 N.C. No Connection K1, K2, K3, K4 DQ7 Data Input/Output 7 A7, B7, C7, D7 N.C. No Connection L1, L2, L3, L4 DQ6 Data Input/Output 6 A8, B8, C8, D8 N.C. No Connection M1, M2, M3, M4 DQ5 Data Input/Output 5 A9, B9, C9, D9 N.C. No Connection N1, N2, N3, N4 DQ4 Data Input/Output 4 A10, B10, C10, D10 VCC Supply Voltage P1, P2, P3, P4 DQ3 Data Input/Output 3 A11, B11, C11, D11 N.C. No Connection R1, R2, R3, R4 DQ2 Data Input/Output 2 A12, B12, C12, D12 N.C. No Connection T1, T2, T3, T4 DQ1 Data Input/Output 1 A13, B13, C13, D13 N.C. No Connection U1, U2, U3, U4 DQ0 Data Input/Output 0 A14, B14, C14, D14 N.C. No Connection V1, V2, V3, V4 GND Ground A15, B15, C15, D15 A19 Address Input 19 W1, W2, W3, W4 GND Ground A16, B16, C16, D16 N.C. No Connection Y1, Y2, Y3, Y4 GND Ground U5, V5, W5, Y5 CS A17, A18, A19, A20 GND Ground U6, V6, W6, Y6 N.C. No Connection B17, B18, B19, B20 A18 Address Input 18 U7, V7, W7, Y7 N.C. No Connection C17,C18,C19, C20 A17 Address Input 17 U8, V8, W8, Y8 N.C. No Connection D17, D18, D19, D20 A14 Address Input 14 U9, V9, W9, Y9 N.C. No Connection E17, E18, E19, E20 A13 Address Input 13 U10, V10, W10, Y10 N.C. No Connection F17, F18, F19, F20 A12 Address Input 12 U11, V11, W11, Y11 N.C. No Connection G17, G18, G19, G20 A11 Address Input 11 U12, V12, W12, Y12 N.C. No Connection H17, H18, H19, H20 A10 Address Input 10 U13, V13, W13, Y13 N.C. No Connection J17, J18, J19, J20 A9 Address Input 9 U14, V14, W14, Y14 N.C. No Connection K17, K18, K19, K20 A8 Address Input 8 U15, V15, W15, Y15 N.C. No Connection L17, L18, L19, L20 A7 Address Input 7 U16, V16, W16, Y16 N.C. No Connection M17, M18, M19, M20 A6 Address Input 6 RTC Chip Select _ 9 DS3065W DS3065W Pin Description 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock DS3065W DS3065W Functional Diagram 32.768kHz IRQ/FT REAL-TIME CLOCK RST CS CS A0-A3 WE OE CE DELAY TIMING CIRCUITRY VTP REF CHARGER CURRENT-LIMITING RESISTOR UNINTERRUPTED POWER SUPPLY FOR THE SRAM AND RTC VCC VCC CE OE WE VSW REF SRAM REDUNDANT LOGIC ML GND CURRENT-LIMITING RESISTOR REDUNDANT SERIES FET BATTERY-CHARGING/SHORTING PROTECTION CIRCUITRY (U.L. RECOGNIZED) OE WE A0A19 10 _ DS3065W DS3065W DQ07 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock The DS3065W DS3065W is an 8Mb (1024k x 8 bits) fully static, NV memory similar in function and organization to the DS1265W DS1265W NV SRAM, but also containing an RTC and rechargeable ML battery. The DS3065W DS3065W NV SRAM constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit to the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing. This device can be used in place of SRAM, EEPROM, or flash components. User access to either the SRAM or the real-time clock registers is accomplished with a byte-wide interface and discrete control inputs, allowing for a direct interface to many 3.3V microprocessor devices. The DS3065W DS3065W RTC contains a full-function, year 2000compliant (Y2KC) clock/calendar with an RTC alarm, watchdog timer, battery monitor, and power monitor. RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in a 24-hour BCD format. Corrections for day of the month and leap year are made automatically. The DS3065W DS3065W RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is on, the internal registers are contin- ually updated, regardless of the state of the external registers, assuring that accurate RTC information is always maintained. The DS3065W DS3065W contains interrupt (IRQ/FT) and reset (RST) outputs, which can be used to control CPU activity. The IRQ/FT interrupt output can be used to generate an external interrupt when the RTC register values match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wake-up. The IRQ/FT output can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt can be activated if the correct activity is not detected. The RST output can be used to detect a system power-down or failure and hold the CPU in a safe state until normal power returns. The DS3065W DS3065W constantly monitors the voltage of the internal battery. The battery-low flag (BLF) in the RTC FLAGS register is not writeable and should always be a 0 when read. Should a 1 ever be present, the battery voltage is below 2V and the contents of the clock and SRAM are questionable. The DS3065W DS3065W module is constructed on a standard 256ball, 27mm x 27mm BGA substrate. Unlike other surface-mount NV memory modules that require the battery to be removable for soldering, the internal ML battery can tolerate exposure to convection reflow soldering temperatures, allowing this single-piece component to be handled with standard BGA assembly techniques. Table 1. RTC/Memory Operational Truth Table CS WE CE OE MODE ICC OUTPUTS 0 1 1 0 RTC Read Active Active 0 1 1 1 RTC Read Active High Impedance 0 0 1 X RTC Write Active High Impedance 1 1 0 0 SRAM Read Active Active 1 1 0 1 SRAM Read Active High Impedance 1 0 0 X SRAM Write Active High Impedance 1 X 1 X Standby Standby High Impedance 0 X 0 X Invalid (1) Active Invalid X = Don't care. (1) = See Figure 4. _ 11 DS3065W DS3065W Detailed Description DS3065W DS3065W 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock SRAM Read Mode SRAM Write Mode The DS3065W DS3065W executes an SRAM read cycle whenever CS (RTC chip select) and WE (write enable) are inactive (high) and CE (SRAM chip enable) is active (low). The unique address specified by the 20 address inputs (A0 to A19) defines which of the 1,048,576 bytes of SRAM data is to be accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable, providing that CE and OE (output enable) access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. The DS3065W DS3065W executes an SRAM write cycle whenever CS is inactive (high) and the CE and WE signals are active (low) after address inputs are stable. The lateroccurring falling edge of CE or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The CS and OE control signal should be kept inactive (high) during SRAM write cycles to avoid bus contention. However, if the output drivers have been enabled (CE and OE active) then WE disables the outputs in tODW from its falling edge. Clock Operations Table 2. RTC Register Map ADDRESS DATA B7 B6 xxxxEh X X xxxxDh X X xxxxCh X FT xxxxBh X X xxxxFh B5 B4 B3 B2 B1 10 YEAR B0 FUNCTION/RANGE YEAR X YEAR 0099 MONTH MONTH 0112 DATE 10 M DATE 0131 10 DATE X X X DAY 10 HOUR DAY 0107 HOUR HOUR 0023 xxxxAh X 10 MINUTES MINUTES MINUTES 0059 xxxx9h OSC 10 SECONDS SECONDS SECONDS 0059 xxxx8h W R CENTURY CONTROL 0039 xxxx7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 WATCHDOG xxxx6h AE Y ABE Y Y Y Y Y INTERRUPTS xxxx5h AM4 Y 10 DATE DATE ALARM DATE 0131 xxxx4h AM3 Y 10 HOURS HOURS ALARM HOURS 0023 xxxx3h AM2 10 MINUTES MINUTES ALARM MINUTES 0059 xxxx2h AM1 10 SECONDS SECONDS ALARM SECONDS 0059 10 CENTURY xxxx1h Y Y Y Y Y Y Y Y UNUSED xxxx0h WF AF 0 BLF 0 0 0 0 FLAGS x = Don't care address bits. X = Unused. Read/writeable under write and read bit control. FT = Frequency test bit. OSC = Oscillator start/stop bit. W = Write bit. R = Read bit. WDS = Watchdog steering bit. BMB0BMB4 = Watchdog multiplier bits. RB0, RB1 = Watchdog resolution bits. 12 AE = Alarm flag enable. Y = Unused. Read/writeable without write and read bit control. ABE = Alarm in backup mode enable. AM1AM4 = Alarm mask bits. WF = Watchdog flag. AF = Alarm flag. 0 = Reads as a 0 and cannot be changed. BLF = Battery low flag. _ 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock RTC Write Mode The DS3065W DS3065W executes an RTC write cycle whenever CE is inactive (high) and the CS and WE signals are active (low) after address inputs are stable. The lateroccurring falling edge of CS or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CS or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The CE and OE control signals should be kept inactive (high) during RTC write cycles to avoid bus contention. However, if the output drivers have been enabled (CS and OE active) then WE disables the outputs in tODW from its falling edge. Clock Oscillator Mode The oscillator can be turned off to minimize battery current drain. The OSC bit is the MSB of the SECONDS register, and must be initialized to a 0 to start the oscillator upon first power application. The OSC bit is factory set to a 1 prior to shipment. Oscillator operation and frequency can be verified by setting the FT bit to a 1 and monitoring the IRQ/FT output for 512Hz. Reading the Clock When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state, allowing the data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted by writing a 1 to the read bit (R). As long as a 1 remains in the R bit, updating is inhibited. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers resume within 1 second after the R bit is set to a 0 for a minimum of 500µs. The R bit must be a 0 for a minimum of 500µs to ensure the external registers have fully updated. Setting the Clock As with a clock read, it is also recommended to halt updates prior to setting new time values. Setting the write bit (W) to a 1 halts updates of the external RTC registers 8h to Fh. After setting the W bit to a 1, the RTC registers can be loaded with the desired count (day, date, and time) in BCD format. Setting the W bit to a 0 then transfers the values written to the internal registers and allows normal clock operation to resume. Frequency Test Mode The DS3065W DS3065W frequency test mode uses the IRQ/FT open-drain output. With the oscillator running, the IRQ/FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the watchdogenable bit (WDS) is a 1 or the WATCHDOG register is written to 00h (FT · AE · (WDS + WATCHDOG). The IRQ/FT output and the frequency test mode can be used to measure the actual frequency of the 32.768kHz RTC oscillator. The FT bit is reset to a 0 on power-up. Using the Clock Alarm The alarm settings and control for the DS3065W DS3065W reside within RTC registers 2h5h. The INTERRUPTS register (6h) contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE). The AE and ABE bits must be set as described below for the IRQ/FT output to be activated when an alarm match occurs. The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS3065W DS3065W is in the Data Retention Mode to serve as a system wake-up. Alarm mask bits AM1 to AM4 control the alarm mode (see Table 3). Configurations not listed in the table will default to the once-per-second mode to notify the user of an incorrect alarm setting. _ 13 DS3065W DS3065W RTC Read Mode The DS3065W DS3065W executes an RTC read cycle whenever CE (SRAM chip enable) and WE (write enable) are inactive (high) and CS (RTC chip select) is active (low). The least significant 4 address inputs (A0 to A3) define which of the 16 RTC registers is to be accessed (see Table 2). Valid data is available to the eight data output drivers within tACC (access time) after the last address input signal is stable, providing that CS and OE (output enable) access times are also satisfied. If CS and OE access times are not satisfied, then data access must be measured from the later occurring signal (CS or OE) and the limiting parameter is either tCO for CS or tOEC for OE rather than address access. DS3065W DS3065W 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock Table 3. Alarm Mask Bits AM4 AM3 AM2 AM1 1 1 1 1 Once per second 1 1 1 0 When seconds match 1 1 0 0 When minutes and seconds match 1 0 0 0 When hours, minutes, and seconds match 0 0 0 0 When date, hours, minutes, and seconds match When the RTC register values match alarm register settings, the alarm flag (AF) is set to a 1. If AE is also a 1, the alarm condition activates the IRQ/FT output. When CS is active, the IRQ/FT signal can be cleared by holding the FLAGS register address stable for tRC and forcing either OE or WE active (see Figure 1). The flag does not change state until the end of the read/write cycle and after the IRQ/FT signal has deasserted. To avoid inadvertently clearing the IRQ/FT signal while preparing for subsequent write/read cycles at other register addresses, assure that tAW is met for that subsequent address (see Figure 2). ALARM RATE The IRQ/FT output can also be activated during battery backup mode. The IRQ/FT goes low if an alarm occurs and both AE and ABE are set to 1. The AE and ABE bits are reset to 0 during the power-up transition, but an alarm generated during power-up will set AF to a 1. Therefore, the AF bit can be read after system powerup to determine if an alarm was generated during the power-up sequence. Figure 3 illustrates alarm timing during battery backup mode and power-up states. CE WE OR OE CS tRC MAX A0A3 ADDRESS 0h IRQ/FT Figure 1. Clearing Active IRQ Waveforms 14 _ HIGH IMPEDANCE 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock DS3065W DS3065W CE tAS INTENTIONAL WRITE OR READ AT ADDRESS Xh INADVERTENT WRITE OR READ OF RTC FLAGS REGISTER WILL RESET IRQ/FT WE OR OE CS A0A3 ADDRESS 0h ADDRESS Xh HIGH IMPEDANCE IRQ/FT Figure 2. Prevent Accidental Clearing of IRQ Waveforms VTP VCC ABE, AE AF IRQ/FT HIGH IMPEDANCE HIGH IMPEDANCE Figure 3. Battery Back-up Mode Alarm Waveforms _ 15 DS3065W DS3065W 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock Using the Watchdog Timer The watchdog timer can be used to detect an out-ofcontrol processor. The user programs the watchdog timer by setting the desired timeout delay into the WATCHDOG register. The five high-order WATCHDOG register bits store a binary multiplier and the two lowerorder WATCHDOG bits select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The watchdog timeout value is then determined by multiplication of the 5-bit multiplier value with the 2-bit resolution value. (For example: writing 00001110 (0Eh) into the WATCHDOG register = 3 x 1 second, or 3 seconds.) If the processor does not reset the timer within the specified period, the watchdog flag (WF) is set to a 1 and a processor interrupt is generated and stays active until either WF is read or the WATCHDOG register is read or written. The MSB of the WATCHDOG register is the watchdog steering bit (WDS). When WDS is set to a 0, the watchdog activates the IRQ/FT output when the watchdog times out. WDS should not be written to a 1, and should be initialized to a 0 if the watchdog function is enabled. The watchdog timer resets when the processor performs a read or write of the WATCHDOG register. The timeout period then starts over. The watchdog timer is disabled by writing a value of 00h to the WATCHDOG register. The watchdog function is automatically disabled upon power-up and the WATCHDOG register is cleared to 00h. Power-On Default States Upon each application of power to the device, the following register bits are automatically set to 0: WDS = 0, BMB0BMB4 = 0, RB0, RB1 = 0, AE = 0, ABE = 0. All other RTC bits are undefined. Data-Retention Mode The DS3065W DS3065W provides full functional capability for VCC greater than 3.0V and write-protects by 2.8V. Data is maintained in the absence of VCC without additional support circuitry. The NV SRAM constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write-protects itself. All inputs become don't care, and all data outputs become high impedance. As VCC falls below approximately 2.5V (VSW), the power-switching circuit connects the lithium energy source to the clock and SRAM to maintain time and retain data. During power-up, when VCC rises above VSW, the power-switching circuit connects external VCC to the clock and SRAM, and disconnects the lithium 16 energy source. Normal clock or SRAM operation can resume after VCC exceeds VTP for a minimum duration of tREC. Battery Charging When VCC is greater than VTP an internal regulator will charge the battery. The UL-approved charger circuit includes short-circuit protection and a temperature-stabilized voltage reference for on-demand charging of the internal battery. Typical data retention expectations greater than 2 years per charge cycle are achievable. A maximum of 96 hours of charging time is required to fully charge a depleted battery. System Power Monitoring When the external VCC supply falls below the selected out-of-tolerance trip point, the output RST is forced active (low). Once active, the RST is held active until the VCC supply has fallen below that of the internal battery. On power-up, the RST output is held active until the external supply is greater than the selected trip point and one reset timeout period (tRPU) has elapsed. This is sufficiently longer than tREC to ensure that the RTC and SRAM are ready for access by the microprocessor. Freshness Seal and Shipping The DS3065W DS3065W is shipped from Dallas Semiconductor with the RTC oscillator disabled and the lithium battery electrically disconnected, guaranteeing that no battery capacity has been consumed during transit or storage. As shipped, the lithium battery is ~60% charged, and no pre-assembly charging operations should be attempted. When VCC is first applied at a level greater than VTP, the lithium battery is enabled for backup operation. The user is required to enable the oscillator (MSB of SECONDS register) and initialize the required RTC registers for proper timekeeping operation. A 96 hour initial battery charge time is recommended for new system installations. Applications Information Power-Supply Decoupling To achieve the best results when using the DS3065W DS3065W, assure that all VCC and GND balls are connected and decouple the power supply with a 0.1µF capacitor. Use a high-quality, ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. _ 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock Using the Open-Drain IRQ/FT and RST Outputs The IRQ/FT and RST outputs are open drain, and therefore require pullup resistors to realize a high logic output level. Pullup resistor values between 1k and 10k are typical. Battery Charging/Lifetime The DS3065W DS3065W charges an ML battery to maximum capacity in approximately 96 hours of operation when VCC is greater than VTP. Once the battery is charged, its lifetime depends primarily on the VCC duty cycle. The DS3065W DS3065W can maintain data from a single, initial charge for up to 2 years. Once recharged, this deepdischarge cycle can be repeated for up to 20 times, producing a worst-case service life of 40 years. More typical duty cycles are of shorter duration, enabling the DS3065W DS3065W to be charged hundreds of times, and extending the service life well beyond 40 years. Recommended Cleaning Procedures DS3065W DS3065W Avoiding Data Bus Contention Care should be taken to avoid simultaneous access of the SRAM and RTC devices (see Figure 4). Any chipenable overlap violates tCCS and can result in invalid and unpredictable behavior. Recommended Reflow Temperature Profile Sn-Pb EUTECTIC ASSEMBLY PROFILE FEATURE Average ramp-up rate (TL to TP) 3°C/second max Preheat - Temperature min (TSmin) - Temperature max (TSmax) - Time (min to max) (ts) 100°C 150°C 60 to 120 seconds TSmax to TL - Ramp-up rate Time maintained above: - Temperature (TL) - Time (tL) 183°C 60 to 150 seconds Peak temperature (TP) 225 +0/-5°C Time within 5°C of actual peak temperature (TP) 10 to 30 seconds Ramp-down rate 6°C/second max Time 25°C to peak temperature 6 minutes max Note: All temperatures refer to topside of the package, measured on the package body surface. The DS3065W DS3065W can be cleaned using aqueous-based cleaning solutions. No special precautions are needed when cleaning boards containing a DS3065W DS3065W module. Removal of the topside label violates the environmental integrity of the package and voids the warranty of the product. VIH CE VIH tCCS tCCS VIH VIH CS Figure 4. SRAM/RTC Data Bus Control _ 17 Pin Configuration TOP VIEW 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 9 1 8 2 0 D A16 A14 D E RST A13 E F VCC A12 F G WE A11 G H OE A10 H J CE A9 J K DQ7 A8 K L DQ6 A7 L M DQ5 A6 M N DQ4 A5 N P DQ3 A4 P R DQ2 A3 R T DQ1 A2 T U DQ0 A1 U V GND A0 V W GND GND W Y GND GND Y 1 2 N.C. C A19 A17 N.C. A15 N.C. C N.C. B N.C. A18 VCC IRQ/FT N.C. B N.C. A N.C. GND N.C. GND N.C. A 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. DS3065W DS3065W CS DS3065W DS3065W 3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock 1 6 1 7 1 8 1 9 2 0 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) DS3065W DS3065W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151 E99151. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 _Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation.