DS207 PCI64 PCI32 PCI32/33 XCV300EBG432-6C XCV1000EFG680-6C

LogiCORE PCI Interface v3.0 DS207 April 26, 2004 0 0 Product Specification v3.0.128 Introduction With the Xilinx LogiCORETM PCI

0 LogiCORE PCI Interface v3.0 DS207 DS207 April 26, 2004 0 0 Product Specification v3.0.128 Introduction With the Xilinx LogiCORETM PCI Interface, a designer can build a customized PCI 2.3-compliant core with the highest possible sustained performance of 528 MB/sec. LogiCORE Facts PCI64 PCI64 Resource Utilization(1) Slice Four Input LUTs Features 724 Slice Flip-Flops 732 · Fully PCI 2.3-compliant core, 64/32-bit, 66/33 MHz interface IOB Flip-Flops 176 · Customizable, programmable, single-chip solution IOBs 89 · Predefined implementation for predictable timing TBUFs 352(10) · Incorporates Xilinx Smart-IPTM technology · 3.3V operation at 0-66 MHz GCLKs 1(2) · 5.0V operation at 0-33 MHz · Fully verified design tested with Xilinx proprietary testbench and hardware · Available for configuration and download on the web: PCI32 PCI32 Resource Utilization(1) Slice Four Input LUTs 553 Slice Flip-Flops 566 - Web-based configuration and download tool IOB Flip-Flops 97 - Web-based user constraint file generator tool IOBs 50 · CardBus compliant · Supported initiator functions: - · Interrupt acknowledge, special cycles 1(2) Memory read, memory write, MRM, MRL - 288(10) GCLKs Configuration read, configuration write - TBUFs I/O read, I/O write Provided with Core Documentation PCI Design Guide PCI Implementation Guide Supported target functions: Design File Formats - Type 0 configuration space header - Up to three base address registers (MEM or I/O with adjustable block size from 16 bytes to 2 GB) - Medium decode speed - Parity generation, parity error detection - Configuration read, configuration write - Memory read, memory write, MRM, MRL - Interrupt acknowledge - I/O read, I/O write - Verilog/VHDL Simulation Model NGO Netlist Target abort, target retry, target disconnect Constraints Files User Constraints File (UCF) Guide File (NCD) Example Design Verilog/VHDL Example Design Xilinx Tools v6.2i SP2 © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS207 DS207 April 26, 2004 Product Specification v3.0.128 www.xilinx.com 1-800-255-7778 1 LogiCORE PCI Interface v3.0 Design Tool Requirements Tested Entry and Verification Tools(3) PCI32/33 PCI32/33 3.3V, 5.0V 3.3V only Virtex-E XCV300EBG432-6C XCV300EBG432-6C 3.3V only Virtex-E XCV1000EFG680-6C XCV1000EFG680-6C 3.3V only Virtex-II XC2V1000FG456-4C/I/M XC2V1000FG456-4C/I/M 3.3V only Virtex-II Pro XC2VP7FF672-5C/I XC2VP7FF672-5C/I 3.3V only Spartan-II XC2S30PQ208-5C XC2S30PQ208-5C Supported Devices PCI64/66 PCI64/66 3.3V, 5.0V Virtex-E XCV100EBG352-6C XCV100EBG352-6C Synplicity Synplify Synopsys FPGA Express Exemplar Leonardo Spectrum Xilinx XST(4) Cadence Verilog XL Model Technology ModelSim Virtex XCV300BG432-5C XCV300BG432-5C Virtex XCV1000FG680-5C XCV1000FG680-5C 3.3V, 5.0V VirtexTM XCV300BG432-6C XCV300BG432-6C 3.3V only Spartan-II XC2S50PQ208-5C XC2S50PQ208-5C 3.3V, 5.0V Virtex XCV1000FG680-6C XCV1000FG680-6C 3.3V only Spartan-II XC2S100PQ208-5C XC2S100PQ208-5C 3.3V, 5.0V Virtex-E XCV300EBG432-6C XCV300EBG432-6C Spartan-II XC2S150PQ208-5C XC2S150PQ208-5C 3.3V, 5.0V 3.3V only Spartan-II XC2S200PQ208-5C XC2S200PQ208-5C 3.3V, 5.0V Virtex-II TM XC2V1000FG456-5C/I/M XC2V1000FG456-5C/I/M 3.3V only Spartan-IIE XC2S50EPQ208-6C XC2S50EPQ208-6C 3.3V only Virtex-II ProTM XC2VP7FF672-6C/I XC2VP7FF672-6C/I 3.3V only Spartan-IIE XC2S100EPQ208-6C XC2S100EPQ208-6C 3.3V only Virtex-II Pro XC2VP20FF1152-6C/I XC2VP20FF1152-6C/I 3.3V only Spartan-IIE XC2S150EPQ208-6C XC2S150EPQ208-6C 3.3V only Virtex-II Pro XC2VP30FF1152-6C/I XC2VP30FF1152-6C/I 3.3V only Spartan-IIE XC2S200EPQ208-6C XC2S200EPQ208-6C 3.3V only Virtex-II Pro XC2VP40FF1152-6C/I XC2VP40FF1152-6C/I 3.3V only Spartan-IIE XC2S300EPQ208-6C XC2S300EPQ208-6C 3.3V only Virtex-II Pro XC2VP50FF1152-6C/I XC2VP50FF1152-6C/I 3.3V only Spartan-IIE XC2S100EPQ208-6C XC2S100EPQ208-6C 3.3V only SpartanTM-II XC2S150FG456-6C XC2S150FG456-6C 3.3V only Spartan-IIE XC2S150EPQ208-6C XC2S150EPQ208-6C 3.3V only Spartan-II XC2S200FG456-6C XC2S200FG456-6C 3.3V only Spartan-IIE XC2S200EPQ208-6C XC2S200EPQ208-6C 3.3V only Spartan-IIE XC2S300EFG456-6C XC2S300EFG456-6C 3.3V only Spartan-IIE XC2S300EPQ208-6C XC2S300EPQ208-6C 3.3V only Virtex XCV300BG432-5C XCV300BG432-5C Virtex XCV1000FG680-5C XCV1000FG680-5C Virtex-E XCV100EBG352-6C XCV100EBG352-6C Virtex-E XCV300EBG432-6C XCV300EBG432-6C Virtex-E XCV1000EFG680-6C XCV1000EFG680-6C Virtex-II XC2V1000FG456-4C/I/M XC2V1000FG456-4C/I/M Virtex-II Pro XC2VP7FF672-5C/I XC2VP7FF672-5C/I 3.3V, 5.0V 3.3V, 5.0V 3.3V only 3.3V only 3.3V only 3.3V only 3.3V only Spartan-3 XC3S1000FG456-4C XC3S1000FG456-4C 12 3.3V only Virtex-II Pro XC2VP20FF1152-5C/I XC2VP20FF1152-5C/I 3.3V only Virtex-II Pro XC2VP30FF1152-5C/I XC2VP30FF1152-5C/I 3.3V only Virtex-II Pro XC2VP40FF1152-5C/I XC2VP40FF1152-5C/I Virtex-II Pro XC2VP50FF1152-5C/I XC2VP50FF1152-5C/I Spartan-II XC2S100FG456-6C XC2S100FG456-6C Spartan-II XC2S150FG456-6C XC2S150FG456-6C Spartan-II XC2S200FG456-6C XC2S200FG456-6C Spartan-IIE XC2S100EFG456-6C XC2S100EFG456-6C Spartan-IIE XC2S150EFG456-6C XC2S150EFG456-6C Spartan-IIE XC2S200EFG456-6C XC2S200EFG456-6C PCI64/33 PCI64/33 3.3V only Virtex-E XCV1000EFG680-6C XCV1000EFG680-6C 3.3V only 3.3V only 3.3V, 5.0V 3.3V, 5.0V 3.3V, 5.0V 3.3V only 3.3V only 3.3V only Spartan-IIE XC2S300EFG456-6C XC2S300EFG456-6C Spartan-3 XC3S1000FG456-4C XC3S1000FG456-4C 12 Virtex XCV200FG256-6C XCV200FG256-6C 3.3V only Notes: 1. The resource utilization depends on configuration of the interface and the user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table are representative of a maximum configuration. 2. Designs running at 66 MHz in devices other than Virtex-II require one GCLKIOB and two GCLKs. 3. See the implementation guide or product release notes for current supported versions. 4. XST is command line option only. See Implementation Guide for details. 5. Universal card implementations require two bitstreams. 6. Virtex-E and Spartan-IIE recommended for CardBus. 3.3V only Virtex-E XCV200EFG256-6C XCV200EFG256-6C PCI32/66 PCI32/66 3.3V only Xilinx provides technical support for this LogiCORE product when used as described in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if customized beyond that allowed in the product documentation. Virtex-E XCV400EFG676-6C XCV400EFG676-6C 3.3V only 3.3V only 7. Commercial devices; 0oC < Tj < 85oC. 8. For additional Part/Package combinations, see the UCF Generator in the PCI Lounge. 9. XC2V1000 XC2V1000 is supported over Military Temp. range. 10. The Spartan-3 device does not contain TBUFs. The Xilinx tools automatically translate TBUFs to LUTs, and they are included in the worst case LUT count listed. 11. Virtex-II Pro devices are supported over commercial and industrial temperatures ranges. 12. Spartan-3 PCI Solution pending production speed files. 2 www.xilinx.com 1-800-255-7778 DS207 DS207 April 26, 2004 Product Specification v3.0.128 LogiCORE PCI Interface v3.0 Applications · Embedded applications in networking, industrial, and telecommunication systems. · PCI add-in boards such as frame buffers, network adapters, and data acquisition boards · Hot Swap CompactPCI boards · CardBus Compliant · Any applications that need a PCI interface ered with Smart-IP constraint files that are unique for a device and package combination. These constraint files guide the implementation tools so that the critical paths always are within specification. Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint files for unsupported device and package combinations may be generated using the web-based constraint file generator. Functional Description PAR PAR64 PAR64 PERRSERR- Other features that enable efficient implementation of a PCI system include: · Block SelectRAMTM memory. Blocks of on-chip ultra-fast RAM with synchronous write and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. · SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. · Internal three-state bus capability for data multiplexing. The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA devices. Smart-IP Technology Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the highest performance, predictability, repeatability, and flexibility in PCI designs. The Smart-IP technology is incorporated in every LogiCORE PCI Interface. Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and segmented routing, as well as floorplanning information, such as logic mapping and location constraints. This technology provides the best physical layout, predictability, and performance. Additionally, these features allow for significantly reduced compile times over competing architectures. Base Address Register 0 Base Address Register 1 Base Address Register 2 Command/ Status Register AD[63:0] ADIO[63:0] FRAMEIRDYREQGNT- Initiator State Machine REQ64- REQ64- Interrupt Pin and Line Register Latency Timer Register Vendor ID, Rev ID, Other User Data PCI Configuration Space ACK64TRDY- ACK64TRDY- The core meets the setup, hold, and clock to timing requirements as specified in the PCI specification. The interface is verified through extensive simulation. Parity Generator/ Checker USER APPLICATION The LogiCORE PCI Interface is a preimplemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined. Critical paths are controlled by constraint and guide files to ensure predictable timing. This significantly reduces the engineering time required to implement the PCI portion of your design. Resources can instead be focused on your unique user application logic in the FPGA and on the system level design. As a result, LogiCORE PCI products minimize your product development time. The LogiCORE PCI Interface is partitioned into five major blocks and a user application as shown in Figure 1. PCI I/O INTERFACE General Description DEVSELSTOP- Target State Machine Figure 1: LogiCORE PCI Interface Block Diagram PCI I/O Interface Block The I/O interface block handles the physical connection to the PCI bus including all signaling, input and output synchronization, output three-state controls, and all requestgrant handshaking for bus mastering. User Application The LogiCORE PCI Interface provides a simple, general-purpose interface for a wide range of applications. PCI Configuration Space This block provides the first 64 bytes of Type 0, version 2.3 Configuration Space Header, as shown in Table 1, to support software-driven "Plug-and-Play" initialization and configuration. This includes information for Command, Status, and three Base Address Registers (BARs). The capability for extending configuration space has been built into the user application interface. This capability, including the ability to implement a capabilities pointer in configuration space, allows the user to implement functions such as power management and message signaled interrupts in the user application. To guarantee the critical setup, hold, minimum clock to out, and maximum clock to out timing, the PCI interface is deliv- DS207 DS207 April 26, 2004 Product Specification v3.0.128 www.xilinx.com 1-800-255-7778 3 LogiCORE PCI Interface v3.0 among many others, are supported by the interface and are described in the product design guide. Table 1: PCI Configuration Space Header 31 16 15 0 · Device ID Vendor ID Status Command Base Address Registers (number, size and type) · 00h Configuration Space Header ROM 04h Rev ID Class Code BIST Header Type Latency Timer Cache Line Size Burst Transfer 08h 0Ch The PCI bus derives its performance from its ability to support burst transfers. The performance of any PCI application depends largely on the size of the burst transfer. Buffers to support PCI burst transfer can efficiently be implemented using on-chip RAM resources. Base Address Register 0 (BAR0) 10h Base Address Register 1 (BAR1) 14h Base Address Register 2 (BAR2) 18h Supported PCI Commands Base Address Register 3 (BAR3) 1Ch Base Address Register 4 (BAR5) 20h Table 2 illustrates the PCI bus commands supported by the LogiCORE PCI Interface. Base Address Register 5 (BAR5) 24h Bandwidth Cardbus CIS Pointer 28h The LogiCORE PCI Interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. This interface supports a sustained bandwidth of up to 528 MBytes/sec. The design can be configured to take advantage of the ability of the LogiCORE PCI Interface to do very long bursts. Subsystem ID Subsystem Vendor ID 30h Expansion ROM Base Address Reserved CapPtr Min Gnt Int Pin 34h 38h Reserved Max Lat 2Ch Int Line Reserved 3Ch 40h-FFh Notes: 1. Shaded areas are not implemented and return zero. Parity Generator/Checker This block generates and checks even parity across the AD bus, the CBE# lines, and the parity signals. It also reports data parity errors via PERR# and address parity errors via SERR#. The flexible user application interface, combined with support for many different PCI features, gives users a solution that lends itself to use in many high-performance applications. The user is not locked into one DMA engine, hence, an optimized design that fits a specific application can be designed. Table 2: PCI Bus Commands CBE [3:0] PCI Initiator Command PCI Target 0000 Interrupt Acknowledge Yes Yes 0001 Special Cycle Yes Ignore Initiator State Machine 0010 I/O Read Yes Yes 0011 I/O Write Yes Yes This block controls the PCI interface initiator functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The initiator control logic uses one-hot encoding for maximum performance. 0100 Reserved Ignore Ignore 0101 Reserved Ignore Ignore 0110 Memory Read Yes Yes 0111 Memory Write Yes Yes Target State Machine 1000 Reserved Ignore Ignore 1001 Reserved Ignore Ignore 1010 Configuration Read Yes Yes 1011 Configuration Write Yes Yes 1100 Memory Read Multiple Yes Yes 1101 Dual Address Cycle No Ignore 1110 Memory Read Line Yes Yes 1111 Memory Write Invalidate No Yes This block controls the PCI interface target functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The target control logic uses one-hot encoding for maximum performance. Interface Configuration The LogiCORE PCI Interface can easily be configured to fit unique system requirements by using the Xilinx Web-based Configuration and Download Tool or by changing the HDL configuration file. The following customization options, 4 www.xilinx.com 1-800-255-7778 DS207 DS207 April 26, 2004 Product Specification v3.0.128 LogiCORE PCI Interface v3.0 Recommended Design Experience The LogiCORE PCI Interface is pre-implemented allowing engineering focus on the unique user application functions of a PCI design. Regardless, PCI is a high-performance design that is challenging to implement in any technology. Therefore, previous experience with building high-performance, pipelined FPGA designs using Xilinx implementation software, constraint files, and guide files is recommended. The challenge to implement a complete PCI design including user application functions varies depending on configuration and functionality of your application. Contact your local Xilinx representative for a closer review and estimation for your specific requirements. Table 4: Timing Parameters, 33MHz Implementations Min Max Tcyc CLK Cycle Time 301 - Thigh CLK High Time 11 - Tlow CLK Low Time 11 - Tval CLK to Signal Valid Delay (bussed signals) 22 112 Tval CLK to Signal Valid Delay (point to point signals) 22 112 Ton Float to Active Delay 22 - Toff Active to Float Delay - 281 Tsu Input Setup Time to CLK (bussed signals) 72 - Timing Specifications Tsu Input Setup Time to CLK (point to point signals) 102 - The maximum speed at which your user design is capable of running can be affected by the size and quality of the design. The following tables show the key timing parameters for the LogiCORE PCI Interface. Th Input Hold Time from CLK 02 - - 40 Table 3 lists the Timing Parameters in the 66 MHz Implementations and Table 4 lists Timing Parameters in the 33 MHz Implementations. Table 3: Timing Parameters, 66MHz Implementations Symbol Parameter Symbol Trstoff Parameter Reset Active to Output Float Notes: 1. Controlled by timespec constraints, included in product. 2. Controlled by SelectIO configured for PCI33 PCI33_3 or PCI33 PCI33_5. Ordering Information This core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE GeneratorTM System v6.1i and later. The Xilinx CORE Generator System tool is bundled with all Alliance and Foundation Series Software packages, at no additional charge. Min Max Tcyc CLK Cycle Time 151 30 Thigh CLK High Time 6 - Tlow CLK Low Time 6 - Tval CLK to Signal Valid Delay (bussed signals) 22 62 To order the Xilinx PCI Core, please visit the contact your local Xilinx sales representative. Tval CLK to Signal Valid Delay (point to point signals) 22 62 Part Numbers Ton Float to Active Delay 22 - Toff Active to Float Delay DO-DI-PCI-AL - 141 Input Setup Time to CLK (bussed signals) 32,3 - -Access to the v3.0 32/64-bit PCI Lounge IP only core supporting Spartan and Virtex Families Tsu Input Setup Time to CLK (point to point signals) 52,3 - - Equivalent to purchasing the DO-DI-PCI64-IP DO-DI-PCI64-IP and DO-DI-PCI32-IP DO-DI-PCI32-IP Th Input Hold Time from CLK 02,3 - - 40 Tsu Trstoff Reset Active to Output Float Notes: 1. Controlled by SelectIO configured for PCI66 PCI66_3. 3. - Upgrade from PCI32 PCI32 IP only to PCI 64 and PCI32 PCI32 IP only core Controlled by timespec constraints, included in product. 2. DX-DI-PCI64-IP DX-DI-PCI64-IP Controlled by guide file, included in product. DS207 DS207 April 26, 2004 Product Specification v3.0.128 www.xilinx.com 1-800-255-7778 5 LogiCORE PCI Interface v3.0 Revision History Date 08/30/02 1.2 Style update 12/18/02 1.3 Updated to V3.0.103; updated Xilinx tool to v5.Ii 3/4/03 1.4 Updated to v3.0.105; v5.2i; changed document date to 3/7/03; updated date in footer legal content to 2003. 4/14/03 1.5 Updated to v3.0.106; In LogiCORE Facts table, updated PCI32/66 PCI32/66 and PC32/33 PC32/33 product listings to include Spartan-3 device support. 5/8/03 1.6 Updated Xilinx tools to 5.2i SP2; added Note 10. 8/11/03 1.7 In Supported Products table, PCI64/66 PCI64/66 section, Virtex-II Pro XC2VP7FF672-7 XC2VP7FF672-7 was -7c; updated to incorporated Corporate documentation standards. 9/17/03 1.8 Updated to v3.0.113; in LogiCORE Facts table, Xilinx Tools v6.1i SP1 was v5.2i SP2; date was August 11, 2003. 11/10/03 1.9 Updated to v3.0.116; in Supported Products table, PCI64/66 PCI64/66 section, Virtex-II Pro XC2VP7FF672-6C XC2VP7FF672-6C was -7C. 12/17/03 1.10 Updated device support information in Facts Table (added Virtex-II Pro devices). 1/7/2004 1.11 Updated to v3.0.117; in Supported Products table, sections PCI64/66 PCI64/66 and PCI64/33 PCI64/33, added Virtex-II Pro XC2VP20 XC2VP20.through XC2VP50 XC2VP50; updated Xilinx tools to 5.2i SP3. 1/30/2004 1.12 Updated to v3.0.122, changed date to January 25, 2004. 4/9/2004 1.13 Updated to v3.0.126; updated Xilinx tools to 6.2i SP1; added notes 11 and 12 to Supported devices table; added suffix /I to all Virtex-II Pro devices. 4/26/2004 6 Version Revision 1.14 Updated build version to v3.0.128, updated Xilinx tools to 6.2i SP2, changed date to April 26, 2004. www.xilinx.com 1-800-255-7778 DS207 DS207 April 26, 2004 Product Specification v3.0.128