NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
DS05-50208-3E MB84LD23381EJ-10 BGA-101P-M01 MB84LD23381EJ MBM29DD640E DQ15-DQ8 - Datasheet Archive
FUJITSU SEMICONDUCTOR DATA SHEET DS05-50208-3E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM CMOS 64 M (× 16)
To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-50208-3E DS05-50208-3E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM CMOS 64 M (× 16) FLASH MEMORY & 16 M (× 16) SRAM Interface FCRAM MB84LD23381EJ-10 MB84LD23381EJ-10 s FEATURES · Power Supply Voltage of 2.3 V to 2.7 V for Flash · Power Supply Voltage of 2.3 V to 2.7 V for FCRAM · High Performance 100 ns maximum access time (Flash) 85 ns maximum access time (FCRAM) · Operating Temperature -30 °C to +85 °C · Package 101-ball FBGA (Continued) s PRODUCT LINE-UP Flash Memory FCRAM VCCf* = 2.3 to 2.7 VCCS* = 2.3 to 2.7 Max Address Access Time (ns) 100 85 Max CE Access Time (ns) 100 85 Max OE Access Time (ns) 40 50 Supply Voltage (V) *: Both VCCf and VCCs must be the same level when either part is accessed. s PACKAGE 101-ball plastic FBGA BGA-101P-M01 BGA-101P-M01 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 (Continued) · FLASH MEMORY · Simultaneous Read/Write Operations (Flex Bank) Two virtual Banks are chosen from the combination of four physical banks. Host system can program or erase in one bank, then immediately and simultaneously read from the other bank. Zero latency between read and write operations. Read-while-erase Read-while-program · Minimum 100,000 Write/Erase Cycles · Sector Erase Architecture Sixteen 4 Kwords and one hundred twenty-six 32 Kword sectors. Any combination of sectors can be concurrently erased. Also MB84LD23381EJ MB84LD23381EJ supports full chip erase. · Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector. · Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address. · Data Polling and Toggle Bit feature for detection of program or erase cycle completion · Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion · Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. · Hidden ROM (Hi-ROM) Region 256 byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) · WP/ACC Input Pin Allows protection of "outermost" 2 × 8 Kbytes on both ends of boot sectors at VIL, regardless of sector protection/ unprotection status. Allows removal of boot sector protection at VIH. Increases program performance at VACC. · Program Suspend/Resume Suspends the program operation to allow a read in another bank. · Erase Suspend/Resume Suspends the erase operation to allow reading in another sector within the same device. · Please refer to "MBM29DD640E MBM29DD640E" datasheet for detailed functions · FCRAM · Power Dissipation Operating: 20 mA Max Standby: 70 µA Max Power Down: 10 µA Max · Power Down Control by CE2s · Byte Write Control: LBs (DQ7-DQ0), UBs (DQ15-DQ8 DQ15-DQ8) · 4 words Address Access Capability *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s PIN ASSIGNMENT FBGA (TOP VIEW) Marking side A12 B12 C12 M12 N12 O12 N.C. N.C. N.C. N.C. N.C. N.C. A11 B11 C11 G11 H11 M11 N11 O11 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. A10 B10 C10 E10 F10 G10 H10 J10 K10 M10 N10 O10 N.C. N.C. N.C. A15 A21 N.C. A16 VCCf VSS N.C. N.C. N.C. D9 E9 F9 G9 H9 J9 K9 L9 A11 A12 A13 A14 N.C. DQ15 DQ7 DQ14 D8 E8 F8 G8 H8 J8 K8 L8 A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5 C7 D7 E7 F7 J7 K7 L7 M7 N.C. WE CE2s A20 DQ4 VCCs N.C. N.C. C6 D6 E6 F6 J6 K6 L6 M6 DQ3 VCCf DQ11 N.C. N.C. WP/ACC RESET RY/BY D5 E5 F5 G5 H5 J5 K5 L5 LBS UBS A18 A17 DQ1 DQ9 DQ10 DQ2 D4 E4 F4 G4 H4 J4 K4 L4 A7 A6 A5 A4 VSS OE DQ0 DQ8 A3 B3 C3 E3 F3 G3 H3 J3 K3 M3 N3 O3 N.C. N.C. N.C. A3 A2 A1 A0 CEf CE1s N.C. N.C. N.C. A2 B2 C2 D2 G2 H2 M2 N2 O2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. A1 B1 C1 M1 N1 O1 N.C. N.C. N.C. N.C. N.C. N.C. (BGA-101P-M01 BGA-101P-M01) 3 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s PIN DESCRIPTION Table 1 Pin Description Pin name A19 to A0 I Address Inputs (Common) A21, A20 I Address Inputs (Flash) DQ15 to DQ0 I/O CEf I Chip Enable (Flash) CE1s I Chip Enable (FCRAM) CE2s I Chip Enable (FCRAM) OE I Output Enable (Common) WE I Write Enable (Common) RY/BY O Ready/Busy Output (Flash) Open Drain Output UBs I Upper Byte Control (FCRAM) LBs I Lower Byte Control (FCRAM) RESET I Hardware Reset Pin/Sector Protection Unlock (Flash) WP/ACC I Write Protect/Acceleration (Flash) N.C. VSS Power Device Ground (Common) VCCf Power Device Power Supply (Flash) VCCs 4 Input/Output Function Power Device Power Supply (FCRAM) Data Inputs/Outputs (Common) No Internal Connection To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s BLOCK DIAGRAM VCCf VSS A21 to A0 RY/BY A21 to A0 WP/ACC RESET CEf 64 Mbit Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A19 to A0 LBs UBs WE OE CE1s CE2s 16 Mbit FCRAM DQ15 to DQ0 5 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s DEVICE BUS OPERATIONS Table 2 User Bus Operations CEf CE1s CE2s OE WE LBs UBs DQ7 to DQ0 DQ15 to DQ8 RESET WP/ACC *7 Operation *1, *2 Full Standby H X High-Z High-Z L H H H X X High-Z High-Z H H H H X X High-Z High-Z H H L H X X DOUT H H H L X X H L H L H X H L H H L X H X DOUT H X DIN DIN H X X DOUT DOUT H X L DIN DIN H L High-Z DIN H X L Write to FCRAM H L Read from FCRAM * X L 5 X L Write to Flash X L Read from Flash *4 H H Output Disable *3 H H DIN High-Z Temporary Sector Group Unprotection *6 X X X X X X X X X VID X Flash Hardware Reset X H H X X X X High-Z High-Z L X Boot Block Sector Write Protection X X X X X X X X X X L FCRAM Power Down*8 X X L X X X X X X X X Legend: L = VIL, H = VIH, X = VIL or VIH . See DC Characteristics for voltage levels. *1: Other operations except for this indicated table are inhibited. *2: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *3: FCRAM Output Disable condition should not be kept longer than 1 µs. *4: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5: FCRAM Byte control at Read operation is not supported. *6: It is also used for the extended sector group protections. *7: Protect "outermost" 2 × 8 Kbytes (4 words) on both ends of the boot block sectors. *8: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. 6 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY · Sixteen 4 Kwords, and one hundred twenty-six 32 Kwords. · Individual-sector, multiple-sector, or bulk-erase capability. Bank A Bank B SA0 : 8 KB (4 KW) SA1 : 8 KB (4 KW) SA2 : 8 KB (4 KW) SA3 : 8 KB (4 KW) SA4 : 8 KB (4 KW) SA5 : 8 KB (4 KW) SA6 : 8 KB (4 KW) SA7 : 8 KB (4 KW) SA8 : 64 KB (32 KW) SA9 : 64 KB (32 KW) SA10 : 64 KB (32 KW) SA11 : 64 KB (32 KW) SA12 : 64 KB (32 KW) SA13 : 64 KB (32 KW) SA14 : 64 KB (32 KW) SA15 : 64 KB (32 KW) SA16 : 64 KB (32 KW) SA17 : 64 KB (32 KW) SA18 : 64 KB (32 KW) SA19 : 64 KB (32 KW) SA20 : 64 KB (32 KW) SA21 : 64 KB (32 KW) SA22 : 64 KB (32 KW) SA23 : 64 KB (32 KW) SA24 : 64 KB (32 KW) SA25 : 64 KB (32 KW) SA26 : 64 KB (32 KW) SA27 : 64 KB (32 KW) SA28 : 64 KB (32 KW) SA29 : 64 KB (32 KW) SA30 : 64 KB (32 KW) SA31 : 64 KB (32 KW) SA32 : 64 KB (32 KW) SA33 : 64 KB (32 KW) SA34 : 64 KB (32 KW) SA35 : 64 KB (32 KW) SA36 : 64 KB (32 KW) SA37 : 64 KB (32 KW) SA38 : 64 KB (32 KW) SA39 : 64 KB (32 KW) SA40 : 64 KB (32 KW) SA41 : 64 KB (32 KW) SA42 : 64 KB (32 KW) SA43 : 64 KB (32 KW) SA44 : 64 KB (32 KW) SA45 : 64 KB (32 KW) SA46 : 64 KB (32 KW) SA47 : 64 KB (32 KW) SA48 : 64 KB (32 KW) SA49 : 64 KB (32 KW) SA50 : 64 KB (32 KW) SA51 : 64 KB (32 KW) SA52 : 64 KB (32 KW) SA53 : 64 KB (32 KW) SA54 : 64 KB (32 KW) SA55 : 64 KB (32 KW) SA56 : 64 KB (32 KW) SA57 : 64 KB (32 KW) SA58 : 64 KB (32 KW) SA59 : 64 KB (32 KW) SA60 : 64 KB (32 KW) SA61 : 64 KB (32 KW) SA62 : 64 KB (32 KW) SA63 : 64 KB (32 KW) SA64 : 64 KB (32 KW) SA65 : 64 KB (32 KW) SA66 : 64 KB (32 KW) SA67 : 64 KB (32 KW) SA68 : 64 KB (32 KW) SA69 : 64 KB (32 KW) SA70 : 64 KB (32 KW) 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh Bank C Bank D SA71 : 64 KB (32 KW) SA72 : 64 KB (32 KW) SA73 : 64 KB (32 KW) SA74 : 64 KB (32 KW) SA75 : 64 KB (32 KW) SA76 : 64 KB (32 KW) SA77 : 64 KB (32 KW) SA78 : 64 KB (32 KW) SA79 : 64 KB (32 KW) SA80 : 64 KB (32 KW) SA81 : 64 KB (32 KW) SA82 : 64 KB (32 KW) SA83 : 64 KB (32 KW) SA84 : 64 KB (32 KW) SA85 : 64 KB (32 KW) SA86 : 64 KB (32 KW) SA87 : 64 KB (32 KW) SA88 : 64 KB (32 KW) SA89 : 64 KB (32 KW) SA90 : 64 KB (32 KW) SA91 : 64 KB (32 KW) SA92 : 64 KB (32 KW) SA93 : 64 KB (32 KW) SA94 : 64 KB (32 KW) SA95 : 64 KB (32 KW) SA96 : 64 KB (32 KW) SA97 : 64 KB (32 KW) SA98 : 64 KB (32 KW) SA99 : 64 KB (32 KW) SA100 SA100 : 64 KB (32 KW) SA101 SA101 : 64 KB (32 KW) SA102 SA102 : 64 KB (32 KW) SA103 SA103 : 64 KB (32 KW) SA104 SA104 : 64 KB (32 KW) SA105 SA105 : 64 KB (32 KW) SA106 SA106 : 64 KB (32 KW) SA107 SA107 : 64 KB (32 KW) SA108 SA108 : 64 KB (32 KW) SA109 SA109 : 64 KB (32 KW) SA110 SA110 : 64 KB (32 KW) SA111 SA111 : 64 KB (32 KW) SA112 SA112 : 64 KB (32 KW) SA113 SA113 : 64 KB (32 KW) SA114 SA114 : 64 KB (32 KW) SA115 SA115 : 64 KB (32 KW) SA116 SA116 : 64 KB (32 KW) SA117 SA117 : 64 KB (32 KW) SA118 SA118 : 64 KB (32 KW) SA119 SA119 : 64 KB (32 KW) SA120 SA120 : 64 KB (32 KW) SA121 SA121 : 64 KB (32 KW) SA122 SA122 : 64 KB (32 KW) SA123 SA123 : 64 KB (32 KW) SA124 SA124 : 64 KB (32 KW) SA125 SA125 : 64 KB (32 KW) SA126 SA126 : 64 KB (32 KW) SA127 SA127 : 64 KB (32 KW) SA128 SA128 : 64 KB (32 KW) SA129 SA129 : 64 KB (32 KW) SA130 SA130 : 64 KB (32 KW) SA131 SA131 : 64 KB (32 KW) SA132 SA132 : 64 KB (32 KW) SA133 SA133 : 64 KB (32 KW) SA134 SA134 : 8 KB (4 KW) SA135 SA135 : 8 KB (4 KW) SA136 SA136 : 8 KB (4 KW) SA137 SA137 : 8 KB (4 KW) SA138 SA138 : 8 KB (4 KW) SA139 SA139 : 8 KB (4 KW) SA140 SA140 : 8 KB (4 KW) SA141 SA141 : 8 KB (4 KW) 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h 3FFFFFh MB84LD23381EJ MB84LD23381EJ Sector Architecture 7 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 Table 3.1 Example of Virtual Banks Combination Bank 1 Bank Splits Volume Combination Bank 2 Sector Size Volume Combination Sector Size Bank B + Bank C + Bank D 8 × 8 Kbyte/4 Kword + 111 × 64 Kbyte/32 Kword 1 8 Mbit Bank A 8 × 8 Kbyte/4 Kword + 56 Mbit 15 × 64 Kbyte/32 Kword 2 16 Mbit Bank A + Bank D 16 × 8 Kbyte/4 Kword + 48 Mbit 30 × 64 Kbyte/32 Kword Bank B + Bank C 96 × 64 Kbyte/32 Kword 16 × 8 Kbyte/4 Kword + 78 × 64 Kbyte/32 Kword 8 × 8 Kbyte/4 Kword + 63 × 64 Kbyte/32 Kword 3 24 Mbit Bank B 48 × 64 Kbyte/32 Kword 40 Mbit Bank A + Bank C + Bank D 4 32 Mbit Bank A + Bank B 8 × 8 Kbyte/4 Kword + 32 Mbit 63 × 64 Kbyte/32 Kword Bank C + Bank D Bank A: Address 000000h to 07FFFFh Bank B: Address 080000h to 1FFFFFh Bank C: Address 200000h to 37FFFFh Bank D: Address 380000h to 3FFFFFh 8 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 Table 3.2 Sector Address Tables Sector Address Bank Sector Bank Address Address Range A21 A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 0 0 000000h to 000FFFh SA1 0 0 0 0 0 0 0 0 0 1 001000h to 001FFFh SA2 0 0 0 0 0 0 0 0 1 0 002000h to 002FFFh SA3 0 0 0 0 0 0 0 0 1 1 003000h to 003FFFh SA4 0 0 0 0 0 0 0 1 0 0 004000h to 004FFFh SA5 0 0 0 0 0 0 0 1 0 1 005000h to 005FFFh SA6 0 0 0 0 0 0 0 1 1 0 006000h to 006FFFh SA7 0 0 0 0 0 0 0 1 1 1 007000h to 007FFFh SA8 0 0 0 0 0 0 1 X X X 008000h to 00FFFFh SA9 0 0 0 0 0 1 0 X X X 010000h to 017FFFh SA10 0 0 0 0 0 1 1 X X X 018000h to 01FFFFh SA11 0 0 0 0 1 0 0 X X X 020000h to 027FFFh SA12 0 0 0 0 1 0 1 X X X 028000h to 02FFFFh SA13 0 0 0 0 1 1 0 X X X 030000h to 037FFFh SA14 0 0 0 0 1 1 1 X X X 038000h to 03FFFFh SA15 0 0 0 1 0 0 0 X X X 040000h to 047FFFh SA16 0 0 0 1 0 0 1 X X X 048000h to 04FFFFh SA17 0 0 0 1 0 1 0 X X X 050000h to 057FFFh SA18 0 0 0 1 0 1 1 X X X 058000h to 05FFFFh SA19 0 0 0 1 1 0 0 X X X 060000h to 067FFFh SA20 0 0 0 1 1 0 1 X X X 068000h to 06FFFFh SA21 0 0 0 1 1 1 0 X X X 070000h to 077FFFh SA22 0 0 0 1 1 1 1 X X X 078000h to 07FFFFh SA23 0 0 1 0 0 0 0 X X X 080000h to 087FFFh SA24 0 0 1 0 0 0 1 X X X 088000h to 08FFFFh SA25 0 0 1 0 0 1 0 X X X 090000h to 097FFFh SA26 0 0 1 0 0 1 1 X X X 098000h to 09FFFFh SA27 0 0 1 0 1 0 0 X X X 0A0000h to 0A7FFFh SA28 Bank B A19 SA0 Bank A A20 0 0 1 0 1 0 1 X X X 0A8000h to 0AFFFFh SA29 0 0 1 0 1 1 0 X X X 0B0000h to 0B7FFFh SA30 0 0 1 0 1 1 1 X X X 0B8000h to 0BFFFFh SA31 0 0 1 1 0 0 0 X X X 0C0000h to 0C7FFFh SA32 0 0 1 1 0 0 1 X X X 0C8000h to 0CFFFFh SA33 0 0 1 1 0 1 0 X X X 0D0000h to 0D7FFFh SA34 0 0 1 1 0 1 1 X X X 0D8000h to 0DFFFFh SA35 0 0 1 1 1 0 0 X X X 0E0000h to 0E7FFFh (Continued) 9 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 Sector Address Bank Sector Bank Address Address Range A21 A18 A17 A16 A15 A14 A13 A12 0 1 1 1 0 1 X X X 0E8000h to 0EFFFFh 0 0 1 1 1 1 0 X X X 0F0000h to 0F7FFFh SA38 0 0 1 1 1 1 1 X X X 0F8000h to 0FFFFFh SA39 0 1 0 0 0 0 0 X X X 100000h to 107FFFh SA40 0 1 0 0 0 0 1 X X X 108000h to 10FFFFh SA41 0 1 0 0 0 1 0 X X X 110000h to 117FFFh SA42 0 1 0 0 0 1 1 X X X 118000h to 11FFFFh SA43 0 1 0 0 1 0 0 X X X 120000h to 127FFFh SA44 0 1 0 0 1 0 1 X X X 128000h to 12FFFFh SA45 0 1 0 0 1 1 0 X X X 130000h to 137FFFh SA46 0 1 0 0 1 1 1 X X X 138000h to 13FFFFh SA47 0 1 0 1 0 0 0 X X X 140000h to 147FFFh SA48 0 1 0 1 0 0 1 X X X 148000h to 14FFFFh SA49 0 1 0 1 0 1 0 X X X 150000h to 157FFFh SA50 0 1 0 1 0 1 1 X X X 158000h to 15FFFFh SA51 0 1 0 1 1 0 0 X X X 160000h to 167FFFh SA52 0 1 0 1 1 0 1 X X X 168000h to 16FFFFh SA53 0 1 0 1 1 1 0 X X X 170000h to 177FFFh SA54 0 1 0 1 1 1 1 X X X 178000h to 17FFFFh SA55 0 1 1 0 0 0 0 X X X 180000h to 187FFFh SA56 0 1 1 0 0 0 1 X X X 188000h to 18FFFFh SA57 0 1 1 0 0 1 0 X X X 190000h to 197FFFh SA58 0 1 1 0 0 1 1 X X X 198000h to 19FFFFh SA59 0 1 1 0 1 0 0 X X X 1A0000h to 1A7FFFh SA60 0 1 1 0 1 0 1 X X X 1A8000h to 1AFFFFh SA61 0 1 1 0 1 1 0 X X X 1B0000h to 1B7FFFh SA62 0 1 1 0 1 1 1 X X X 1B8000h to 1BFFFFh SA63 0 1 1 1 0 0 0 X X X 1C0000h to 1C7FFFh SA64 0 1 1 1 0 0 1 X X X 1C8000h to 1CFFFFh SA65 0 1 1 1 0 1 0 X X X 1D0000h to 1D7FFFh SA66 0 1 1 1 0 1 1 X X X 1D8000h to 1DFFFFh SA67 0 1 1 1 1 0 0 X X X 1E0000h to 1E7FFFh SA68 0 1 1 1 1 0 1 X X X 1E8000h to 1EFFFFh SA69 0 1 1 1 1 1 0 X X X 1F0000h to 1F7FFFh SA70 10 A19 0 SA37 Bank B A20 SA36 0 1 1 1 1 1 1 X X X 1F8000h to 1FFFFFh (Continued) To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 Sector Address Bank Sector Bank Address Address Range A21 A19 A18 A17 A16 A15 A14 A13 A12 1 0 0 0 0 0 0 X X X 200000h to 207FFFh SA72 1 0 0 0 0 0 1 X X X 208000h to 20FFFFh SA73 1 0 0 0 0 1 0 X X X 210000h to 217FFFh SA74 1 0 0 0 0 1 1 X X X 218000h to 21FFFFh SA75 1 0 0 0 1 0 0 X X X 220000h to 227FFFh SA76 1 0 0 0 1 0 1 X X X 228000h to 22FFFFh SA77 1 0 0 0 1 1 0 X X X 230000h to 237FFFh SA78 1 0 0 0 1 1 1 X X X 238000h to 23FFFFh SA79 1 0 0 1 0 0 0 X X X 240000h to 247FFFh SA80 1 0 0 1 0 0 1 X X X 248000h to 24FFFFh SA81 1 0 0 1 0 1 0 X X X 250000h to 257FFFh SA82 1 0 0 1 0 1 1 X X X 258000h to 25FFFFh SA83 1 0 0 1 1 0 0 X X X 260000h to 267FFFh SA84 1 0 0 1 1 0 1 X X X 268000h to 26FFFFh SA85 1 0 0 1 1 1 0 X X X 270000h to 277FFFh SA86 1 0 0 1 1 1 1 X X X 278000h to 27FFFFh SA87 Bank C A20 SA71 1 0 1 0 0 0 0 X X X 280000h to 287FFFh SA88 1 0 1 0 0 0 1 X X X 288000h to 28FFFFh SA89 1 0 1 0 0 1 0 X X X 290000h to 297FFFh SA90 1 0 1 0 0 1 1 X X X 298000h to 29FFFFh SA91 1 0 1 0 1 0 0 X X X 2A0000h to 2A7FFFh SA92 1 0 1 0 1 0 1 X X X 2A8000h to 2AFFFFh SA93 1 0 1 0 1 1 0 X X X 2B0000h to 2B7FFFh SA94 1 0 1 0 1 1 1 X X X 2B8000h to 2BFFFFh SA95 1 0 1 1 0 0 0 X X X 2C0000h to 2C7FFFh SA96 1 0 1 1 0 0 1 X X X 2C8000h to 2CFFFFh SA97 1 0 1 1 0 1 0 X X X 2D0000h to 2D7FFFh SA98 1 0 1 1 0 1 1 X X X 2D8000h to 2DFFFFh SA99 1 0 1 1 1 0 0 X X X 2E0000h to 2E7FFFh SA100 SA100 1 0 1 1 1 0 1 X X X 2E8000h to 2EFFFFh SA101 SA101 1 0 1 1 1 1 0 X X X 2F0000h to 2F7FFFh SA102 SA102 1 0 1 1 1 1 1 X X X 2F8000h to 2FFFFFh SA103 SA103 1 1 0 0 0 0 0 X X X 300000h to 307FFFh SA104 SA104 1 1 0 0 0 0 1 X X X 308000h to 30FFFFh SA105 SA105 1 1 0 0 0 1 0 X X X 310000h to 317FFFh SA106 SA106 1 1 0 0 0 1 1 X X X 318000h to 31FFFFh (Continued) 11 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 (Continued) Sector Address Bank Sector Bank Address Address Range A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SA107 SA107 1 1 0 0 1 0 0 X X X 320000h to 327FFFh SA108 SA108 1 1 0 0 1 0 1 X X X 328000h to 32FFFFh SA109 SA109 1 1 0 0 1 1 0 X X X 330000h to 337FFFh SA110 SA110 1 1 0 0 1 1 1 X X X 338000h to 33FFFFh SA111 SA111 1 1 0 1 0 0 0 X X X 340000h to 347FFFh SA112 SA112 1 1 0 1 0 0 1 X X X 348000h to 34FFFFh SA113 SA113 1 1 0 1 0 1 0 X X X 350000h to 357FFFh SA114 SA114 1 1 0 1 0 1 1 X X X 358000h to 35FFFFh SA115 SA115 1 1 0 1 1 0 0 X X X 360000h to 367FFFh SA116 SA116 1 1 0 1 1 0 1 X X X 368000h to 36FFFFh SA117 SA117 1 1 0 1 1 1 0 X X X 370000h to 377FFFh SA118 SA118 1 1 0 1 1 1 1 X X X 378000h to 37FFFFh SA119 SA119 1 1 1 0 0 0 0 X X X 380000h to 387FFFh SA120 SA120 1 1 1 0 0 0 1 X X X 388000h to 38FFFFh SA121 SA121 1 1 1 0 0 1 0 X X X 390000h to 397FFFh SA122 SA122 1 1 1 0 0 1 1 X X X 398000h to 39FFFFh SA123 SA123 1 1 1 0 1 0 0 X X X 3A0000h to 3A7FFFh SA124 SA124 1 1 1 0 1 0 1 X X X 3A8000h to 3AFFFFh SA125 SA125 1 1 1 0 1 1 0 X X X 3B0000h to 3B7FFFh SA126 SA126 1 1 1 0 1 1 1 X X X 3B8000h to 3BFFFFh SA127 SA127 1 1 1 1 0 0 0 X X X 3C0000h to 3C7FFFh SA128 SA128 1 1 1 1 0 0 1 X X X 3C8000h to 3CFFFFh SA129 SA129 1 1 1 1 0 1 0 X X X 3D0000h to 3D7FFFh Bank D SA130 SA130 1 1 1 1 0 1 1 X X X 3D8000h to 3DFFFFh SA131 SA131 1 1 1 1 1 0 0 X X X 3E0000h to 3E7FFFh SA132 SA132 1 1 1 1 1 0 1 X X X 3E8000h to 3EFFFFh SA133 SA133 1 1 1 1 1 1 0 X X X 3F0000h to 3F7FFFh SA134 SA134 1 1 1 1 1 1 1 0 0 0 3F8000h to 3F8FFFh SA135 SA135 1 1 1 1 1 1 1 0 0 1 3F9000h to 3F9FFFh SA136 SA136 1 1 1 1 1 1 1 0 1 0 3FA000h to 3FAFFFh SA137 SA137 1 1 1 1 1 1 1 0 1 1 3FB000h to 3FBFFFh SA138 SA138 1 1 1 1 1 1 1 1 0 0 3FC000h to 3FCFFFh SA139 SA139 1 1 1 1 1 1 1 1 0 1 3FD000h to 3FDFFFh SA140 SA140 1 1 1 1 1 1 1 1 1 0 3FE000h to 3FEFFFh SA141 SA141 1 1 1 1 1 1 1 1 1 1 3FF000h to 3FFFFFh Bank C 12 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 Table 4 Sector Group Addresses (MB84LD23381EJ MB84LD23381EJ) Sector Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 0 0 1 1 1 SA7 0 1 0 X X X SA8 to SA10 SGA8 0 0 0 0 0 1 1 1 SGA9 0 0 0 0 1 X X X X X SA11 to SA14 SGA10 SGA10 0 0 0 1 0 X X X X X SA15 to SA18 SGA11 SGA11 0 0 0 1 1 X X X X X SA19 to SA22 SGA12 SGA12 0 0 1 0 0 X X X X X SA23 to SA26 SGA13 SGA13 0 0 1 0 1 X X X X X SA27 to SA30 SGA14 SGA14 0 0 1 1 0 X X X X X SA31 to SA34 SGA15 SGA15 0 0 1 1 1 X X X X X SA35 to SA38 SGA16 SGA16 0 1 0 0 0 X X X X X SA39 to SA42 SGA17 SGA17 0 1 0 0 1 X X X X X SA43 to SA46 SGA18 SGA18 0 1 0 1 0 X X X X X SA47 to SA50 SGA19 SGA19 0 1 0 1 1 X X X X X SA51 to SA54 SGA20 SGA20 0 1 1 0 0 X X X X X SA55 to SA58 SGA21 SGA21 0 1 1 0 1 X X X X X SA59 to SA62 SGA22 SGA22 0 1 1 1 0 X X X X X SA63 to SA66 SGA23 SGA23 0 1 1 1 1 X X X X X SA67 to SA70 SGA24 SGA24 1 0 0 0 0 X X X X X SA71 to SA74 SGA25 SGA25 1 0 0 0 1 X X X X X SA75 to SA78 SGA26 SGA26 1 0 0 1 0 X X X X X SA79 to SA82 SGA27 SGA27 1 0 0 1 1 X X X X X SA83 to SA86 SGA28 SGA28 1 0 1 0 0 X X X X X SA87 to SA90 SGA29 SGA29 1 0 1 0 1 X X X X X SA91 to SA94 SGA30 SGA30 1 0 1 1 0 X X X X X SA95 to SA98 SGA31 SGA31 1 0 1 1 1 X X X X X SA99 to SA102 SA102 SGA32 SGA32 1 1 0 0 0 X X X X X SA103 SA103 to SA106 SA106 SGA33 SGA33 1 1 0 0 1 X X X X X SA107 SA107 to SA110 SA110 SGA34 SGA34 1 1 0 1 0 X X X X X SA111 SA111 to SA114 SA114 SGA35 SGA35 1 1 0 1 1 X X X X X SA115 SA115 to SA118 SA118 SGA36 SGA36 1 1 1 0 0 X X X X X SA119 SA119 to SA122 SA122 (Continued) 13 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 (Continued) Sector Group SGA37 SGA37 SGA38 SGA38 A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors 1 1 1 0 1 X X X X X SA123 SA123 to SA126 SA126 1 1 1 1 0 X X X X X SA127 SA127 to SA130 SA130 0 0 0 1 X X X SA131 SA131 to SA133 SA133 1 SGA39 SGA39 A21 0 1 1 1 1 1 SGA40 SGA40 1 1 1 1 1 1 1 0 0 0 SA134 SA134 SGA41 SGA41 1 1 1 1 1 1 1 0 0 1 SA135 SA135 SGA42 SGA42 1 1 1 1 1 1 1 0 1 0 SA136 SA136 SGA43 SGA43 1 1 1 1 1 1 1 0 1 1 SA137 SA137 SGA44 SGA44 1 1 1 1 1 1 1 1 0 0 SA138 SA138 SGA45 SGA45 1 1 1 1 1 1 1 1 0 1 SA139 SA139 SGA46 SGA46 1 1 1 1 1 1 1 1 1 0 SA140 SA140 SGA47 SGA47 1 1 1 1 1 1 1 1 1 1 SA141 SA141 Table 5.1 MB84LD23381EJ MB84LD23381EJ Sector Group Protection Verify Autoselect Codes Type A21 to A12 A6 A3 A2 A1 A0 Code (HEX) Manufacture's Code BA VIL VIL VIL VIL VIL 04h Device Code Word BA VIL VIL VIL VIL VIH 227Eh Extended Device Code*2 Word BA VIL VIH VIH VIH VIL 2204h Word BA VIL VIH VIH VIH VIH 2200h Sector Group Addresses VIL VIL VIL VIH VIL 01h*1 Sector Group Protection *1: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2: At WORD mode, a read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh,as well as at (BA) 0Fh. 14 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 Table 6 Flash Memory Command Definitions First Bus Second Bus Write Bus Write Cycle Write Cycle Cycles Req'd Addr. Data Addr. Data Command Sequence Addr. Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Data Addr. Data Addr. Data Addr. Data 555h AAh 2AAh 55h 555h F0h RA RD 555h AAh 2AAh 55h (BA) 555h 90h PD Read/Reset 1 XXXh F0h Read/Reset 3 Autoselect 3 Third Bus Write Cycle Program 4 555h AAh 2AAh 55h 555h A0h PA Chip Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h Sector Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h Sector Erase Suspend 1 BA B0h Sector Erase Resume 1 BA 30h Program Suspend 1 BA B0h Program Resume 1 BA 30h 3 555h AAh 2AAh 55h 555h 20h 1 2 XXXh A0h PD Reset from Fast Mode*1 2 90h XXXh F0h Extended Sector Group Protection *2 4 Query *3 1 55h Hi-ROM Entry 3 555h AAh 2AAh Set to Fast Mode Fast Program * BA XXXh 60h 98h PA SPA 60h SPA 40h SPA SD 55h 555h 88h (HRA) A0h PA PD 90h 00h Hi-ROM Program *4 4 555h AAh 2AAh 55h 555h Hi-ROM Exit *4 4 555h AAh 2AAh 55h (HRBA) 555h XXXh *1: This command is valid during Fast Mode. *2: This command is valid while RESET = VID. *3: This command is valid during Hi-ROM mode. *4: The data "00h" is also acceptable. 15 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 Notes: 1. Address bits A21 to A11 = X = "H" or "L" for all address commands except for Program Address (PA), Sector Address (SA), Bank Address (BA), and Sector Group Address (SPA). 2. Bus operations are defined in Table 2 and 3. 3. RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A21, A20, A19) 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. 5. SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6. HRA = Address of the Hi-ROM area Word Mode: 000000h to 00007Fh Byte Mode: 000000h to 0000FFh 7. HRBA = Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL) 8. The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A10 to A0 Byte Mode: AAAh or 555h to addresses A10 to A0, and A-1 9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 16 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max Tstg -55 +125 °C TA -30 +85 °C -0.3 VCCf + 0.3 -0.3 VCCs + 0.3 VCCf -0.2 +3.6 VCCs -0.2 +3.3 RESET *2 VIN -0.5 +13.0 V WP/ACC *3 VIN -0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins *1 VIN, VOUT VCCf/VCCs Supply *1 V V *1: Minimum DC voltage on input or I/O pins is 0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to 1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or VCCs+0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf+1.0 V or VCCs+1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is 0.5 V. During voltage transitions, RESET pin may undershoot VSS to 2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is 0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Ambient Temperature TA VCCf/VCCs Supply Voltages VCC Value Unit Min Max -30 +85 °C +2.3 +2.7 V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 17 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Value Conditions Min Typ Max Unit Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max -1.0 +1.0 µA Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max -1.0 +1.0 µA RESET Inputs Leakage Current ILIT VCCf = VCCf Max, RESET = 12.5 V 35 µA Flash VCC Active Current (Read) *1 ICC1f CEf = VIL, OE = VIH tCYCLE = 5 MHz 18 mA tCYCLE = 1 MHz 7 mA Flash VCC Active Current (Program/Erase) *2 ICC2f CEf = VIL, OE = VIH 35 mA Flash VCC Active Current (Read-While-Program) *5 ICC3f CEf = VIL, OE = VIH 53 mA Flash VCC Active Current (Read-While-Erase) *5 ICC4f CEf = VIL, OE = VIH 53 mA 15 20 ICC1s VCCs = VCCs Max, tRC/tWC = Min CE1s = VIL, CE2s = VIH, VIN = VIH or VIL, IOUT = 0 mA tRC/tWC = 1µs. FCRAM VCC Active Current 2.5 3.0 Flash VCC Standby Current ISB1f VCCf = VCCf Max, CEf = VCCf ± 0.3 V RESET = VCCf ± 0.3 V, WP/ACC = VCCf ± 0.3 V 5 µA Flash VCC Standby Current (RESET) ISB2f VCCf = VCCf Max, RESET = VSS ± 0.3 V, WP/ACC = VCCf ± 0.3 V 5 µA Flash VCC Current (Automatic Sleep Mode) *3 ISB3f VCCf = VCCf Max, CEf = VSS ± 0.3 V RESET = VCCf ± 0.3 V, WP/ACC = VCCf ± 0.3 V, VIN = VCCf ± 0.3 V or VSS ± 0.3 V 5 µA FCRAM VCC Standby Current ISBs VCCs = VCCs Max, CE1s = CE2s = VIH, VIN = VIH or VIL, IOUT = 0 mA 0.5 1 mA FCRAM VCC Standby Current ISB1s VCCs = VCCs Max, CE1s VCCs - 0.2 V, CE2s VCCs - 0.2 V, VIN 0.2 V or VCCs - 0.2 V, IOUT = 0 mA 70 µA FCRAM VCC Standby Current ISB2s VCCs = VCCs Max, CE1s VCCs - 0.2 V, CE2s VCCs - 0.2 V, Cycle time = tRC Min, IOUT = 0 mA 5 *6 mA FCRAM VCC Power Down Current IPDs VCCs = VCCs Max, VIN VCCf - 0.2 V or VIN 0.2 V, CE1s 0.2 V, CE2s 0.2 V, IOUT = 0 mA 10 µA mA (Continued) 18 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 (Continued) Parameter Symbol Conditions Input Low Level VIL Input High Level Value Unit Min Typ Max -0.3 0.4 V VIH 2.3 VCC + 0.3 V Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 VID 11.5 12.5 V Voltage for Program Acceleration (WP/ACC) *4 VACC 8.5 9.0 9.5 V FCRAM Output Low Level VOL VCCs = VCCs Min, IOL = 1.0 mA 0.4 V FCRAM Output High Level VOH VCCs = VCCs Min, IOH = -0.5 mA 1.8 V Flash Output Low Level VOL VCCf = VCCf Min, IOL = 0.1 mA 0.1 V Flash Output High Level VOH VCCf = VCCf Min, IOH = -0.1 mA VCCf - 0.1 V *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC is active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: Applicable for only VCC applying. *5: Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6: ISB2s depends on VIN cycle time. Please refer to "s APPENDIX". 19 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 2. AC Characteristics · CE Timing Parameter Symbols JEDEC Standard CE Recover Time tCCR CE Hold Time Conditions tCHOLD Value Typ Max 0 ns 3 ns · Timing Diagram for alternating FCRAM to Flash CEf tCCR tCCR CE1s WE tCHOLD tCCR CE2s 20 Unit Min tCHOLD tCCR To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read Only Operations Characteristics (Flash) Symbols Parameter JEDEC Standard Conditions Value * Min Max Unit Read Cycle Time tAVAV tRC 100 ns Address to Output Delay tAVQV tACC CEf = VIL OE = VIL 100 ns Chip Enable to Output Delay tELQV tCEf OE = VIL 100 ns Output Enable to Output Delay tGLQV tOE 40 ns Chip Enable to Output High-Z tEHQZ tDF 30 ns Output Enable to Output High-Z tGHQZ tDF 30 ns Output Hold Time From Addresses, CEf or OE, Whichever Occurs First tAXQX tOH 0 ns tREADY 20 µs RESET Pin Low to Read Mode *: Test Conditions - Output Load: 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V or VCCf Timing measurement reference level Input: 0.5 × VCCf Output: 0.5 × VCCf 21 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read Cycle (Flash) tRC Address Address Stable tACC CEf tOE tDF OE tOEH WE tOH tCEf High-Z High-Z Output Valid Outputs · Hardware Reset/Read Operation Timing Diagram (Flash) tRC Address Address Stable tACC CEf tRH tRP tRH tCEf RESET tOH Outputs 22 High-Z Output Valid To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Erase/Program Operations (Flash) Parameter Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time to CE Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Read Toggle and Data Polling CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Word Programming Operation Sector Erase Operation *1 VCCf Setup Time Voltage Transition Time *2 Rise Time to VID *2 Rise Time to VACC Recover Time from RY/BY RESET Pulse Width Delay Time from Embedded Output Enable RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Erase Time-out Time *3 Erase Suspend Transition Time *4 Output Enable Hold Time Symbol JEDEC Standard tWC tAVAV tAVWL tAS tASO tWLAX tAH tAHT tDVWH tDS tWHDX tDH tOEH tCEPH tOEPH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tVIDR tVACCR tRB tRP tEOE tRH tBUSY tTOW tSPD tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Min 100 0 15 50 0 50 0 0 10 20 20 0 0 0 0 0 0 45 45 30 30 50 4 500 500 0 500 200 50 Value Typ 16 1 Max 100 90 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs s µs µs ns ns ns ns ns ns ns µs µs *1: This does not include the preprogramming time. *2: This timing is for the Sector group Protection Operation. *3: The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command (s). *4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. 23 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Write Cycle (WE control) (Flash) 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CEf tCS tCH tCEf OE tGHWL tWP tOE tWPH tWHWH1 WE Data Notes: · · · · · 24 A0h tOH tDF tDS tDH PD DQ7 DOUT PA is an address of the memory location to be programmed. PD is data to be programmed at a word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. DOUT To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Write Cycle (CEf control) (Flash) 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CEf tDS Data Notes: · · · · · A0h tDH PD DQ7 DOUT PA is an address of the memory location to be programmed. PD is data to be programmed at a word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. 25 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · AC Waveforms Chip/Sector Erase Operations (Flash) 555h Address tWC 2AAh tAS 555h 555h 2AAh SA* tAH CEf tCS tCH OE tWP tWPH tDS tGHWL tDH WE AAh 30h for Sector Erase 55h 80h AAh 55h Data tVCS VCCf *: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase. 26 10h To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CEf tCH tDF tOE OE tOEH WE tCEf * DQ7 Data DQ7 DQ7 = Valid Data High-Z tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6 to DQ0 = Output Flag Data tBUSY DQ6 to DQ0 Valid Data High-Z tEOE RY/BY *: DQ7 = Valid Data (The device has completed the Embedded operation) 27 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Address tAHT tASO tAHT tAS CEf tCEPH WE tOEH tOEPH tOEH OE tDH DQ6, DQ2 tOE tCEf * Toggle Data Data Toggle Data Toggle Data tBUSY RY/BY *: DQ6 stops toggling (The device has completed the Embedded operation) 28 Stop Toggling Output Valid To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Back-to-back Read/Write Timing Diagram (Flash) Read Address Command Read Command Read Read tRC tWC tRC tWC tRC tRC BA1 BA2 (555h) BA1 BA2 (PA) BA1 BA2 (PA) tAS tACC tAH tAS tAHT tCEf CEf tOE tCEPH OE tGHWL tDF tOEH tWP WE tDS DQ Valid Output tDH Valid Intput (A0h) tDF Valid Output Valid Intput (PD) Valid Output Status Note: This is an example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1 BA2: Address of Bank 2 29 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY · RY/BY Timing Diagram during Write/Erase Operations (Flash) WE RESET tRP tRB RY/BY tREADY 30 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Temporary Sector Group Unprotection (Flash) VCCf tVIDR tVCS tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period · Acceleration Mode Timing Diagram (Flash) VCCf tVACCR tVCS tVLHT VID VIH WP/ACC CEf WE tVLHT tVLHT RY/BY Acceleration Mode period 31 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Extended Sector Group Protection (Flash) VCCf tVCS RESET tVLHT tVIDR tWC Address tWC SPAX SPAX SPAY A6, A3, A2, A0 A1 CEf OE TIME-OUT tWP WE Data 60h 60h 40h 01h tOE SPAX: Sector Group Address to be protected SPAY: Next Sector Group Address to be protected TIME-OUT: Time-Out window = 250 µs (Min) 32 60h To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Power On/Off Timing tPS tPS RESET VIH VCCf 2.3 V 2.3 V 0V Address Valid Data In Data Valid Data Out tRH tACC 33 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read Operation (FCRAM) Parameter Symbol Value Min Max Unit Notes Read Cycle Time tRC 90 ns Chip Enable Access Time tCE 85 ns *1, *3 Output Enable Access Time tOE 45 ns *1 Chip Enable Access Time tAA 85 ns *1, *4 Output Data Hold Time tOH 5 ns *1 CE1s Low to Output Low-Z tCLZ 5 ns *2 OE Low to Output Low-Z tOLZ 0 ns *2 CE1s High to Output High-Z tCHZ 30 ns *2 OE High to Output High-Z tOHZ 25 ns *2 Address Setup Time to CE1s Low tASC -5 ns *5 tASO 45 ns *3, *6 tASO[ABS] 10 ns *7 tAX 5 ns *4 CE1s Low to Address Hold Time tCLAH 90 ns *4 OE Low to Address Hold Time tOLAH 45 ns *4, *8 CE1s High to Address Hold Time tCHAH -5 ns OE High to Address Hold Time tOHAH -5 ns CE1s Low to OE Low Delay Time tCLOL 45 1000 ns *4, *6, *8, *9 OE Low to CE1s High Delay Time tOLCH 45 ns *8 tCP 20 ns tOP 45 1000 ns *6, *8, *9 tOP[ABS] 20 ns *7 Address Setup Time to OE Address Invalid Time CE1s High Pulse Width OE High Pulse Width *1: Output load is 30 pF. *2: Output load is 5 pF. *3: tCE is applicable if OE is brought to Low before CE1s goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable only to A0 and A1 when both CE1s and OE are kept at Low for the address access. *5: Applicable if OE is brought to Low before CE1s goes Low. *6: tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount of subtraction actual value from specified minimum value. For example if actual tASO, tASO (actual), is shorter than specified minimum value, tASO (Min), during OE control access (i.e., CE1s stays Low), the tOE becomes tOE (Max) + tASO (Min) - tASO (actual). *7: tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) - tCLOL (actual) or tRC (Min) - tOP (actual). *9: Maximum value is applicable if CE1s is kept at Low. 34 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Write Operation (FCRAM) Parameter Symbol Value Min Max Unit Notes Write Cycle Time tWC 90 ns *1 Address Setup Time tAS 0 ns *2 Address Hold Time tAH 45 ns *2 CE1s Write Setup Time tCS 0 1000 ns CE1s Write Hold Time tCH 0 1000 ns WE Setup Time tWS 0 ns WE Hold Time tWH 0 ns LBs and UBs Setup Time tBS 0 ns LBs and UBs Hold Time tBH -5 ns OE Setup Time tOES 0 1000 ns *3 tOEH 45 1000 ns *3, *4 tOEH[ABS] 20 ns *5 OE High to CE1s Low Setup Time tOHCL -3 ns *6 OE High to Address Hold Time tOHAH -5 ns *7 CE1s Write Pulse Width tCW 60 ns *1, *8 WE Write Pulse Width tWP 60 ns *1, *8 CE1s Write Recovery Time tWRC 15 ns *1, *9 WE Write Recovery Time tWR 15 1000 ns *1, *3, *9 Data Setup Time tDS 20 ns Data Hold Time tDH 0 ns CE1s High Pulse Width tCP 20 ns OE Hold Time *9 *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR). *2: New write address is valid from either CE1s or WE is brought to High. *3: Maximum value is applicable if CE1s is kept at Low and both WE and OE are kept at High. *4: The tOEH is specified from the end of tWC (Min), and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1s stays Low. *6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min), WE Low must be asserted after tRC (Min) from CE1s Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7: Applicable if CE1s stays Low after read operation. *8: tCW and tWP are applicable if write operation is initiated by CE1s and WE, respectively. *9: tWRC and tWR are applicable if write operation is terminated by CE1s and WE, respectively. The tWR (Min) can be ignored if CE1s is brought to High together or after WE is brought to High. In such a case, the tCP (Min) must be satisfied. 35 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Power Down Parameter (FCRAM) Parameter Symbol Value Min Max Unit CE2s Low Setup Time for Power Down Entry tCSP 10 ns CE2s Low Hold Time after Power Down Entry tC2LP 100 ns CE1s High Hold Time following CE2s High after Power Down Exit tCHH 350 µs CE1s High Setup Time following CE2s High after Power Down Exit tCHS 10 Note ns · Other Timing Parameter (FCRAM) Parameter Symbol CE1s High to OE Invalid Time for Standby Entry Value Unit Notes Min Max tCHOX 20 ns CE1s High to WE Invalid Time for Standby Entry tCHWX 20 ns *1 CE2s Low Hold Time after Power-up tC2LH 50 µs *2 CE2s Low High Time after Power-up tC2HL 50 µs *3 CE1s High Hold Time following CE2s High after Power-up tCHH 350 µs *2 tT 1 25 ns *4 Input Transition Time *1: It may write some data into any address location if tCHWX is not satisfied. *2: Must satisfy tCHH (Min) after tC2LH (Min) . *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. · AC Test Conditions (FCRAM) Symbol Parameter Conditions Value Unit VIH Input High Level VCCs = 2.7 V to 3.1 V 2.3 V VIL Input Low Level VCCs = 2.7 V to 3.1 V 0.4 V Input Timing Measurement Level VCCs = 2.7 V to 3.1 V 1.3 V Input Transition Time Between VIL and VIH 5 ns VREF tT 36 Note To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read Timing #1 (OE Control Access) (FCRAM) tRC Address tRC Address Valid Address Valid tOHAH tASO tCE tOHAH CE1s tOLCH tCLOL tOE tOP tOE OE tOHZ tASO tOLZ tOHZ tOLZ tOH tOH DQ (Output) Valid Data Output Valid Data Output Note: CE2s and WE must be High during the entire read cycle. · Read Timing #2 (CE1s Control Access) (FCRAM) tRC tRC Address Address Valid tASC Address Valid tCE tCHAH tASC tCE tCHAH CE1s tOLCH tCP tCE tCHZ tCHZ OE tCLZ tOH tCLZ tOH DQ (Output) Valid Data Output Valid Data Output Note: CE2s and WE must be High during the entire read cycle. 37 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read Timing #3 (Address Access after OE Control Access) (FCRAM) tRC tRC Address (A19 - A2) Address Valid Address Valid (No change) Address (A1, A0) Address Valid Address Valid tASO tOLAH tOHAH tAA tAX CE1s tOHZ tOE OE tOLZ tOH tOH DQ (Output) Valid Data Output Valid Data Output Note: CE2s and WE must be High during the entire read cycle. · Read Timing #4 (Address Access after CE1s Control Access) (FCRAM) tRC Address (A19 - A2) Address Valid Address (A1, A0) tRC Address Valid Address Valid (No change) Address Valid tCLAH tASC tAA tCHAH tAX CE1s tCHZ tCE OE tCLZ tOH tOH DQ (Output) Valid Data Output Note: CE2s and WE must be High during the entire read cycle. 38 Valid Data Output To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Write Timing #1 (CE1s Control) (FCRAM) tWC Address Address Valid tAS tAH tAS CE1s tCW tWRC tWS tWH tWS tBS tBH tBS WE UBs, LBs tOHCL OE tDS tDH DQ (Input) Valid Data Input Note: CE2s must be High during the write cycle. 39 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Write Timing #2-1 (WE Control, Single Write Operation) (FCRAM) tWC Address Address Valid tOHAH tAS tAH tAS tCH CE1s tCP tOHCL tCS tWP tWR WE tBS tBH UBs, LBs tOES OE tOHZ tDS tDH DQ (Input) Valid Data Input Note: CE2s must be High during the write cycle. 40 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Write Timing #2 (WE Control, Continuous Write Operation) (FCRAM) tWC Address Valid Address tOHAH tAS tAH tAS CE1s tOHCL tCS tWP tWR WE tBH tBS tBS UBs, LBs tOES OE tOHZ tDS tDH DQ (Input) Valid Data Input Note: CE2s must be High during the write cycle. 41 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read/Write Timing #1-1 (CE1s Control) (FCRAM) tWC Write Address Address tCHAH tAS Read Address tASC tAH CE1s tCP tWH tWRC tWS tCW tWH tWS WE tBH tBS UBs, LBs tCLOL tOHCL OE tOLZ tCHZ tOH tDS tDH DQ Read Data Output Write Data Input Note: Write address is valid from either CE1s or WE of the last falling edge. 42 tCLZ To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read/Write Timing #1-2 (CE1s Control) (FCRAM) tRC Address Read Address Write Address tASC tCHAH tWRC tAS CE1s tWRC (Min) tWH tCP tWH tWS tWS WE tBH tBS tCE UBs, LBs tOHCL tOEH OE tCHZ tDH tCLZ tOH DQ Write Data Input Read Data Output Note: The tOEH is specified from the time satisfied both tWRC and tWR (Min). 43 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read (OE Control) /Write (WE Control) Timing #2-1 (FCRAM) tWC Write Address Address tOHAH CE1s tAS Read Address tAH tASO Low tWR tWP WE tBH tBS UBs, LBs tOEH tOES OE tOHZ tOH tDS tDH DQ Read Data Output Write Data Input Note: CE1s can be tied to Low for WE and OE controlled operation. When CE1s is tied to Low, output is exclusively controlled by OE. 44 tOLZ To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Read (OE Control) /Write (WE Control) Timing #2-2 tRC Address Read Address Valid Write Address tOHAH tASO CE1s tAS Low tWR WE tBS tBH UBs, LBs tOEH tOES tOE OE tOHZ tDH tOLZ tOH DQ Write Data Input Read Data Output Note: CE1s can be tied to Low for WE and OE controlled operation. When CE1s is tied to Low, output is exclusively controlled by OE. 45 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Power Down Timing (FCRAM) CE1s tCHS CE2s tCSP tC2LP tCHH High-Z DQ Power Down Entry Power Down Mode Power Down Exit · Standby Entry Timing after Read or Write (FCRAM) CE1s tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period from either last address transition of A0 and A1, or CE1s Low to High transition. 46 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 · Power-Up Timing 1 (FCRAM) CE1s tCHS tC2LH CE2s tCHH * VDD VCCs Min 0V *: It is recommended that CE2s is kept at Low during VCCs power-up. The tC2LH specifies after VCCs reaches specifiled minimum level. · Power-Up Timing 2 (FCRAM) tCHS CE1s tCSP tC2HL CE2s tC2LP tCHH tC2HL VCCs Min VCCs 0V The tC2LH specifies from CE2s Low to High transition after VCCS reaches specified minimum level. CE1S must be brought to High prior to or together with CE2s Low to High transition. s ERASE AND PROGRAMMING PERFORMANCE (Flash) Parameter Value Unit Remarks 10 s Excludes programming time prior to erasure 16 360 µs Excludes system-level overhead 200 s Excludes system-level overhead 100,000 cycle Min Typ Max Sector Erase Time 1 Word Programming Time Chip Programming Time Erase/Program Cycle 47 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s PIN CAPACITANCE Parameter Symbol Input Capacitance CIN Conditions Value Unit Min Typ Max VIN = 0 V 11 14 pF Output Capacitance COUT VOUT = 0 V 12 16 pF Control Pin Capacitance CIN2 VIN = 0 V 14 16 pF WP/ACC Pin Capacitance CIN3 VIN = 0 V 21.5 26 pF Note: Test conditions TA = 25 °C, f = 1.0 MHz s HANDLING OF PACKAGE Please handle this package carefully since the sides of package are created acute angles. s CAUTION · The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when use autoselect and sector group protect function are used. Then the high voltage can be applied to RESET. · Without the high voltage (VID), sector group protection can be achieved by using "Extended Sector Group Protection" command. s ORDERING INFORMATION MB84LD23381 MB84LD23381 EJ 10 -PBS PACKAGE TYPE PBS = 101-ball FBGA SPEED OPTION See Product Selector Guide Device Revision DEVICE NUMBER/DESCRIPTION 64 Mega-bit (4 M × 16-bit) Dual Operation Flash Memory 2.5 V-only Read, Program, and Erase 16 Mega-bit (1 M × 16-bit) FCRAM 48 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s APPENDIX · ISB2s vs. VIN Cycle Time ISB2s vs VIN cycle time (VCCs = 2.7 V) 2.5 : RT = 25 °C : LT = -30 °C : HT = 85 °C ISB2s (mA) 2.0 1.5 1.0 0.5 0.0 0 200 400 600 800 1000 VIN cycle time (ns) 49 To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 s PACKAGE DIMENSION 101-ball plastic FBGA (BGA-101P-M01 BGA-101P-M01) 12.00±0.10(.472±.004) 0.20(.008) S A +0.15 1.25 0.10 +.006 (Mounting height) .049 .004 0.39±0.10 (Stand off) (.015±.004) B 0.40(.016) REF 0.80(.031) REF 12 11 10 9 8 7 6 5 4 3 2 1 0.80(.031) REF A 11.00±0.10 (.433±.004) 0.40(.016) REF 0.10(.004) S P N M L K J H G F E D C B A INDEX-MARK AREA 0.20(.008) S A S +0.10 101-Ø0.45 0.05 +.004 101-Ø.018 .002 0.08(.003) M S AB 0.10(.004) S C 50 2001 FUJITSU LIMITED B101001S-C-2-2 B101001S-C-2-2 Dimension in mm (inches) To Top / Lineup / Index MB84LD23381EJ-10 MB84LD23381EJ-10 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0110 F0110 © FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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