DS05-11406-1E MB81E161622-10-X/-12-X MB81E161622 -10-X -12-X FPT-54P-M02 A10/AP - Datasheet Archive

 

DATA SHEET DS05-11406-1E MEMORY CMOS 2 × 512 K × 16 Bit Single Data Rate I/F FCRAMTM(Extended Temp.Version)

 

FUJITSU SEMICONDUCTOR DATA SHEET DS05-11406-1E DS05-11406-1E MEMORY CMOS 2 × 512 K × 16 Bit Single Data Rate I/F FCRAMTM(Extended Temp.Version) Consumer/Embedded Application Specific Memory MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X CMOS 2-Bank × 524,288-Word × 16 Bit Fast Cycle Random Access Memory (FCRAM) with Single Data Rate s DESCRIPTION The Fujitsu MB81E161622 MB81E161622 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216 memory cells accessible in a 16-bit format. The MB81E161622 MB81E161622 features a fully synchronous operation referenced to a positive edge clock, whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81E161622 MB81E161622 is utilized using a Fujitsu advanced FCRAM core technology and designed to improve the random access performance and the complexity of controlling regular synchronous DRAM (SDRAM) which require many wait state due to long latency constraints. The MB81E161622 MB81E161622 is ideally suited for various embedded/consumer applications including digital AVs, printers and file storage where a large band width memory is needed. * : FCRAM is a trademark of Fujitsu Limited, Japan. s PRODUCT LINEUP MB81E161622 MB81E161622 Parameter -10-X -10-X -12-X -12-X 100 MHz Max. 84 MHz Max. CL = 1 15 ns Min. 20 ns Min. CL = 2 10 ns Min. 12 ns Min. CL = 1 10 ns Max. 14 ns Max. CL = 2 6 ns Max. 7 ns Max. 30 ns Min. 36 ns Min. 130 mA Max. 120 mA Max. Clock Frequency @CL = 2 Burst Mode Cycle Time Access Time From Clock RAS Cycle Time Operating Current (ICC1) Power Down Mode Current (ICC2P) 0.6 mA Max. MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s FEATURES · · · · Single +3.3 V Supply ±0.3 V tolerance LVTTL compatible I/O interface Two-bank operation Programmable burst type, burst length, and CAS latency · · · · 4 K refresh cycles every 32 ms Auto-refresh CKE power down mode Output Enable and Input Data Mask s PACKAGE 54-pin Plastic TSOP (II) Package Marking side (FPT-54P-M02 FPT-54P-M02) (Normal Bend) 2 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s PIN ASSIGNMENT TSOP (II) (TOP VIEW) < Normal Bend : FPT-54P-M02 FPT-54P-M02 > VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS NC BA A10/AP A10/AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE NC NC A9 A8 A7 A6 A5 A4 VSS (Marking side) s PIN DESCRIPTION Symbol Function VCC, VCCQ Supply Voltage VSS, VSSQ * Ground DQ0 to DQ15 Data I/O DQML, DQMU · Lower Byte : DQ0 to DQ7 · Upper Byte : DQ8 to DQ15 Input/Output Mask WE Write Enable CAS Column Address Strobe RAS Row Address Strobe CS Chip Select BA Bank Select AP Auto Precharge Enable A0 to A10 Address Input CKE Clock Enable CLK Clock Input NC · Row : A0 to A10 · Column : A0 to A7 No Connection *: These pins are connected internally in the chip. 3 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s BLOCK DIAGRAM Fig. 1 - MB81E161622 MB81E161622 BLOCK DIAGRAM To each block CLK CLOCK BUFFER CKE BANK-1 BANK-0 RAS CONTROL SIGNAL LATCH CS RAS CAS CAS COMMAND DECODER WE WE DRAM CORE (2,048 × 256 × 16) MODE REGISTER ROW ADDR. A0 to A9, A10/AP A10/AP BA ADDRESS BUFFER/ REGISTER & BANK SELECT 11 COL. ADDR. COLUMN ADDRESS COUNTER 8 I/O DQML, DQMU I/O DATA BUFFER/ REGISTER DQ0 to DQ15 16 VCC VCCQ VSS/VSSQ 4 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s FUNCTIONAL TRUTH TABLE *1 · COMMAND TRUTH TABLE *2, *3, *4 WE BA A10 (AP) A9, A8 A7 to A0 CKE Command Function n-1 n CS RAS CAS Device Deselect *5 DESL H X H X X X X X X X No Operation *5 NOP H X L H H H X X X X BST H X L H H L X X X X READ H X L H L H V L X V Burst Stop Read *6 Read with Auto-precharge *6 READA H X L H L H V H X V Write *6 WRIT H X L H L L V L X V Write with Auto-precharge *6 WRITA H X L H L L V H X V Bank Active *7 ACTV H X L L H H V V V V Precharge Single Bank *8 PRE H X L L H L V L X X Precharge All Banks *8 PALL H X L L H L X H X X *8, 9 MRS H X L L L L X X V V Mode Register Set *1: V = Valid, L = Logic Low, H = Logic High, X = either L or H. *2: All commands assume no CSUS command on previous rising edge of clock. *3: All commands are assumed to be valid state transitions. *4: All inputs are latched on the rising edge of the clock. *5: The NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will represent both NOP and DESL commands in later descriptions. *6: The READ, READA, WRIT and WRITA commands should be issued only after the corresponding bank has been activated (ACTV command) . Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION." *7: The ACTV command should be issued only after the corresponding bank has been precharged (PRE or PALL command) . *8: Required after power up. Refer to "POWER-UP INITIALIZATION" in section "s FUNCTIONAL DESCRIPTION." *9: The MRS command should be issued only after all banks have been precharged (PRE or PALL command) and DQ is in High-Z. Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION." 5 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X · DQM TRUTH TABLE Function CKE Command n-1 DQML n DQMU Data Write/Output Enable for Lower Byte ENBL L H X L X Data Write/Output Enable for Upper Byte ENBL U H X X L Data Mask/Output Disable for Lower Byte MASK L H X H X Data Mask/Output Disable for Upper Byte MASK U H X X H Note : DQML and DQMU control DQ0-7 and DQ8-15 DQ8-15, respectively. · CKE TRUTH TABLE Current State Bank Active Command Function Clock Suspend Mode Entry Any Clock Suspend Continue (Except Idle) CS RAS CAS WE BA A10 (AP) A9 to A0 n-1 n H L X X X X X X X L L X X X X X X X L H X X X X X X X H H L L L H X X X H L L H H H X X X H L H X X X X X X L H L H H H X X X L H H X X X X X X *1 CSUS *1 Clock Suspend Clock Suspend Mode Exit Idle Auto-refresh Command *2 REF Idle Power Down Entry *3 PD Power Down Power Down Exit CKE *1: The CSUS command requires that at least one bank is active. Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION." *2: The REF command should be issued only after all banks have been precharged (PRE or PALL command) . Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION." *3: The PD command should be issued only after the last read data have been appeared on DQ. 6 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X · OPERATION COMMAND TABLE (Applicable to single bank) Current CS RAS CAS WE Addr Command State Function H X X DESL NOP H H H X NOP NOP L H H L X BST NOP *1 L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV L L H L BA, AP PRE NOP L L H L AP PALL NOP *1 L L L H X REF Auto-refresh *3 L L L L MODE MRS Mode Register Set (Idle after tRSC) H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, AP READ/READA Begin Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP L L H H BA, RA ACTV L L H L BA, AP PRE Precharge L L H L AP PALL Precharge L L L H X REF Illegal L L L L MODE MRS Illegal H X X X X DESL NOP (Continue Burst to End Bank Active) L H H H X NOP NOP (Continue Burst to End Bank Active) L H H L X BST Burst Stop Bank Active L Bank Active X L Idle X H L H BA, CA, AP READ/READA Terminate Burst, New Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Terminate Burst, Start Write; Determine AP *4 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE Terminate Burst, Precharge Idle L L H L AP PALL Terminate Burst, Precharge Idle *1 L L L H X REF Illegal L L L L MODE MRS Illegal Read Bank Active after tRCD *3, *5 Illegal *2 *1 (Continued) 7 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Current State CS RAS CAS WE Addr Command Function H X X X X DESL NOP (Continue Burst to End Bank Active) L H H H X NOP NOP (Continue Burst to End Bank Active) L H H L X BST Burst Stop Bank Active L H L H BA, CA, AP READ/READA Terminate Burst, Start Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Terminate Burst, New Write; Determine AP L L H H BA, RA ACTV L L H L BA, AP PRE Terminate Burst, Precharge Idle L L H L AP PALL Terminate Burst, Precharge Idle L L L H X REF Illegal L L L L MODE MRS Illegal H X X X X DESL NOP (Continue Burst to End Precharge Idle) L H H H X NOP NOP (Continue Burst to End Precharge Idle) L H H L X BST Illegal L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE Illegal *2 L L H L AP PALL Illegal L L L H X REF Illegal L L L L MODE MRS Illegal Write Read with Autoprecharge Illegal *4 *2 *1 (Continued) 8 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Current State CS RAS CAS WE Addr Command Function H X DESL NOP (Continue Burst to End Precharge Idle) H H H X NOP NOP (Continue Burst to End Precharge Idle) H H L X BST Illegal L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE Illegal *2 L L H L AP PALL Illegal L L L H X REF Illegal L L L L MODE MRS Illegal H X X X X DESL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L X BST NOP (Idle after tRP) L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE NOP L L H L AP PALL NOP L L L H X REF Illegal L L L L MODE MRS Illegal H X X X X DESL NOP (Bank Active after tRCD) L H H H X NOP NOP (Bank Active after tRCD) L H H L X BST NOP (Bank Active after tRCD) *1 L Bank Activating X L Precharging X L Write with Autoprecharge X H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE Illegal *2 L L H L AP PALL Illegal L L L H X REF Illegal L L L L MODE MRS Illegal *1 (Continued) 9 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X (Continued) Current State CAS WE Addr Command H X X X X DESL NOP (Idle after tREFC) H H X X NOP/BST NOP (Idle after tREFC) L H L X X L L H X X ACTV/ PRE/PALL Illegal L L L X X REF/ MRS Illegal H X X X X DESL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L X BST Illegal L H L X X READ/READA/ Illegal WRIT/WRITA L Mode Register Setting RAS L Refreshing CS Function L X X X ACTV/PRE/ Illegal PALL/REF/MRS READ/READA/ Illegal WRIT/WRITA ABBREVIATIONS : RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge *1: Entry may affect other bank. *2: Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of that bank. *3: Illegal if any bank is not idle. *4: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to "TIMING DIAGRAM -11 & -12" in section "s TIMIMG DIAGRAMS." *5: The MRS command should be issued only when all DQ are in High-Z. Note: All entries in "OPERATION COMMAND TABLE" assume that the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence will be asserted after power shut down. 10 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X · COMMAND TRUTH TABLE FOR CKE Current CKE CKE CS RAS CAS State (n-1) (n) WE Addr Function H H H X X X X H L H H H X L L X X X X X NOP (Maintain Power Down Mode) H L L X X X Illegal H L H L X X Illegal H L H H X X Illegal H H H X X X V Refer to "Operation Command Table". H H L H X X V Refer to "Operation Command Table". H H L L H X V Refer to "Operation Command Table". H H L L L H X Auto-refresh H H L L L L V Refer to "Operation Command Table". H L H X X X X Power Down H L L H H H X Power Down H L L H H L X Illegal H L L H L X X Illegal H L L L H X X Illegal H L L L L L X Illegal L X X X X X X Invalid H H X X X X X Refer to "Operation Command Table". H L X X X X X Begin Clock Suspend next cycle L X X X X X X Invalid H X X X X X X Invalid L H X X X X X Exit Clock Suspend next cycle L Any State Other Than Listed Above X L Clock Suspend X L Read with Autoprecharge/ Write with Autoprecharge X L Bank Active Bank Activating Read/Write X L All Banks Idle X L Power Down X Invalid L X X X X X Maintain Clock Suspend L X X X X X X Invalid H H X X X X X Refer to "Operation Command Table". H L X X X X X Illegal Exit Power Down Mode Idle Note: All entries in "COMMAND TRUTH TABLE FOR CKE" are specified at CKE (n) state and CKE input from CKE (n-1) to CKE (n) state must satisfy the corresponding setup and hold time for CKE. 11 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s FUNCTIONAL DESCRIPTION SDRAM BASIC FUNCTION Three major differences between SDRAMs and conventional DRAMs are : a synchronized operation, a burst mode, and a mode register. The synchronized operation is the fundamental difference. An SDRAM uses a clock input for synchronization, while a DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of a DRAM is determined by their timing phase differences while each operation of the SDRAM is determined by commands and all operations are referenced to a rising edge of a clock. Fig 2 shows the basic timing diagram differences between SDRAMs and DRAMs. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to configure the SDRAM operation and function into desired system conditions. "s MODE REGISTER TABLE" shows how the SDRAM can be configured for system requirements by mode register programming. FCRAMTM The MB81E161622 MB81E161622 utilizes FCRAM core technology. The FCRAM is an acronym for Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs. CLOCK (CLK) and CLOCK ENABLE (CKE) All input and output signals of the SDRAM use register type buffers. A CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a rising edge of a CLK. All outputs are validated by the CLK. A CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged ) , the Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current. CHIP SELECT (CS) A CS enables all command inputs, RAS, CAS, WE and address inputs. When the CS is High, command signals are negated but internal operations such as a burst cycle will not be suspended. If such a control isn't needed, the CS can be tied to ground level. COMMAND INPUT (RAS, CAS and WE) Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operations, such as Row address strobe by RAS. Instead, each combination of RAS, CAS, and WE inputs in conjunction with CS input at the rising edge of the CLK determines SDRAM operations. Refer to "s FUNCTIONAL TRUTH TABLE." ADDRESS INPUT (A0 to A10) Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of nineteen address input signals are required to decode such a matrix. The SDRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV) , eleven Row addresses are initially latched and the remainder of eight Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or a Write command (WRIT or WRITA) . BANK SELECT (BA) This SDRAM has two banks and each bank contains 512 K words by 16-bit. Bank selection by A11 occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT or WRITA) , and precharge commands (PRE or PALL) . 12 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X DATA INPUTS AND OUTPUTS (DQ0 to DQ15) Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input : tRAC : from the bank active command when tRCD (Min.) is satisfied. (This parameter is reference only.) tCAC : from the read command when tRCD is greater than tRCD (Min.) at CL = 1. tAC : from the clock edge after tRAC and tCAC. The polarity of the output data is identical to that of input data. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH) . DATA I/O MASK (DQML/DQMU) DQML and DQMU are an active high enable input and have an output disable and input mask functions. During burst cycle and when DQML/DQMU = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on the burst type. BURST MODE OPERATION The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatically strobing column address. Access time and cycle time of Burst mode is specified as tCAC/tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and the burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required : Current Stage Next Stage Method (Assert the following command) Burst Read Burst Read Burst Read Burst Write Burst Write Burst Write Write Command Burst Write Burst Read Read Command Burst Read Precharge Precharge Command Burst Write Precharge Precharge Command Read Command 1st Step Mask Command (Normally 3 clock cycles) 2nd Step Write Command after lOWD BURST TYPE The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the least significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A0 through A2. If the first access of column address is even (0) , the next address will be odd (1) , or vice-versa. 13 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X X X 0 0-1 0-1 X X 1 1-0 1-0 0-1-2-3 0-1-2- 3 X 0 1 1-2-3-0 1-0-3-2 X 1 0 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 8 Interleave Mode 0 0 0 4 Sequential Mode X 1 1 2 Starting Column Address A2 A1 A0 X 0 0 Burst Length 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 FULL COLUMN BURST AND BURST STOP COMMAND (BST) The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address, then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read (READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge option is illegal during the full column burst operation. The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When a read mode is interrupted by the BST command, the output will be in High-Z. For the detailed rule, please refer to "TIMING DIAGRAM-8" in section "s TIMING DIAGRAMS." When a write mode is interrupted by the BST command, the data to be applied at the same time with the BST command will be ignored. PRECHARGE AND PRECHARGE OPTION (PRE, PALL) The SDRAM memory core is the same as a conventional DRAM's, requiring precharge and refresh operations. Precharge rewrites the bit line and reset the internal Row address line and is executed by the Precharge command (PRE) . With the Precharge command, the SDRAM will automatically be in standby state after precharge time (tRP) . The precharged bank is selected by combination of AP and BA when the Precharge command is asserted. If AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected by A11 is precharged (PRE) . The auto-precharge enters precharge mode at the end of burst mode of read or write without the Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to "s FUNCTIONAL TRUTH TABLE." 14 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X AUTO-REFRESH (REF) The Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates the Precharge command internally. All banks of the SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 7.8 µs or a total 4096 refresh commands within a 32 ms period. MODE REGISTER SET (MRS) The mode register of the SDRAM provides a variety of operations. The register consists of three operation fields; Burst Length, Burst Type, and CAS latency. Refer to "s MODE REGISTER TABLE." The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power) . The MRS command should be issued only when DQ is in High-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of the SDRAM. Refer to "POWER-UP INITIALIZATION" below. POWER-UP INITIALIZATION The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply the power and start the clock. Attempt to maintain either the NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs. 3. Precharge all banks by the Precharge (PRE) or Precharge All command (PALL) . 4. Assert minimum of 2 Auto-refresh commands (REF) . 5. Program the mode register by the Mode Register Set command (MRS) . In addition, it is recommended that DQM and CKE track VCC to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh commands (REF) . 15 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Fig. 2 - BASIC TIMING FOR CONVENTIONAL DRAM vs. SYNCHRONOUS DYNAMIC RAM < SDRAM > Active Read/Write Precharge CLK CKE H H H tHI tSI CS RAS CAS H : Read WE L : Write Address BA RA BA CA CAS Latency = 2 BA AP (A10) DQ Burst Length = 4 < Conventional DRAM > Row Address Select RAS CAS DQ 16 Column Address Select Precharge MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Fig. 3 - TIMING COMPARISON BETWEEN SDRAM AND SDR FCRAM 0 SDRAM tRC = 5 clock CL = 2 1 3 RD ACT 2 4 PRE 5 6 8 RD ACT 7 PRE Q ACT RDA ACT RDA Q tRC = 30 ns 10 ACT Q tRC = 75 ns SDR FCRAM tRC = 2 clock CL = 1 9 tRAC = 36 ns ACT RDA Q ACT RDA Q ACT RDA Q ACT Q tRAC = 25 ns Example of Random Cycle Operation @ 67 MHz 0 SDRAM tRC = 6 clock CL = 2 1 ACT 2 3 RD 4 5 PRE 6 7 ACT 8 9 RD PRE Q Q tRC = 60 ns SDR FCRAM tRC = 3 clock CL = 2 ACT RD PRE ACT tRAC = 37 ns RD PRE Q tRC = 30 ns 10 ACT RD Q PRE ACT RD Q tRAC = 26 ns Example of Random Cycle Operation @ 100 MHz 17 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Fig. 4 - STATE DIAGRAM (Simplified for Single BANK Operation State Diagram) MRS MODE REGISTER SET IDLE REF CKE CKE\ (PD) ACTV AUTO REFRESH POWER DOWN CKE\ (CSUS) BANK ACTIVE SUSPEND BANK ACTIVE CKE BST WRIT BST WRITA CKE\ (CSUS) WRITE SUSPEND READ WRIT READA READ WRIT CKE CKE WRITE WITH AUTO PRECHARGE PRE or PALL POWER ON PRE or PALL WRITA READA PRE or PALL CKE\ (CSUS) WRITE SUSPEND CKE\ (CSUS) READ WRITE WRITA READ CKE READA READ WITH CKE\ (CSUS) AUTO PRECHARGE CKE PRE or PALL PRECHARGE POWER APPLIED DEFINITION OF ALLOWS Manual Input Note: CKE\ means CKE goes Low-level from High-level 18 READ SUSPEND Automatic Sequence READ SUSPEND MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s BANK OPERATION COMMAND TABLE · MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION Second command (same bank) *3 MRS ACTV tRSC READ *3 tRSC WRIT WRITA PRE PALL REF BST tRSC READA tRSC tRSC tRSC First command MRS tRCD READA 1 tRCD tRAS tRAS *4 *3 *3 1 1 1 1 *3 1 READ tRCD tRCD *4 ACTV *3 *1 CL + BL CL + BL-1 WRITA *1 tWR 1 1 tDPL tDPL *3 tRP 1 *1 BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL *1, *2 PRE *1 *3 *3 tWR BL-1 + tDAL BL-1 + tDAL 1 CL + BL-1 CL + BL-1 CL + BL-1 *3 WRIT 1 *3 *1 tRP 1 1 tRP 1 *2 PALL tRP tRP 1 1 tRP 1 REF tREFC tREFC tREFC tREFC tREFC tREFC *1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: Assume tRAS (Min.) is satisfied. *4: Assume no I/O conflict. Illegal Command. 19 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X · MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION Second command (other bank) *4 MRS ACTV tRSC *4, *5 *4 *4, *5 READ READA WRIT WRITA PALL REF BST tRSC tRSC PRE tRSC tRSC tRSC First command MRS *1 *6 *6 *6 *6 *5, *6 *6 tRRD ACTV 1 1 1 1 1 tRAS *7 *7 *5 *5 1 1 1 1 1 1 *1, *3 READ READA 1 *1 *1, *3 *5 *5 *5, *7 *5, *7 *5 CL + BL 1 1 1 1 1 1 1 1 1 1 *1, *3 WRIT 1 *5 1 1 *1 CL + BL-1 CL + BL-1 *5 *5 1 tDPL *5 1 PRE *1 *1, *3 *5 *5 *5 *5 *5 BL-1 + tDAL 1 1 1 1 1 1 *1, *2 WRITA *1, *3 *6 *6 *6 *6 *5, *6 *6 *1 tRP 1 1 1 1 1 1 1 tRP tRP 1 1 tRP 1 tREFC tREFC tREFC tREFC tREFC *1 BL-1 + tDAL BL-1 + tDAL 1 *2 PALL REF tRP tREFC *1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: tRRD (Min.) of other bank (the second command will be asserted) is satisfied. *4: Assume other bank is in active, read or write state. *5: Assume tRAS (Min.) is satisfied. *6: Assume other banks are not in READA/WRITA state. *7: Assume no I/O conflict. Illegal Command. 20 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s MODE REGISTER TABLE MODE REGISTER SET BA A10 A9 A8 A7 0 0 0 0 A6 0 A5 A4 A3 CL A6 A5 A4 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A1 BT CAS Latency 0 0 0 0 1 1 1 1 A2 Reserved 1 2 Reserved Reserved Reserved Reserved Reserved A0 BL A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ADDRESS MODE REGISTER Burst Length BT = 0 BT = 1 * 1 2 4 8 Reserved Reserved Reserved Full Column Reserved 2 4 8 Reserved Reserved Reserved Reserved A3 Burst Type 0 1 Sequential (Wrap around, Binary-up) Interleave (Wrap around, Binary-up) *: BL = 1 and Full Column are not applicable to the interleave mode. 21 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Min. Unit Max. Voltage of VCC Supply Relative to VSS VCC, VCCQ -0.5 to +4.6 V Voltage at Any Pin Relative to VSS VIN, VOUT -0.5 to +4.6 V Short Circuit Output Current IOUT -50 to +50 mA Power Dissipation PD 1.3 W TSTG -55 to +125 °C Storage Temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Typ. Max. VCC, VCCQ 3.0 3.3 3.6 V VSS, VSSQ *1 Supply Voltage Min. 0 0 0 V Input High Voltage *2 VIH 2.0 VCC + 0.5 V Input Low Voltage *3 VIL -0.5 +0.8 V Ta -40 +85 °C Ambient Temperature *1 : All voltages are referenced to VSS. *3: Undershoot limit : *2: Overshoot limit : VIL (Min.) = VSS - 1.5 V for pulse width 5 ns acceptable, VIH (Max.) = 4.6 V for pulse width 5 ns acceptable, pulse width measured at 50% of pulse amplitude. pulse width measured at 50% of pulse amplitude. 4.6 V VIH 50% of pulse amplitude VIH VIH Min. VIL Pulse width < 5 ns VIL Max. VIL 50% of pulse amplitude Pulse width < 5 ns -1.5 V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 22 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s PIN CAPACITANCE (Ta = +25 °C, f = 1 MHz) Parameter Symbol Value Min. Typ. Max. Unit Input Capacitance, Except for CLK CIN1 2.5 5.0 pF Input Capacitance for CLK CIN2 2.5 4.0 pF I/O Capacitance CI/O 4.0 6.5 pF 23 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s ELECTRICAL CHARACTERISTICS 1. DC Characteristics (At recommended operating conditions unless otherwise noted.) Parameter Symbol Condition Value Min. Max. Unit Output High Voltage VOH (DC) IOH = -2 mA 2.4 V Output Low Voltage VOL (DC) IOL = 2 mA 0.4 V Input Leakage Current (Any Input) ILI 0 V VIN VCC; All other pins not under test = 0 V -5 +5 µA Output Leakage Current ILO 0 V VIN VCC; Data out disabled -5 +5 µA ICC1 Burst Length = 4 tRC = Min. for BL = 4 tCK = Min. One bank active Output pin open Addresses changed up to one time during tCK (Min.) 0 V VIN VIL Max. VIH Min. VIN VCC ICC2P CKE = VIL All banks idle, tCK = Min. Power down mode 0 V VIN VIL Max. VIH Min. VIN VCC 0.6 mA ICC2PS CKE = VIL, All banks idle CLK = VIH or VIL Power down mode 0 V VIN VIL Max. VIH Min. VIN VCC 0.6 mA ICC2N CKE = VIH , All banks idle tCK = 15 ns NOP command only, Input signals (except to CMD) are changed one time during 30 ns 0 V VIN VIL Max. VIH Min. VIN VCC 20 mA ICC2NS CKE = VIH All banks idle CLK = VIH or VIL Input signal are stable 0 V VIN VIL Max. VIH Min. VIN VCC 2 mA MB81E161622-10-X MB81E161622-10-X Operating Current (Average Power Supply Current) MB81E161622-12-X MB81E161622-12-X Precharge Standby Current (Power Supply Current) Precharge Standby Current (Power Supply Current) 130 mA 120 (Continued) 24 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X (Continued) Parameter Symbol Condition Value Unit Min. Max. ICC3P CKE = VIL Any bank active tCK = Min. 0 V VIN VIL Max. VIH Min. VIN VCC 1 mA ICC3PS CKE = VIL Any bank active CLK = VIH or VIL 0 V VIN VIL Max. VIH Min. VIN VCC 1 mA ICC3N CKE = VIH Any bank active tCK = 15 ns NOP command only, Input signals (except to CMD) are changed one time during 30 ns 0 V VIN VIL Max. VIH Min. VIN VCC 20 mA ICC3NS CKE = VIH Any bank active CLK = VIH or VIL Input signals are stable 0 V VIN VIL Max. VIH Min. VIN VCC 2 mA Active Standby Current (Power Supply Current) MB81E161622-10-X MB81E161622-10-X Burst mode Current (Average Power Supply Current) ICC4 MB81E161622-12-X MB81E161622-12-X Refresh Current #1 MB81E161622-10-X MB81E161622-10-X (Average Power Supply Current) MB81E161622-12-X MB81E161622-12-X ICC5 tCK = Min. Burst Length = 4 Output pin open All-banks active Gapless data 0 V VIN VIL Max. VIH Min. VIN VCC Auto-refresh; tCK = Min. tREFC = Min. 0 V VIN VIL Max. VIH Min. VIN VCC 100 mA 90 80 mA 70 Notes: · All voltages are referenced to VSS. · DC characteristics are measured after following the POWER-UP INITIALIZATION procedure. · ICC depends on output termination, load conditions, clock rate, number of address and/or command change within certain period. The specified values are obtained with the output open. 25 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X 2. AC Characteristics (At recommended operating conditions unless otherwise noted.) *1, *2, and *3 MB81E16162210-X MB81E16162210-X Parameter Symbol Min. Max. MB81E16162212-X MB81E16162212-X Min. Unit Max. CL = 1 tCK1 15 CL = 2 tCK2 10 Clock High Time *4 tCH 3 4 ns Clock Low Time *4 tCL 3 4 ns Input Setup Time *4 tSI 2 2 ns Input Hold Time except for CKE *4 tHI 1 1.5 ns RAS Access Time *5 tRAC 25 34 ns CAS Access Time *4, *6 tCAC 10 14 ns CL = 1 tAC1 14 ns CL = 2 tAC2 7 ns *4 tLZ ns CL = 1 tHZ1 14 ns CL = 2 tHZ2 7 ns *4, *6 tOH 1.5 1.5 ns *5 tREFI 7.8 7.8 µs tREF 32 32 ms Clock Period Access Time from Clock (tCK = Min.) *4, *6, *7 Output in Low-Z Output in High-Z *4, *8 Output Hold Time Time between Auto-Refresh command interval Time between Refresh 0 1.5 10 6 10 6 20 12 0 1.5 ns ns Transition Time tT 0.5 10 0.5 10 ns CKE Setup Time for Power Down Exit Time 26 *4 *4 tCKSP 3 3 ns MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X BASE VALUES FOR CLOCK COUNT/ LATENCY MB81E161622 MB81E161622 Parameter Symbol -10-X -10-X -12-X -12-X Unit Min. Max. Min. Max. tRC 30 36 ns RAS Precharge Time tRP 10 12 ns RAS Active Time tRAS 15 110000 20 110000 ns RAS to CAS Delay Time tRCD 10 12 ns Write Recovery Time tWR 10 12 ns RAS to RAS Bank Active Delay Time tRRD 10 12 ns Data-in to Precharge Lead Time tDPL 10 12 ns CL = 1 tDAL1 15 20 ns CL = 2 tDAL2 20 24 ns Refresh Cycle Time tREFC 50 60 ns Mode Resister Set Cycle Time tRSC 10 12 ns RAS Cycle Time Data-in to Active/ Refresh Command Period *9 CLOCK COUNT FORMULA Clock *10 Base Value Clock Period (Round up to a whole number) 27 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X LATENCY - FIXED VALUES (The latency values on these parameters are fixed regardless of clock period.) MB81E161622 MB81E161622 Parameter Symbol -10-X -10-X MB81E161622 MB81E161622 -12-X -12-X Unit CKE to Clock Disable lCKE 1 1 cycle DQM to Output in High-Z lDQZ 2 2 cycle DQM to Input Data Delay lDQD 0 0 cycle Last Output to Write Command Delay lOWD 2 2 cycle Write Command to Input Data Delay lDWD 0 0 cycle CL = 1 lROH1 1 1 cycle CL = 2 lROH2 2 2 cycle CL = 1 lBSH1 1 1 cycle CL = 2 lBSH2 2 2 cycle CAS to CAS Delay (Min.) lCCD 1 1 cycle CAS Bank Delay (Min.) lCBD 1 1 cycle Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay *1: AC characteristics are measured after following the POWER-UP INITIALIZATION procedure. *2: AC characteristics assume tT = 1 ns and 50 of terminated load. *3: 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (Min.) and VIL (Max.) . Refer to Fig. 5. *4: If input signal transition time (tT) is longer than 1 ns; [ (tT / 2) - 0.5] ns should be added to tCAC (Max.) , tAC (Max.) , tHZ (Max.) , and tCKSP (Min.) spec values, [ (tT / 2) - 0.5] ns should be subtracted from tLZ (Min.) , tHZ (Min.) , and tOH (Min.) spec values, and (tT - 1.0) ns should be added to tCH (Min.) , tCL (Min.) , tSI (Min.) , and tHI (Min.) spec values. *5: This value is for reference only. *6: Measured under AC test load circuit shown in Fig. 4. *7: tAC also specifies the access time at burst mode except for first access at CL = 1. *8: Specified where output buffer is no longer driven. *9: tRC (Min.) is not sum of tRAS (Min.) and tRP (Min.) . Actual clock count of tRC (lRC) must satisfy tRC (Min.) , tRAS (Min.) and tRP (Min.) . *10:All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula : clock count equals base value divided by clock period (round up to a whole number) . 28 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Fig. 5 - OUTPUT LOAD CIRCUIT R1 = 50 1.4 V Output CL = 30 pF LVTTL 29 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Fig. 6 - TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME tCK tCH tCL 2.4 V 1.4 V CLK 0.4 V tSI tHI 2.4 V Input (Control, Addr. & Data) 1.4 V 0.4 V tHZ tAC tOH tLZ 2.4 V Output 1.4 V 0.4 V Note : Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL. AC characteristics are also measured in this condition. Fig. 7 - TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT CLK H or L 1 clock (Min.) tCKSP (Min.) CKE Command 30 H or L NOP NOP ACTV MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X Fig. 8 - TIMING DIAGRAM, PULSE WIDTH CLK tRC, tRP, tRAS, tRCD, tWR, tREFI, tREFC, Input (Control) tDPL, tDAL, tRSC, tRRD, tCKSP Command Command Note : These parameters are a limit value of the rising edge of the clock from one command input to the next input. tCKSP is the latency value from the rising edge of the CKE. Measurement reference voltage is 1.4 V. Fig. 9 - TIMING DIAGRAM, ACCESS TIME CLK tRAC RAS tRCD tCAC CAS tAC tAC tAC Q (Valid) Q (Valid) 1 clock at CL = 2 DQ (Output) Q (Valid) 31 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s TIMING DIAGRAMS TIMING DIAGRAM - 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4) CLK tSI tHI tSI tHI tSI tHI CKE *1 lCKE (1 clock) CLK (Internal) 1 lCKE (1 clock)* *2 *2 DQ (Read) Q1 DQ (Write) Q2 NOT *3 WRITTEN D1 *2 (NO CHANGE) D2 Q3 *2 (NO CHANGE) NOT *3 WRITTEN Q4 D3 D4 *1: The latency of the CKE (lCKE) is one clock. *2: During the read mode, burst counter will not be incremented/decremented at the next clock of the CSUS command. Output data remains the same data. *3: During the write mode, data at the next clock of the CSUS command is ignored. TIMING DIAGRAM - 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT CLK tCKSP (Min.) 1 clock (Min.) CKE Command 1 NOP * 2 PD (NOP) * H or L 3 NOP * NOP * 3 4 ACTV * tREF (Max.) *1: The Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2: The Precharge command can be posted in conjunction with CKE after the last read data has been appeared on DQ. *3: It is recommended to apply the NOP command in conjunction with CKE. *4: The ACTV command can be latched after tCKSP (Min.) + 1 clock (Min.) . 32 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY CLK RAS lCCD (1 clock) tRCD (Min.) lCCD lCCD lCCD CAS Address ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS Note : CAS to CAS delay can be one or more clock period. TIMING DIAGRAM - 4 : DIFFERENT BANK ADDRESS INPUT DELAY CLK tRRD (Min.) RAS lCBD (1 clock) tRCD (Min.) or more lCBD CAS tRCD (Min.) Address ROW ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS A11 (BA) Bank 0 Bank 1 Bank 0 Bank 1 Bank 0 Bank 1 Note : CAS Bank delay can be one or more clock period. 33 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 5 : DQMU, DQML - INPUT MASK AND OUTPUT DISABLE (@ BL = 4) CLK DQML, DQMU (@ Read) IDQZ (2 clocks) DQ (@ Read) Q1 Q2 High-Z Q4 End of burst DQML, DQMU (@ Write) IDQD (same clock) DQ (@ Write) D1 MASKED D3 D4 End of burst TIMING DIAGRAM - 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK) CLK tRAS (Min.) Command ACTV Note : PRECHARGE means `PRE' or `PALL'. 34 PRECHARGE MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4) CLK Command PRECHARGE IROH (2 clocks) High-Z DQ Command Q1 PRECHARGE IROH (2 clocks) DQ Q1 Command Q2 High-Z PRECHARGE IROH (2 clocks) DQ Q1 Q2 Command High-Z Q3 PRECHARGE No effect (end of burst) DQ Q1 Q2 Q3 Q4 Notes : In case of CL = 1, the lROH is 1 clock. In case of CL = 2, the lROH is 2 clocks. PRECHARGE means `PRE' or `PALL'. 35 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column) CLK Command (CL = 1) BST IBSH (1 clock) High-Z DQ Qn - 2 Qn - 1 Command (CL = 2) Qn BST IBSH (2 clocks) Qn - 2 DQ Qn - 1 Qn Qn + 1 High-Z TIMING DIAGRAM - 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2) CLK BST Command DQ 36 LAST Dn Masked by BST COMMAND MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 10 : WRITE INTERRUPTED BY PRECHARGE CLK tDPL (Min.) DQ ACTV PRECHARGE Command Dn - 1 LAST Dn tRP (Min.) MASKED by Precharge Note : The precharge command (PRE) should be issued only after the tDPL of final data input is satisfied. PRECHARGE means `PRE' or `PALL'. TIMING DIAGRAM - 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 2, BL = 4) CLK IOWD (2 clocks) Command DQM (DQML, DQMU) DQ READ WRIT *1 *2 *3 IDQZ (2 clocks) IDWD (same clock) Q1 Masked D1 D2 *1: The First DQM makes high-impedance state High-Z between the last output and the first input data. *2: The Second DQM makes internal output data mask to avoid bus contention. *3: The Third DQM in illustrated above also makes internal output data mask. If burst read ends (the final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention. 37 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 1, BL = 4) CLK tWR (Min.) WRIT Command READ DQM (DQML, DQMU) tCAC (Max.) DQ D1 D2 D3 Masked by READ tAC Q1 tAC Q2 Notes : The Read command should be issued after tWR of the final data input is satisfied. The write data after the READ command is masked by the READ command. TIMING DIAGRAM - 13 : READ WITH AUTO-PRECHARGE (EXAPLE @ CL = 2, BL = 2 Applied to same bank) CLK Command ACTV READA NOP or DESL ACTV CL + BL - 1 * DQM (DQML, DQMU) DQ Q1 Q2 *: The Next ACTV command should be issued after CL + BL - 1 from the READA command. 38 tAC Q3 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 14 : WRITE WITH AUTO-PRECHARGE *1, *2, *3 (EXAMPLE @ CL = 2, BL = 2 Applied to same bank) CLK tDAL (Min.) (BL - 1) + tDAL*4 Command ACTV WRITA NOP or DESL ACTV DQM (DQML, DQMU) DQ D1 D2 *1: If the final data is masked by DQM, the precharge does not start at the clock of the final data input. *2: Once the auto precharge command is asserted, no new command within the same bank can be issued. *3: The Auto-precharge command can not be invoked at full column burst operation. *4: The Next command should be issued after (BL - 1) + tDAL from the WRITA command. TIMING DIAGRAM - 15 : AUTO-REFRESH TIMING CLK Command REF *1 NOP *3 NOP *4 NOP REF tREFC (Min.) BA H or L*2 NOP Command *4 tREFC (Min.) H or L*2 BA *1: All banks should be precharged prior to the first Auto-refresh command (REF) . *2: Bank select is ignored at the REF command. The refresh address and bank select are selected by the internal refresh counter. *3: Either the NOP or DESL command should be asserted within tRC period during Auto-refresh mode. *4: Any activation command such as the ACTV or MRS commands other than the REF command should be asserted after tREFC from the last REF command. 39 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X TIMING DIAGRAM - 16 : MODE REGISTER SET TIMING CLK tRSC (Min.) Command Address MRS MODE NOP or DESL ACTV ROW ADDRESS Note : The Mode Register Set command (MRS) should be asserted only after all banks have been precharged and DQ is in High-Z. 40 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s ORDERING INFORMATION Part Number MB81E161622-10FH-X MB81E161622-10FH-X MB81E161622-12FH-X MB81E161622-12FH-X Package Remarks 54 pin, Plastic TSOP (II) (FPT-54P-M02 FPT-54P-M02) 41 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X s PACKAGE DIMENSION 54-pin plastic TSOP (II) (FPT-54P-M02 FPT-54P-M02) Note1)Resin protrusion. (Each side : 0.15 (.006) MAX) Note2)Pins width and pins thickness include plating thickness. 54 28 Details of "A" part 0.25(.010) 0°~8° INDEX LEAD No. 1 0.45/0.75 (.018/.030) 27 * 22.22±0.10(.875±.004) 0.32 .013 +0.08 ­0.07 +.003 ­.003 0.16(.006) M 1.15±0.05 (.045±.002) (Mounting height) 11.76±0.20(.463±.008) 10.16±0.10(.400±.004) "A" +0.05 0.80(.031) 0.145 ­0.03 20.80(.819)REF C +.002 0.10(.004) .006 ­.001 0.10±0.05 (.004±.002) (Stand off) 2000 FUJITSU LIMITED F54003S-c-2-3 Dimensions in mm (inches) 42 MB81E161622-10-X/-12-X MB81E161622-10-X/-12-X FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0112 F0112 © FUJITSU LIMITED Printed in Japan