DS05-11239-1E MB8504E036AA-60/-70 MB8504E036AA MB8117405A MB814105C - Datasheet Archive

 

FUJITSU SEMICONDUCTOR DATA SHEET DS05-11239-1E MEMORY 4 M × 36 BIT HYPER PAGE MODE DRAM MODULE MB8504E036AA-60/-70 4M

 

To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-11239-1E DS05-11239-1E MEMORY 4 M × 36 BIT HYPER PAGE MODE DRAM MODULE MB8504E036AA-60/-70 MB8504E036AA-60/-70 4M × 36 BIT Hyper Page Mode DRAM Module, 5 V, 1-Bank s DESCRIPTION The Fujitsu MB8504E036AA MB8504E036AA is a fully decoded, CMOS Dynamic Random Access Memory (DRAM) module consisting of eight MB8117405A MB8117405A and four MB814105C MB814105C devices. The MB8504E036AA MB8504E036AA is optimized for those applications requiring high speed, high performance and large memory storage. The operation and electrical characteristics of the MB8504E036AA MB8504E036AA are the same as the MB8117405A MB8117405A which features hyper page mode operation providing extended valid time for data output and higher speed random access of upto 2,048-bit of data within the same row than the fast page mode. For ease of memory expansion, the MB8504E036AA MB8504E036AA is offered in a 72-pad Single In-line Memory Module package (SIMM). s PRODUCT LINE & FEATURES Parameter MB8504E036AA-60 MB8504E036AA-60 MB8504E036AA-70 MB8504E036AA-70 RAS Access Time 60 ns max. 70 ns max. Random Cycle Time 104 ns min. 124 ns min. Address Access Time 30 ns max. 35 ns max. CAS Access Time 15 ns max. 20 ns max. Hyper Page Mode Cycle Time 25 ns min. 30 ns min. 5962 mW max. 5148 mW max. Power Dissipation Operating Mode Standby Mode · Organization : 4,194,304 words × 36 bits · Memory : MB8117405A MB8117405A, 8 pcs MB814105C MB814105C, 4 pcs · 5.0 V ± 10% Supply Voltage · 2,048 Refresh Cycles / 32.8 ms · Hyper page mode operation (EDO) 66 mW (CMOS) / 132 mW (TTL) · Package and Ordering Information: 72-pin SIMM, order as MB8504E036AA-xxSG (SG = Gold Pad) MB8504E036AA-xxSS (SS = Solder Pad) To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 s ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit Supply Voltage VCC ­0.5 to +7.0 V Input Voltage VIN ­0.5 to +7.0 V Output Voltage VOUT ­0.5 to +7.0 V Short Circuit Output Current IOUT ±50 mA Power Dissipation PD 12 W TSTG ­55 to +125 °C Storage Temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s PACKAGE DQ0 DQ1 DQ2 DQ3 VCC A0 A2 A4 A6 DQ4 DQ5 DQ6 DQ7 A7 VCC A9 RAS2 DQ8 Plastic SIMM Package (MSS-72P-P81 MSS-72P-P81) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 VSS DQ18 DQ19 DQ20 DQ21 N.C. A1 A3 A5 A10 DQ22 DQ23 DQ24 DQ25 N.C. A8 N.C. DQ26 DQ35 CAS0 CAS3 RAS0 N.C. N.C. DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 N.C. PD2 PD4 VSS 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DQ17 VSS CAS2 CAS1 N.C. WE DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 PD1 PD3 N.C. -60 -70 67 PD1 VSS VSS 68 69 70 PD2 PD3 PD4 N.C. N.C. N.C. N.C. VSS N.C. Pin # Symbol 2 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 FUNCTIONAL BLOCK DIAGRAM CAS RAS OE CAS0 RAS0 CAS RAS OE CAS RAS W CAS RAS OE CAS RAS OE CAS RAS W CAS RAS OE CAS RAS OE CAS RAS CAS RAS OE CAS RAS OE CAS RAS DQ4 DQ5 DQ6 DQ7 DIN DOUT A0 to A10 DQ8 I/O I/O I/O A0 to A10 I/O DQ9 DQ10 DQ11 DQ12 I/O I/O I/O A0 to A10 I/O DQ13 DQ14 DQ15 DQ16 CHIP 03 W CHIP 04 W CHIP 05 DIN DOUT A0 to A10 DQ17 I/O I/O I/O A0 to A10 I/O DQ18 DQ19 DQ20 DQ21 I/O I/O I/O A0 to A10 I/O DQ22 DQ23 DQ24 DQ25 CHIP 06 W CHIP 07 W CHIP 08 W CAS3 I/O I/O I/O A0 to A10 I/O CHIP 02 W CAS2 RAS2 DQ0 DQ1 DQ2 DQ3 CHIP 01 W CAS1 I/O I/O I/O A0 to A10 I/O CHIP 00 DIN DOUT A0 to A10 DQ26 I/O I/O I/O A0 to A10 I/O DQ27 DQ28 DQ29 DQ30 I/O I/O I/O A0 to A10 I/O DQ31 DQ32 DQ33 DQ34 CHIP 09 W CHIP 10 W CHIP 11 W DIN DOUT A0 to A10 DQ35 WE A0 to A10 VCC VSS C0 to 11 CHIPS 00 to 11 CHIPS 00 to 11 3 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 s RECOMMENDED OPERATING CONDITION (Referenced to VSS) Parameter Symbol Min. Typ. Max. Unit Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS - 0 - V Input High Voltage, all inputs VIH 2.4 - 6.5 V Input Low Voltage, all inputs* VIL ­0.3 - 0.8 V Ambient Temperature TA 0 - 70 °C * : Undershoots of up to ­2.0 volts with a pulse width not exceeding 10 ns are acceptable WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 4 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 s DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Notes Output High Voltage Output Low Voltage Symbol *1 *1 VOH VOL IOH = ­5.0 mA IOL = 4.2 mA II(L) 0 V VIN VCC, 4.5 V VCC 5.5 V, VSS = 0 V, All other pins not under test = 0 V RAS Input Leakage Current CAS Address, WE IO(L) 0 V VOUT 5.5 V, Data out disabled ICC1 Output Leakage Current RAS & CAS cycling, tRC = min MB8504E036AA-60 MB8504E036AA-60 Operating Current (Average power supply current) Condition *2 MB8504E036AA-70 MB8504E036AA-70 TTL Level Standby Current (Power supply current) ICC2 CMOS Level MB8504E036AA-60 MB8504E036AA-60 Refresh Current#1 (Average power supply current) *2 Hyper Page Mode Current *2 Refresh Current#2 (Average power supply current) *2 ICC3 MB8504E036AA-70 MB8504E036AA-70 RAS = CAS = VIH RAS = CAS VCC ­0.2 V CAS = VIH, RAS = cycling, tRC = min Value Min. Max. 2.4 - - 0.4 ­40 30 ­80 80 ­20 20 - 1084 - 936 - 24 - 12 - 1084 - 936 µA µA mA mA mA ICC4 RAS = VIL, CAS = cycling, tHPC = min - - 984 860 RAS cycling, CAS-before-RAS, tRC = min - 1036 ICC5 MB8504E036AA-60 MB8504E036AA-60 MB8504E036AA-70 MB8504E036AA-70 V V 40 ­30 Unit MB8504E036AA-60 MB8504E036AA-60 MB8504E036AA-70 MB8504E036AA-70 mA mA - 896 Notes: *1. Referenced to VSS. *2. ICC depends on the output load conditions and cycle rate. The specific values are obtained with the output open. ICC depends on the number of address change as RAS = VIL and CAS = VIH, VIL > ­0.3 V. ICC1, ICC3, ICC4 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC2 is specified during RAS = VIH and VIL > ­0.3 V. s CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5.0 V) Parameter Symbol Typ. Max. Unit Input Capacitance, A0 to A10 CIN1 - 85 pF Input Capacitance, RAS0 and RAS2 CIN2 - 46 pF Input Capacitance, CAS0 to CAS3 CIN3 - 27 pF Input Capacitance, WE CIN4 - 83 pF I/O Capacitance, (DQ0-7, DQ9-16 DQ9-16, DQ18-25 DQ18-25, DQ27-34 DQ27-34) CDQ1 - 12 pF I/O Capacitance, (DQ8, DQ17, DQ26, DQ35) CDQ2 - 13 pF 5 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 s AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3 No. Parameter Notes Symbol MB8504E036EAA-60 MB8504E036EAA-60 MB8504E036EAA-70 MB8504E036EAA-70 Min. Max. Min. Max. Unit 1 Time Between Refresh tREF - 32.8 - 32.8 ms 2 Random Read/Write Cycle Time tRC 104 - 124 - ns 3 Access Time from RAS *4,7 tRAC - 60 - 70 ns 4 Access Time from CAS *5,7 tCAC - 15 - 20 ns 5 Column Address Access Time *6,7 tAA - 30 - 35 ns 6 Output Hold Time tOH 5 - 5 - ns 7 Output Hold Time from CAS tCHC 5 - 5 - ns 8 Output Buffer Turn On Delay Time tON 0 - 0 - ns 9 Output Buffer Turn Off Delay Time *8 tOFF - 15 - 17 ns 10 Output Buffer Turn Off Delay Time from RAS *8 tOFR - 15 - 17 ns 11 Output Buffer Turn Off Delay Time from WE *8 tWEZ - 15 - 17 ns 12 Transition Time tT 1 50 1 50 ns 13 RAS Precharge Time tRP 40 - 50 - ns 14 RAS Pulse Width tRAS 60 100000 70 100000 ns 15 RAS Hold Time tRSH 15 - 20 - ns 16 CAS to RAS Precharge Time tCRP 5 - 5 - ns 17 CAS to RAS Delay Time tRCD 14 45 14 53 ns 18 CAS Pulse Width tCAS 10 - 13 - ns 19 CAS Hold Time tCSH 40 - 50 - ns 20 CAS Precharge Time (Normal) tCPN 10 - 10 - ns 21 Row Address Set Up Time tRSR 0 - 0 - ns 22 Row Address Hold Time tRAH 10 - 10 - ns 23 Column Address Set Up Time tASC 0 - 0 - ns 24 Column Address Hold Time tCAH 10 - 10 - ns 25 Column Address Hold Time from RAS tAR 24 - 24 - ns 26 RAS to Column Address Delay Time tRAD 12 30 12 35 ns 27 Column Address to RAS Lead Time tPAL 30 - 35 - ns 28 Column Address to CAS Lead Time tCAL 23 - 28 - ns 29 Read Command Set Up Time tRCS 0 - 0 - ns 30 Read Command Hold Time Referenced to RAS *12 tRRH 0 - 0 - ns 31 Read Command Hold Time Referenced to CAS *12 tRCH 0 0 - ns *9,10 *15 *11 (Continued) 6 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 (Continued) No. Parameter Notes *13 Symbol MB8504E036EAA-60 MB8504E036EAA-60 MB8504E036EAA-70 MB8504E036EAA-70 Unit Min. Max. Min. Max. tWCS 0 - 0 - ns 32 Write Command Set Up Time 33 Write Command Hold Time tWCH 10 - 10 - ns 34 Write Command Hold Time from RAS tWCR 24 - 24 - ns 35 WE Pulse Width tWP 10 - 10 - ns 36 Write Command to RAS Lead Time tRWL 15 - 18 - ns 37 Write Command to CAS Lead Time tCWL 10 - 13 - ns 38 DIN Set Up Time tDS 0 - 0 - ns 39 DIN Hold Time tDH 10 - 10 - ns 40 Date Hold Time from RAS tDHR 24 - 24 - ns 41 RAS Precharge Time to CAS Active Time (Refresh Cycles) tRPC 5 5 - ns 42 CAS Set Up Time (C-B-R Refresh) tCSR 0 - 0 - ns 43 CAS Hold Time (C-B-R Refresh) tCHR 10 - 12 - ns 44 WE Set Up Time from RAS *16 tWSR 0 - 0 - ns 45 WE Hold Time from RAS *16 tWHR 10 - 10 - ns 46 RAS to Data In Delay Time tRDD 15 - 17 - ns 47 CAS to Data In Delay Time tCDD 15 - 17 - ns 48 DIN to CAS Delay Time tDZC 0 - 0 - ns 49 WE Precharge Time tWPZ 8 - 8 - ns 50 WE to Data In Delay Time tWED 15 - 17 - ns 51 Hyper Page Mode RAS Pulse Width tRASP - 100000 - 100000 ns 52 Hyper Page Mode Read/Write Cycle Time tHPC 25 - 30 - ns 53 Access Time from CAS Precharge tCPA - 35 - 40 ns 54 Hyper Page Mode CAS Precharge Time tCP 10 - 10 - ns 55 Hyper Page Mode RAS Hold Time from CAS Precharge tRHCP 35 - 40 - ns *7,14 7 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 Notes: *1. An initial pause (RAS = CAS = VIH) of 200 µs is required after power-up followed by any eight RAS -only cycles before proper device operation is achieved. If an internal refresh counter is used, a minimum of eight CAS-before-RAS initialization cycles are required instead of eight RAS cycles. *2. AC characteristics assume tT = 5 ns. *3. VIH (min) and VIL (max) are reference levels for measureing the timing of input signals. Transition times are measured between VIH (min) and VIL (max). *4. Assumes that tRCD tRCD (max), tRAD tRAD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. *5. If tRCD tRCD (max), tRAD tRAD (max), and tASC tAA- tCAC - tT, access time is tCAC. *6. If tRAD tRAD (max) and tASC tAA - tCAC - tT, access time is tAA. *7. Measured with a load equivalent to two TTL loads and 100 pF. *8. tOFF, tOFR and tWEZ are specified that output buffer change to high impedance state. *9. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC or tAA. *10. tRCD (min) = tRAH (min)+ 2 tT + tASC (min). *11. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled exclusively by tCAC or tAA. *12. Either tRRH or tRCH must be satisfied for a read cycle. *13. tWCS is specified as a reference point only. If tWCS tWCS (min) the data output pin will remain High-Z state through entire cycle. *14. tCPA is access time from the selection of a new column address (caused by changing CAS from "L" to "H"). Therefore, if tCP become long, tCPA also become longer than tCPA (max). *15. Assumes that CAS-before-RAS refresh. *16. Assumes that test mode function. *Source: See MB8117405A MB8117405A Data Sheet for details on the electricals. 8 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 s PACKAGE DIMENSIONS 72-PAD 72-PAD PLASTIC SINGLE IN-LINE TYPE MODULE (CASE No.: MSS-72P-P81 MSS-72P-P81) 107.95±0.13 (4.250±.005) 101.19±0.10 (3.984±.004) 8.89(.350)MAX Resistor mounting area.* 6.35±0.13 (.250±.005) 10.16±0.08 (.400±.003) 25.27±0.13 (.995±.005) 1 "A" 2.03±0.13 (.080±.005) 6.35±0.13 (.250±.005) Pin No.1 INDEX R1.57±0.05 1.27±0.03 (R.062±.002) (.050±.001) 44.45±0.05 6.35±0.03 (1.750±.002) (.250±.001) 95.25±0.05 (3.750±.002) 5.72(.225)MIN +0.10 1.27 ­0.08 +.004 .050 ­.003 R1.57±0.05 (R.062±.002) Ø3.18±0.05 (Ø.125±.002) C 1995 FUJITSU LIMITED M72082SC-1-1 M72082SC-1-1 Details of "A" part 1.04(.041)TYP 2.54(.100)MIN 0.25(.010)MAX Dimension in mm (inches) 9 To Top / Lineup / Index MB8504E036AA-60/-70 MB8504E036AA-60/-70 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9704 F9704 © FUJITSU LIMITED Printed in Japan 10