DS05-10191-2E MB81V4265S-60/-70/-60L/-70L MB81V4265S LCC-40P-M01 FPT-44P-M07 - Datasheet Archive

 

FUJITSU SEMICONDUCTOR DATA SHEET DS05-10191-2E MEMORY CMOS 256 K × 16 BITS HYPER PAGE MODE DYNAMIC RAM

 

To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-10191-2E DS05-10191-2E MEMORY CMOS 256 K × 16 BITS HYPER PAGE MODE DYNAMIC RAM MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L CMOS 262,144 × 16 BITS Hyper Page Mode Dynamic RAM s DESCRIPTION The Fujitsu MB81V4265S MB81V4265S is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory cells accessible in 16-bit increments. The MB81V4265S MB81V4265S features the "hyper page" mode of operation which provides extended valid time for data output and higher speed random access of up to 512 × 16-bits of data within the same row than the fast page mode. The MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L DRAMs are ideally suited for memory applications such as embedded control, buffer, portable computers, and video imaging equipment where very low power dissipation and high bandwidth are basic requirements of the design. The MB81V4265S MB81V4265S is fabricated using silicon gate CMOS and Fujitsu's advanced four-layer polysilicon process. This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. s PRODUCT LINE & FEATURES Parameter RAS Access Time CAS Access Time Address Access Time Random Cycle Time Hyper Page Mode Cycle Time Operating Current Low Power LVTTL Level Standby Dissipation Current CMOS Level · 262,144 words × 16 bits organization · Silicon gate, CMOS, Advanced Stacked Capacitor Cell · All input and output are LVTTL compatible · 512 refresh cycles every 8.2 ms · 9 rows × 9 columns, addressing scheme · Self refresh function MB81V4265S MB81V4265S -60L -70 -60 60 ns max. 20 ns max. 30 ns max. 104 ns min. 25 ns min. 378 mW max. 7.2 mW 3.6 mW 3.6 mW 540 µW · · · · · -70L 70 ns max. 20 ns max. 35 ns max. 119 ns min. 30 ns min. 335 mW max. 7.2 mW 3.6 mW 3.6 mW 540 µW Standard and low power versions Early Write or OE controlled Write capability RAS-only, CAS-before-RAS, or Hidden Refresh Hyper page mode, Read-Modify-Write capability On chip substrate bias generator for high performance 1 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L s ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit VIN, VOUT ­0.5 to +4.6 V Voltage of VCC Supply Relative to VSS VCC ­0.5 to +4.6 V Power Dissipation PD 1.0 W Short Circuit Output Current IOUT ­50 to +50 mA Storage Temperature TSTG ­55 to +125 °C Temperature under Bias TBIAS 0 to +70 °C Voltage at Any Pin Relative to VSS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s PACKAGE Plastic SOJ Package Plastic TSOP (II) Package Marking side (LCC-40P-M01 LCC-40P-M01) (FPT-44P-M07 FPT-44P-M07) (Normal Bend) Package and Ordering Information ­ 40-pin plastic (400 mil) SOJ, order as MB81V4265S- MB81V4265S-××PJ and MB81V4265S- MB81V4265S-××LPJ (Low Power) ­ 44-pin plastic (400 mil) TSOP (II) with normal bend leads, order as MB81V4265S- MB81V4265S-××PFTN and MB81V4265S- MB81V4265S-××LPFTN (Low Power) 2 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 1 ­ MB81V4265S MB81V4265S DYNAMIC RAM - BLOCK DIAGRAM RAS Clock Gen #1 LCAS UCAS Write Clock Gen WE Mode Control Clock Gen #2 Data In Buffer A0 Column Decoder A1 A2 Address Buffer & PreDecoder A3 A4 DQ1 to DQ16 Sense Ampl & I/O Gate A5 Row Decoder A6 A7 4,194,304 Bit Storage Cell Data Out Buffer A8 Refresh Address Counter OE Substrate Bias Gen VCC VSS s CAPACITANCE (TA = 25°C, f = 1 MHz) Parameter Symbol Typ. Max. Unit Input Capacitance, A0 to A8 CIN1 - 5 pF Input Capacitance, RAS, LCAS, UCAS, WE, OE CIN2 - 5 pF Input/Output Capacitance, DQ1 to DQ16 CDQ - 7 pF 3 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L s PIN ASSIGNMENTS AND DESCRIPTIONS 44-Pin TSOP (II) (TOP VIEW) 40-Pin SOJ (TOP VIEW) VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 N.C. N.C. WE RAS N.C. A0 A1 A2 A3 VCC Designator A0 to A8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 N.C. LCAS UCAS OE A8 A7 A6 A5 A4 VSS Function Address inputs row : A0 to A8 column : A0 to A8 refresh : A0 to A8 RAS Row address strobe LCAS Lower column address strobe UCAS Upper column address strobe WE Write enable OE Output enable DQ1 to DQ16 Data Input/ Output VCC Circuit ground N.C. 4 +3.3 volt power supply VSS No connection VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 1 2 3 1 Pin Index 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 N.C. N.C. WE RAS N.C. A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 (Marking side) 32 31 30 29 28 27 26 25 24 23 N.C. LCAS UCAS OE A8 A7 A6 A5 A4 VSS To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L s RECOMMENDED OPERATING CONDITIONS Parameter Notes Supply Voltage *1 Input High Voltage, all inputs Input Low Voltage, all inputs* *1 *1 Symbol Min. Typ. Max. VCC VSS VIH VIL 3.0 0 ­2.0 ­0.3 3.3 0 - - 3.6 0 VCC+0.3 0.8 Unit Ambient Operating Temp. V V V 0°C to +70°C * : Undershoots of up to ­2.0 volts with a pulse width not exceeding 20 ns are acceptable. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. s FUNCTIONAL OPERATION ADDRESS INPUTS Eighteen input bits are required to decode any sixteen of 4,194,304 cell addresses in the memory matrix. Since only nine address bits (A0 to A8) are available, the column and row inputs are separately strobed by LCAS or UCAS and RAS as shown in Figure 1. First, nine row address bits are input on pins A0-through-A8 and latched with the row address strobe (RAS) then, nine column address bits are input and latched with the column address strobe (LCAS or UCAS). Both row and column addresses must be stable on or before the falling edges of RAS and LCAS or UCAS, respectively. The address latches are of the flow-through type; thus, address information appearing after tRAH (min) + tT is automatically treated as the column address. WRITE ENABLE The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored. DATA INPUT Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The falling edge of WE or LCAS / UCAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data of DQ1 to DQ8 is strobed by LCAS and DQ9 to DQ16 is strobed by UCAS and the setup/hold times are referenced to each LCAS and UCAS because WE goes Low before LCAS / UCAS. In a delayed write or a read-modify-write cycle, WE goes Low after LCAS / UCAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal. DATA OUTPUT The three-state buffers are LVTTL compatible with a fanout of one TTL load. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under the following conditions: tRAC : from the falling edge of RAS when tRCD (max) is satisfied. tCAC : from the falling edge of LCAS (for DQ1 to DQ8) UCAS (for DQ9 to DQ16) when tRCD is greater than tRCD (max). tAA : from column address input when tRAD is greater than tRAD (max), and tRCD (max) is satisfied. tOEA : from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA. tOEZ : from OE inactive. tOFF : from CAS inactive while RAS inactive. tOFR : from RAS inactive while CAS inactive. tWEZ : from WE active while CAS inactive. The data goes a high-impedance state after either OE is inactive, or both RAS and LCAS (and/or UCAS) are inactive, or CAS is reactived. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. 5 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L HYPER PAGE MODE OPERATION The hyper page mode operation provides faster memory access and lower power dissipation. The hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each page of memory (within column address locations), any of 512 × 16-bits can be accessed and, when multiple MB81V4265Ss are used, CAS is decoded to select the desired memory page. Hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. Hyper page mode features that output remains valid when CAS is inactive until CAS is reactivated. 6 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L s DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Parameter Notes Symbol Condition Note 3 Min. Value Max. Unit Std Power Low Power Output High Voltage *1 VOH IOH = ­2.0 mA 2.4 - - Output Low Voltage *1 VOL IOL = 2.0 mA - 0.4 0.4 ­10 10 10 Input Leakage Current (Any Input) Output Leakage Current Operating Current (Average Power Supply Current) Standby Current (Power Supply Current) Refresh Current #1 (Average Power Supply Current) Hyper Page Mode Current Refresh Current #2 (Average Power Supply Current) Refresh Current #3 (Average Power Supply Current) Refresh Current #4 (Average Power Supply Current) II(L) IDQ(L) MB81V4265S MB81V4265S -60/60L -60/60L *2 MB81V4265S MB81V4265S -70/70L -70/70L ICC1 LVTTL Level ICC2 CMOS Level MB81V4265S MB81V4265S -60/60L -60/60L *2 MB81V4265S MB81V4265S -70/70L -70/70L MB81V4265S MB81V4265S -60/60L -60/60L *2 MB81V4265S MB81V4265S -70/70L -70/70L MB81V4265S MB81V4265S -60/60L -60/60L *2 MB81V4265S MB81V4265S -70/70L -70/70L MB81V4265S MB81V4265S -60/60L -60/60L MB81V4265S MB81V4265S -70/70L -70/70L MB81V4265S MB81V4265S -60/60L -60/60L MB81V4265S MB81V4265S -70/70L -70/70L ICC3 ICC4 ICC5 ICC6 ICC9 0 V VIN 3.6 V; 3.0 V VCC 3.6 V; VSS = 0 V; All other pins not under test = 0 V 0 V VOUT 3.6 V; Data out disabled RAS, LCAS & UCAS cycling; tRC = min V µA ­10 10 10 105 105 93 93 2.0 1.0 mA 1000 150 µA 105 105 93 93 105 105 93 93 105 105 93 93 - - 250 - - 250 - 1000 250 - RAS = LCAS = UCAS = VIH RAS = LCAS = UCAS VCC ­0.2 V - LCAS = UCAS = VIH, RAS cycling; tRC = min - RAS = VIL, LCAS / UCAS cycling; tHPC = min - RAS cycling; CAS-before-RAS; tRC = min mA - RAS cycling; CAS-before-RAS; tRC = 125 µs, tRAS = min to 1 µs, VIH VCC ­ 0.2 V RAS = VIL, CAS = VIL Self refresh; tRASS = min mA mA mA µA µA 7 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L s AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5 No. Parameter 1 Time Between Refresh 2 3 Notes Symbol Std Power Low Power tREF Random Read/Write Cycle Time Read-Modify-Write Cycle Time tRC tRWC MB81V4265S-60/60L MB81V4265S-60/60L Min. Max. - 8.2 - 64 104 - 138 - MB81V4265S-70/70L MB81V4265S-70/70L Min. Max. - 8.2 - 64 119 - 158 - Unit ms ns ns 4 Access Time from RAS *6,9 tRAC - 60 - 70 ns 5 Access Time from CAS *7,9 tCAC - 20 - 20 ns 6 Column Address Access Time *8,9 tAA - 30 - 35 ns 7 8 9 tOH tOHC tON 5 5 0 - - - 5 5 0 - - - ns ns ns tOFF - 15 - 15 ns tOFR - 15 - 15 ns tWEZ - 15 - 15 ns 13 14 15 16 Output Hold Time Output Hold Time from CAS Output Buffer Turn On Delay Time Output Buffer Turn Off Delay Time Output Buffer Turn Off Delay Time from RAS Output Buffer Turn Off Delay Time from WE Transition Time RAS Precharge Time RAS Pulse Width RAS Hold Time tT tRP tRAS tRSH 1 40 60 20 50 - 100000 - 1 45 70 20 50 - 100000 - ns ns ns ns 17 CAS to RAS Precharge Time *21 tCRP 0 - 0 - ns 18 RAS to CAS Delay Time CAS Pulse Width CAS Hold Time *11,12, 22 tRCD 14 40 14 50 ns tCAS tCSH 10 40 - - 10 50 - - ns ns tCPN 10 - 10 - ns tASR tRAH tASC tCAH 0 10 0 10 - - - - 0 10 0 10 - - - - ns ns ns ns tRAD 12 30 12 35 ns tRAL tCAL tRCS 30 23 0 - - - 35 28 0 - - - ns ns ns tRRH 0 - 0 - ns 10 11 12 19 20 21 22 23 24 25 26 27 28 29 30 CAS Precharge Time (Normal) Row Address Set Up Time Row Address Hold Time Column Address Set Up Time Column Address Hold Time RAS to Column Address Delay Time Column Address to RAS Lead Time Column Address to CAS Lead Time Read Command and Set Up Time Read Command Hold Time Referenced to RAS *10 *19 *13 *14 (Continued) 8 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Parameter Notes Read Command Hold Time Referenced to CAS Write Command Set Up Time Write Command Hold Time WE Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time DIN Set Up Time DIN Hold Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS Precharge Time to CAS Active Time (Refresh Cycles) CAS Set Up Time for CAS-beforeRAS Refresh CAS Hold Time for CAS-before-RAS Refresh Access Time from OE Output Buffer Turn Off Delay from OE OE to RAS Lead Time for Valid Data OE to CAS Lead Time OE Hold Time Referenced to WE OE to Data in Delay Time DIN to CAS Delay Time DIN to OE Delay Time CAS to Data in Delay Time RAS to Data in Delay Time Column Address Hold Time from RAS Write Command Hold Time from RAS DIN Hold Time Referenced to RAS OE Precharge Time OE Hold Time Referenced to CAS WE Precharge Time Symbol MB81V4265S-60/60L MB81V4265S-60/60L Min. Max. MB81V4265S-70/70L MB81V4265S-70/70L Min. Max. Unit *14 tRCH 0 - 0 - ns *15 tWCS 0 - 0 - ns tWCH tWP 10 10 - - 10 10 - - ns ns tRWL 15 - 20 - ns tCWL tDS tDH tRWD tCWD tAWD 10 0 10 77 37 47 - - - - - - 10 0 10 87 37 52 - - - - - - ns ns ns ns ns ns tRPC 10 - 10 - ns tCSR 0 - 0 - ns tCHR 10 - 10 - ns *9 tOEA - 20 - 20 ns *10 tOEZ - 15 - 15 ns tOEL tCOL 10 5 - - 10 5 - - ns ns tOEH 0 - 0 - ns tOED tDZC tDZO tCDD tRDD 15 0 0 15 15 - - - - - 15 0 0 15 15 - - - - - ns ns ns ns ns tAR 26 - 26 - ns tWCR 24 - 24 - ns tDHR tOEP tOECH tWPZ 24 10 10 10 - - - - 24 10 10 10 - ns - ns - ns - ns (Continued) *16 *17 *17 9 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L (Continued) No. 61 62 63 64 65 66 67 68 10 Parameter Notes WE to Data in Delay Time Hyper Page Mode RAS Pulse Width Hyper Page Mode Read/Write Cycle Time Hyper Page Mode Read-ModifyWrite Cycle Time Access Time from CAS Precharge Hyper Page Mode CAS Pulse Width Hyper Page Mode RAS Hold Time from CAS Precharge Hyper Page Mode CAS Precharge to WE Delay Time Symbol tWED tRASP MB81V4265S-60/60L MB81V4265S-60/60L Min. Max. 15 - 60 200000 MB81V4265S-70/70L MB81V4265S-70/70L Min. Max. 15 - 70 200000 Unit ns ns tHPC - 30 - ns tHPRWC *9,18 25 66 - 71 - ns tCPA - 35 - 40 ns tCP 10 - 10 - ns tRHCP 35 - 40 - ns tCPWD 52 - 57 - ns To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Notes: *1. Referenced to VSS. To all VCC (VSS) pins, the same supply voltage should be applied. *2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the output open. ICC depends on the number of address change as RAS = VIL and UCAS = VIH, LCAS = VIH, VIL > ­0.3 V. ICC1, ICC3 and ICC5 are specified at one time of address change during RAS = VIL and UCAS = VIH, LCAS = VIH. ICC4 is specified at one time of address change during one Page cycle. *3. An initial pause (RAS = CAS =VIH) of 200 µs is required after power-up followed by any eight RAS-only cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. *4. AC characteristics assume tT = 2 ns. *5. Input voltage levels are 0 V and 3.0 V, and input reference levels are VIH (min) and VIL (max) for measuring timing of input signals. Also, the transition time(tT) is measured between VIH (min) and VIL (max). The output reference levels are VOH = 2.0 V and VOL = 0.8 V. *6. Assumes that tRCD tRCD (max), tRAD tRAD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig. 2 and 3. *7. If tRCD tRCD (max), tRAD tRAD (max), and tASC tAA- tCAC - tT, access time is tCAC. *8. If tRAD tRAD (max) and tASC tAA- tCAC - tT, access time is tAA. *9. Measured with a load equivalent to one TTL load and 50 pF (60 ns version). Measured with a load equivalent to one TTL and 100 pF (70 ns version). *10. tOFF and tOEZ are specified that output buffer change to high-impedance state. *11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC or tAA. *12. tRCD (min) = tRAH (min)+ 2 tT + tASC (min). *13. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled exclusively by tCAC or tAA. *14. Either tRRH or tRCH must be satisfied for a read cycle. *15. tWCS is specified as a reference point only. If tWCS tWCS (min) the data output pin will remain High-Z state through entire cycle. *16. Assumes that tWCS < tWCS (min). *17. Either tDZC or tDZO must be satisfied. *18. tCPA is access time from the selection of a new column address (that is caused by changing both UCAS and LCAS from "L" to "H"). Therefore, if tCP is long, tCPA is longer than tCPA (max). *19. Assumes that CAS-before-RAS refresh. *20. The last CAS rising edge. *21. The first CAS falling edge. 11 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 2 ­ tRAC vs. tRCD Fig. 4 ­ tCPA vs. tCP Fig. 3 ­ tRAC vs. tRAD tRAC (ns) tRAC (ns) tCPA (ns) 140 100 70 120 90 60 100 80 50 80 70 70ns version 70ns version 40 70ns version 60ns version 60 0 20 40 60 80 100 60ns version 30 60ns version 60 10 0 20 30 40 50 60 10 0 30 40 50 tCP (ns) tRAD (ns) tRCD (ns) 20 s FUNCTIONAL TRUTH TABLE Address Input Clock Input Operation Mode RAS LCAS UCAS WE OE Row Column Input/Output Data DQ1 to DQ8 DQ9 to DQ16 Refresh Note Input Output Input Output Standby H H H X X - - - High-Z - High-Z Read Cycle L L H L H L L H L Valid Valid - Valid High-Z Valid - High-Z Valid Valid Yes* tRCS tRCS (min) Write Cycle (Early Write) L L H L H L L Yes* tWCS tWCS (min) Read-ModifyWrite Cycle L L H L H L L Yes* RAS-only Refresh Cycle L H H X X Valid - - High-Z - High-Z Yes CAS-beforeRAS Refresh Cycle L L L X X - - - High-Z - High-Z Yes tCSR tCSR(min) L H L H L L H L - - - Valid High-Z Valid - High-Z Valid Valid Yes Previous data is kept. Hidden HL Refresh Cycle Valid Valid Valid - - High-Z Valid High-Z Valid Valid HL LH Valid Valid Valid Valid - High-Z - High-Z Valid Valid Valid Valid Valid Valid L X : "H" or "L" * : It is impossible in Hyper Page Mode. 12 X - To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 5 ­ READ CYCLE tRC tRAS RAS tRA VIH VIL tCRP tRP tCSH tRCD LCAS or UCAS tRSH tCAS VIH VIL tRAD tCDD tRAL tASR A0 to A8 tCAL tRAH tASC tCOL tOEL tCAH VIH VIL ROW ADD COLUMN ADD tRRH tRCH tRCS WE VIH tCAC tOH VOL tOFF HIGH-Z tON tOEZ tOEA VIH HIGH-Z VIL tDZO OE tWED tWEZ VOH tDZC DQ (Input) tWPZ tAA VIL tRAC DQ (Output) tRDD tON tOH tOED VIH VIL "H" or "L" Valid Data DESCRIPTION To implement a read operation, a valid address is latched by the RAS and LCAS or UCAS address strobes and with WE set to a High level and OE set to a low level, the output is valid once the memory access time has elapsed. DQ8 to DQ16 pins is valid when RAS and CAS are High or until OE goes High. The access time is determined by RAS(tRAC), LCAS/UCAS(tCAC), OE(tOEA) or column addresses (tAA) under the following conditions: If tRCD > tRCD (max), access time = tCAC. If tRAD > tRAD (max), access time = tAA. If OE is brought Low after tRAC, tCAC, or tAA (whichever occurs later), access time = tOEA. However, if either LCAS/UCAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied. 13 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 6 ­ EARLY WRITE CYCLE tRC tRAS RAS VIH VIL tCRP tCSH tRSH tRCD LCAS or UCAS tRP tCAS VIH VIL tAR tASR A0 to A8 tRAH tASC tCAH VIH VIL ROW ADD COLUMN ADD tWCR tWCS tWCH VIH WE VIL tDHR tDS DQ (Input) VIH DQ (Output) VOH tDH VIL VOL VALID DATA IN HIGH-Z "H" or "L" DESCRIPTION A write cycle is similar to a read cycle except WE is set to a Low state and OE is an "H" or "L" signal. A write cycle can be implemented in either of three ways ­ early write, delayed write, or read-modify-write. During all write cycles, timing parameters tRWL, tCWL, tRAL and tCAL must be satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pins are latched with the falling edge of LCAS or UCAS and written into memory. 14 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 7 ­ DELAYED WRITE CYCLE (OE CONTROLLED) tRC tRAS RAS VIH tAR VIL tRP tCSH tCRP tCAS tRCD tRSH LCAS or UCAS VIH VIL tASR A0 to A8 VIH VIL tRAH tASC ROW ADD tCAH COL ADD tCWL tRCS tWCH tRWL tWP WE VIH VIL tDS tDH tDZC DQ (Input) VIH VIL HIGH-Z tOED VALID DATA IN tON VOH DQ (Output) VOL HIGH-Z HIGH-Z tDZO tOEH tON tOEZ OE VIH VIL "H" or "L" Invalid Data DESCRIPTION In the delayed write cycle, tWCS is not satisfied; thus, the data on the DQ pins are latched with the falling edge of WE and written into memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tT + tDS). 15 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 8 ­ READ-MODIFY-WRITE CYCLE tRWC tRAS RAS VIH VIL tAR tCRP LCAS VIH or UCAS VIL tRAD tASR A0 to A8 VIH VIL tRP tRCD tRAH tASC tCAH COL ADD ROW ADD tRWD tRCS WE tCWL tRWL tAWD tCWD VIH VIL tWP tDS tDZC DQ VIH (Input) VIL tDH VALID DATA IN HIGH-Z tOED tCAC tAA DQ VOH (Output) VOL tOEH tRAC VALID DATA HIGH-Z tDZO HIGH-Z tON tOEA tON tOEZ OE VIH VIL tOH "H" or "L" DESCRIPTION The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the readmodify-write cycle, OE must be changed from Low to High after the memory access time. 16 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L tRASP Fig. 9 ­ HYPER PAGE MODE READ CYCLE tRASP tRCD tRHCP VIH VIL RAS tRAD tHPC tCRP tCSH tCAS tCAS tCAS LCAS or UCAS VIH VIL tASR tAR tASC tCAH tASC tCAH A0 to A8 VIH VIL ROW ADD COL ADD tRCS tRAL COL ADD COL ADD tRCS tRCH tRCH tRCS tRCH VIH VIL tCPA tDZC tOHC tDZC DQ (Input) tRDD tRRH tCAH tASC tRAH WE tRP tRSH tCP VIH VIL HIGH-Z tCPA tCDD HIGH-Z HIGH-Z tCAC tDZO tCAC tON tOH tDZC tCAC tON tOFR tON tOHC tOFF tOH tRAC DQ VOH (Output) VOL HIGH-Z tAA OE tAA tOH tOEZ tOED VIH VIL During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" Valid Data DESCRIPTION The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 17 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 10 ­ HYPER PAGE MODE READ CYCLE (OE = "H" or "L") tRASP tRCD RAS VIH VIL tRHCP tAR tRAD tHPC tCRP LCAS or UCAS tCSH tCP tCAS tCAH tCAL tASC tCAH tASC tRAH tASC tCDD tRAL tCAH VIH VIL tRRH tCAS tCAS VIH VIL tASR A0 to A8 tRP tRSH tCP ROW ADD COL ADD COL ADD COL ADD tRCH tRCS WE tRDD VIH VIL tOH tDZC DQ (Input) HIGH-Z HIGH-Z tCPA tCPA tRAC tAA tAA tCAC tCAC DQ (Output) VOH VOL tDZO OE tAA tCAC tOFF HIGH-Z tON VIH VIL tOFR tOH VIH VIL tOECH tOH tCOL tOEP tOEA tON tOEA tOECH tON tOEA tCOL tOEZ tOEZ tOH tOEP tOH tOED tCOL tOEZ During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" Valid Data DESCRIPTION The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 18 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 11 ­ HYPER PAGE MODE READ CYCLE (WE = "H" or "L") tRASP tRHCP VIH RAS tAR VIL tRCD tCRP tHPC tCAS LCAS or UCAS VIH tCAS tCAS tRAD VIL tASR tCAL tASC tRAL tCSH VIL ROW ADD COL ADD tOH tRCS tRCH tRCH tWPZ VIH WE COL ADD COL ADD tRCS tOFR tCSH tCAH VIH tRDD tASC tASC tRAH A0 to A8 tRP tRSH tCSH tRCS tRCH tWPZ tWPZ VIL tCDD tWED tDZC tOH DQ VIH (Input) VIL HIGH-Z tRAC tAA tAA tWEZ tCAC DQ VOH (Output) VOL HIGH-Z tAA tCAC tCAC tON tON HIGH-Z tOH tOEZ tOED tDZO OE tWEZ tWEZ tON VIH tOFF tON tOEA VIL During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" Valid Data DESCRIPTION The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 19 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 12 ­ HYPER PAGE MODE EARLY WRITE CYCLE tRASP VIH RAS tRHCP VIL tCSH tCRP tRCD LCAS or UCAS tRHCP tHPC tCP tCAS tCAS tCAS VIH VIL tAR VIH VIL tCAH tRAL tASC tASR A0 to A8 tCAH tCAH tRAH tASC ROW ADD tASC COL ADD COL ADD tWCH tWCR tWCS tWCH tWCS tCWL COL ADD tWCH tWCS tCWL tRWL tCWL VIH WE VIL tDHR tDS DQ (Input) tRP VIH VIL VOH DQ (Output) VOL tDH VALID DATA tDS tDH VALID DATA tDS tDH VALID DATA HIGH-Z During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" DESCRIPTION The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of WE and OE are reversed. Data appearing on the DQ1 to DQ8 is latched on the falling edge of LCAS and one appearing on the DQ9 to DQ16 is latched on the falling edge of UCAS and the data is written into the memory. During the hyper page mode early write cycle, including the delayed (OE) write and read-modify-write cycles, tCWL must be satisfied. 20 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 13 ­ HYPER PAGE MODE DELAYED WRITE CYCLE tRASP VIH RAS VIL tCSH tCRP LCAS or UCAS tRCD tCAS VIL VIH A0 to A8 VIL tAR tASC tRAH tRSH tCAS ROW ADD tCAH VIL tCWL tWCH tWP tRWL tWCH tWP tDS tDS tDZC tDH tDH VIH VALID DATA IN VIL tCWL COL ADD COL ADD VIH VOH DQ (Output) VOL tASC tCAH tRCS DQ (Input) tRP tHPC VIH tASR WE tCP tOED tON tOEH VALID DATA IN tON tOED HIGH-Z tON tON tDZO tOEZ tOEH tOEZ VIH OE VIL "H" or "L" Invalid Data DESCRIPTION The hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the hyper page mode delayed write cycle, OE must be changed from Low to High before WE goes Low (tOED + tT + tDS). 21 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 14 ­ HYPER PAGE MODE READ/WRITE MIXED CYCLE VIH RAS tRASP tRHCP VIL tRCD tCRP LCAS or UCAS tCSH VIH tASR VIH A0 to A8 VIL tRSH tCAS tCAS tCAS tRAD VIL tCP tASC tRAH tCAL tCAH ROW ADD tASC tCAL tCAH tRCS COL ADD tRCH tWCH VIH WE tWCS VIL tWED tDZC DQ (Input) tRAL tCAH tASC COL ADD COL ADD tRP tHPC VIH VALID DATA IN HIGH-Z VIL tCPA tAA tRAC tAA VOH DQ (Output) VOL tDH tDS tOHC tCAC tOED tCAC tWEZ HIGH-Z HIGH-Z tON tOEZ tDZO tON VIH OE VIL tOEA "H" or "L" Valid Data DESCRIPTION The hyper page mode performs read/write operations repetitively during one RAS cycle. At this time, tHPC (min) is invalid. 22 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 15 ­ HYPER PAGE MODE READ-MODIFY-WRITE CYCLE tRASP VIH RAS VIL LCAS or UCAS A0 to A8 tRCD tHPRWC VIH tCWD tCP tCWD tRAD VIL tASR tASC tRAH tASC tCAH tCAH VIH COL ADD VIL COL ADD tAWD tRCS tCPWD tRCS tCWL tWP VIL tDS tRWD DQ (Input) tCWL tWP VIH WE tRP tRWL tCRP VIL tOED VALID DATA VALID DATA tOED tCAC tAA tON tDH tDH tDZC VIH VOH DQ (Output) VOL tDS tAA tCAC tON HIGH-Z tON tRAC tDZO tOEH tON tOEA tOEZ tOEZ tOEH VIH OE VIL tOEA tCPA "H" or "L" Valid Data DESCRIPTION During the hyper page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data appears at the DQ pins during a normal cycle. 23 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 16 ­ RAS-ONLY REFRESH (WE = OE = "H" or "L") tRC RAS tRAS VIH VIL tASR A0 to A8 VIH VIL tRP tRAH tRPC ROW ADDRESS tCRP tCRP LCAS or UCAS VIH VIL tOFF tOH DQ VOH (Output) VOL HIGH-Z "H" or "L" DESCRIPTION Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 512 row addresses every 8.2-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. RAS-only refresh is performed by keeping RAS Low and LCAS and UCAS High throughout the cycle; the row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state. Fig. 17 ­ CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = "H" or "L") tRC RAS tCPN LCAS or UCAS tRP tRAS VIH VIL tCSR tRPC tCHR tCSR tCPN VIH VIL tOFF tOH DQ VOH (Output) VOL HIGH-Z "H" or "L" DESCRIPTION CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS is held Low for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. 24 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 18 ­ HIDDEN REFRESH CYCLE tRC tRC tRP tRAS RAS tOEL VIH VIL tRCD tRP tCRP tRSH tCHR tRAD LCAS or UCAS tRAS VIH VIL tRAH tASR tASC tRAL tAR tCAH A0 to A8 VIH VIL ROW ADDRESS COLUMN ADDRESS tRRH tRCS WE VIH VIL tAA tRAC DQ (Input) tCDD tCAC tDZC VIH VIL HIGH-Z tOFF tOFR tOH tON tOH DQ (Output) VOH VOL tDZO OE VALID DATA OUT HIGH-Z tOEA tOEZ tOED VIH VIL "H" or "L" DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of LCAS or UCAS and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that is required by DRAMs that do not have CAS-before-RAS refresh capability. 25 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 19 ­ CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE RAS VIH VIL tCHR LCAS or UCAS tFRSH tFCAS tCP tCSR VIH VIL tFCAH tASC A0 to A8 VIH VIL COLUMN ADDRESS VIH VIL tCWL tRWL tFCWD tRCS WE tRP tDZC tWP tDS DQ (Input) tDH VIH VIL tOED tFCAC DQ VOH (Output) VOL HIGH-Z HIGH-Z tON tOEA tDZO OE VALID DATA IN HIGH-Z tOEH tOEZ VIH VIL "H" or "L" Valid Data DESCRIPTION A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality of CAS-before-RAS refresh circuitry. After a CAS-before-RAS refresh cycle, if LCAS or UCAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Address: Bits A0 through A8 are defined by the on-chip refresh counter. Column Address: Bits A0 through A8 are defined by latching levels on A0 to A8 at the second falling edge of LCAS or UCAS. The CAS-before-RAS Counter Test procedure is as follows; 1) Normalize the internal refresh address counter by using 8 RAS-only refresh cycles. 2) Use the same column address throughout the test. 3) Write "0" to all 512 row addresses at the same column address by using CBR refresh counter test cycles. 4) Read "0" written in procedure 3) by using normal read cycle and check; after reading "0" and check are completed (or simultaneously), write "1" to the same addresses by using normal write cycle (or read-modify-write cycle). 5) Read and check data "1" written in procedure 4) by using CBR refresh counter test cycle for all 512 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). (At recommended operating conditions unless otherwise noted.) No. Parameter Symbol MB81V4265S-60/60L MB81V4265S-60/60L Min. Max. - 55 90 Access Time from CAS tFCAC 91 Column Address Hold Time 92 93 CAS to WE Delay Time tFCAH tFCWD 30 80 - - tFCAS 55 - 94 95 26 CAS Pulse Width RAS Hold Time CAS Hold Time MB81V4265S-70/70L MB81V4265S-70/70L Unit Min. Max. µs - 55 - ns 30 - 80 ns - µs 55 - - 55 55 ns tFRSH ns - - tFCSH 85 85 Note: Assumes that CAS-before-RAS refresh counter test cycle only. To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L Fig. 20 ­ SELF REFRESH CYCLE (A0 to A8 = WE = OE = "H" or "L") RAS VIH VIL tCSR tCPN LCAS or UCAS tRPS tRASS tRPC tCHS VIH VIL tOFF tOH VOH DQ (Output) VOL HIGH-Z "H" or "L" (At recommended operating conditions unless otherwise noted.) No. 74 Parameter Symbol 75 RAS Pulse Width RAS Precharge Time tRASS tRPS 76 CAS Hold Time tCHS MB81V4265S-60/60L MB81V4265S-60/60L Min. Max. 100 - - 104 ­50 - MB81V4265S-70/70L MB81V4265S-70/70L Unit Min. Max. µs 100 - ns - 119 ­50 - ns Note: Assumes Self Refresh cycle only. DESCRIPTION The Self Refresh cycle provides a refresh operation without external clock and external Address. Self Refresh control circuit on chip is operated in the Self Refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator. If CAS goes to "L" before RAS goes to "L" (CBR) and the condition of CAS "L" and RAS "L" is kept for term of tRASS (more than 100 µs), the device can enter the Self Refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using internal refresh address counter during "RAS=L" and "CAS=L". Exit from Self Refresh cycle is performed by toggling RAS and CAS to "H" with specified tCHS min. In this time, RAS must be kept "H" with specified tRPS min. Using Self Refresh mode, data can be retained without external CAS signal during system is in standby. Restriction for Self Refresh operation; For Self Refresh operation, the notice below must be considered. 1) In the case that distributed CBR refresh are operated between read/write cycles Self Refresh cycles can be executed without special rule if 512 cycles of distributed CBR refresh are executed within tREF max. 2) In the case that burst CBR refresh or distributed/burst RAS-only refresh are operated between read/write cycles 512 times of burst CBR refresh or 512 times of burst RAS-only refresh must be executed before and after Self Refresh cycles. Read/Write operation RAS VIH VIL tNS < 0.5 ms 512 burst refresh cycle Self Refresh operation tRASS Read/Write operation tSN < 0.5 ms 512 burst refresh cycle * Read/Write operation can be performed non refresh time within tNS or tSN. 27 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L s PACKAGE DIMENSIONS 40-LEAD 40-LEAD PLASTIC LEADED CHIP CARRIER (CASE No.: LCC-40P-M01 LCC-40P-M01) +0.25 3.50 ­0.20 +.010 .138 ­.008 2.31(.091)NOM * 26.03±0.13(1.025±0.05) 40 21 1 R0.89(.035)TYP 10.16(.400) 11.18±0.13 NOM (.440±.005) INDEX LEAD No 0.64(.025)MIN +0.05 20 1.27±0.13 (.050±.005) 9.40±0.51 (.370±.020) 0.20 ­0.02 +.002 .008 ­.001 24.13(.950)REF Details of "A" part 0.81(.032)MAX. 2.60(.102)NOM 0.43±0.10(.017±.004) "A" 0.10(.004) * Resin protrusion. (Each side: 0.15 (.006)MAX.) ©1993 FUJITSU LIMITED C40051S-3C-1 C40051S-3C-1 28 Dimensions in mm (inches) To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L s PACKAGE DIMENSIONS 44-LEAD 44-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-44P-M07 FPT-44P-M07) 44 35 32 23 Details of "A" part 0.15(.006) 0.25(.010) 0.15(.006)MAX INDEX 0.40(.016)MAX "A" LEAD No. 1 10 13 22 * 18.41±0.10 (.725±.004) 0.30±0.10 (.012±.004) 0.13(.005) M 0.10(.004) 0.80(.0315)TYP +0.10 1.10 ­0.05 +.004 .043 ­.002 0.50±0.10 0(0)MIN (.020±.004) (STAND OFF) 11.76±0.20 (.463±.008) 10.16±0.10 (.400±.004) 0.15±0.05 (.006±.002) 10.76±0.20 (.424±.008) 16.80(.661)REF * Resin protrusion. (Each side: 0.15 (.006)MAX.) C 1994 FUJITSU LIMITED F44016S-1C-2 F44016S-1C-2 Dimensions in mm (inches) 29 To Top / Lineup / Index MB81V4265S-60/-70/-60L/-70L MB81V4265S-60/-70/-60L/-70L FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. 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If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9704 F9704 © FUJITSU LIMITED Printed in Japan 30