MB15F73UL MB15F03SL MB15F73SP BCC20 BCC16 FPT-20P-M06 LCC-20P-M05 MB15F02SL - Datasheet Archive

 

DATA SHEET DS04-21368-1Ea ASSP Dual Serial Input PLL Frequency Synthesizer MB15F73UL DESCRIPTION The Fujitsu Microelectronics

 

FUJITSU MICROELECTRONICS DATA SHEET DS04-21368-1Ea ASSP Dual Serial Input PLL Frequency Synthesizer MB15F73UL MB15F73UL DESCRIPTION The Fujitsu Microelectronics MB15F73UL MB15F73UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250 MHz and a 600 MHz prescalers. A 64/65 or a 128/129 for the 2250 MHz prescaler, and a 8/9 or a 16/17 for the 600 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 3.2 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The data format is the same as the previous one MB15F03SL MB15F03SL, MB15F73SP MB15F73SP. Fast locking is achieved for adopting the new circuit. The new package (BCC20 BCC20) decreases a mount area of MB15F73UL MB15F73UL more than 30% comparing with the former BCC16 BCC16 (for dual PLL) . MB15F73UL MB15F73UL is ideally suited for wireless mobile communications, such as GSM and PCS. FEATURES · High frequency operation : RF synthesizer : 2250 MHz Max. : IF synthesizer : 600 MHz Max. · Low power supply voltage : VCC = 2.4 to 3.6 V · Ultra low power supply current : ICC = 3.2 mA Typ. (VCC = Vp = 2.7 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state) (Continued) PACKAGES 20-pin plastic TSSOP 20-pad plastic BCC (FPT-20P-M06 FPT-20P-M06) (LCC-20P-M05 LCC-20P-M05) Copyright©2001-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2001.6 MB15F73UL MB15F73UL (Continued) · Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25 °C) Max. 10 µA (VCC = Vp = 2.7 V) · Software selectable charge pump current : 1.5 mA/6.0 mA Typ. · Dual modulus prescaler : 2250 MHz prescaler (64/65 or128/129) /600 MHz prescaler (8/9 or 16/17) · 23 bit shift register · Serial input binary 14-bit programmable reference divider : R = 3 to 16,383 · Serial input programmable divider consisting of: - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 3 to 2,047 · Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit · On-chip phase control for phase comparator · On-chip phase comparator for fast lock and low noise · Built-in digital locking detector circuit to detect PLL locking and unlocking · Operating temperature : Ta = -40 °C to +85 °C · Serial data format compatible with MB15F02SL MB15F02SL PIN ASSIGNMENTS (TSSOP-20 TSSOP-20) TOP VIEW OSCIN GND finIF XfinIF GNDIF VCCIF PSIF VpIF DoIF LD/fout 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (BCC-20 BCC-20) TOP VIEW Clock Data LE finRF XfinRF GNDRF VCCRF PSRF VpRF DoRF (FPT-20P-M06 FPT-20P-M06) 2 OSCIN Data GND Clock finIF 1 20 19 18 17 16 XfinIF GNDIF VCCIF PSIF 2 3 4 5 15 14 13 12 VpIF 6 7 8 9 10 11 DoRF DoIF LD/fout VpRF (LCC-20P-M05 LCC-20P-M05) LE finRF XfinRF GNDRF VCCRF PSRF MB15F73UL MB15F73UL PIN DESCRIPTION Pin no. TSSOP BCC Pin name I/O Descriptions The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor. 1 19 OSCIN I 2 20 GND 3 1 finIF I Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. 4 2 XfinIF I Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. 5 3 GNDIF 6 4 VCCIF 7 5 PSIF I 8 6 VpIF Power supply voltage input pin for the IF-PLL charge pump. 9 7 DoIF O Charge pump output for the IF-PLL section. 10 8 LD/fout O Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The output signal is selected by LDS bit in a serial data. LDS bit = "H" ; outputs fout signal/LDS bit = "L" ; outputs LD signal 11 9 DoRF O Charge pump output for the RF-PLL section. 12 10 VpRF Power supply voltage input pin for the RF-PLL charge pump. 13 11 PSRF I 14 12 VCCRF 15 13 GNDRF 16 14 XfinRF I Prescaler complimentary input pin for the RF-PLL section. This pin should be grounded via a capacitor. 17 15 finRF I Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling. 18 16 LE I Load enable signal input pin (with the schmitt trigger circuit) When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 Data I Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. 20 18 Clock I Clock input pin for the 23-bit shift register (with the schmitt trigger circuit) One bit data is shifted into the shift register on a rising edge of the clock. Ground pin for OSC input buffer and the shift register circuit. Ground pin for the IF-PLL section. Power supply voltage input pin for the IF-PLL section (except for the charge pump circuit) , the shift register and the oscillator input buffer. Power saving mode control pin for the IF-PLL section. This pin must be set at "L" when the power supply is started up. (Open is prohibited.) PSIF = "H" ; Normal mode/PSIF = "L" ; Power saving mode Power saving mode control for the RF-PLL section. This pin must be set at "L" when the power supply is started up. (Open is prohibited. ) PSRF = "H" ; Normal mode/PSRF = "L" ; Power saving mode Power supply voltage input pin for the RF-PLL section (except for the charge pump circuit) Ground pin for the RF-PLL section 3 MB15F73UL MB15F73UL BLOCK DIAGRAM VpIF 8 (6) VCCIF GNDIF (4) 6 5 (3) Intermittent mode control (IF-PLL) FCIF SWIF 3 bit latch LDS PSIF 7 (5) 7 bit latch 11 bit latch Phase comp. (IF-PLL) Binary 7-bit Binary 11-bit swallow counter programmable (IF-PLL) counter (IF-PLL) Charge pump Current (IF-PLL) Switch 9 DoIF (7) fpIF finIF 3 (1) XfinIF 4 (2) Prescaler (IF-PLL) (8/9, 16/17) Lock Det. (IF-PLL) 2 bit latch T1 T2 14 bit latch 1 bit latch Binary 14-bit programmable ref. counter(IF-PLL) C/P setting counter LDIF frIF Fast lock Tuning OSCIN 1 (19) T1 Binary 14-bit programmable ref. counter (RF-PLL) OR 2 bit latch LE 18 (16) (17) Data 19 Clock 20 (18) Intermittent mode control (RF-PLL) Schmitt circuit Schmitt circuit Schmitt circuit FCRF fpRF Binary 11-bit Binary 7-bit swallow counter programmable counter (RF-PLL) (RF-PLL) 3 bit latch 7 bit latch 4 Phase comp. (RF-PLL) Charge Current pump Switch (RF-PLL) fpRF 11 bit latch Latch selector C C N N 1 2 23-bit shift register 2 (20) GND O : TSSOP ( ) : BCC Lock Det. (RF-PLL) Fast lock Tuning PSRF 13 (11) 10 LD/ (8) fout LDRF SWRF XfinRF 16 (14) 1 bit latch Prescaler (RF-PLL) (64/65, 128/129) LDS (15) finRF 17 LD frIF frRF fpIF fpRF C/P setting counter 14 bit latch T2 Selector AND frRF (12) 14 15 (13) VCCRF GNDRF 12 (10) VpRF 11 DoRF (9) MB15F73UL MB15F73UL ABSOLUTE MAXIMUM RATINGS Parameter Symbol Unit Min. Max. VCC -0.5 4.0 V Vp VCC 4.0 V VI -0.5 VCC + 0.5 V LD/fout VO GND VCC V DoIF, DoRF VDO GND Vp V Tstg -55 +125 °C Power supply voltage Input voltage Output voltage Rating Storage temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Remarks 3.6 V VCCRF = VCCIF 2.7 3.6 V GND VCC V -40 +85 °C Min. Typ. Max. VCC 2.4 2.7 Vp VCC Input voltage VI Operating temperature Ta Power supply voltage Note : · VCCRF, VpRF, VCCIF and VpIF must supply equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. · Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the following precautions when handling the device. · When storing and transporting the device, put it in a conductive case. · Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench. · Before fitting the device into or removing it from the socket, turn the power supply off. · When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 5 MB15F73UL MB15F73UL ELECTRICAL CHARACTERISTICS * (VCC = 2.4 V to 3.6 V, Ta = -40 °C to +85 °C) Parameter Symbol Condition Value Min. Typ. Max. Unit ICCIF *1 finIF = 480 MHz VCCIF = VpIF = 2.7 V 0.8 1.2 1.7 mA ICCRF *1 finRF = 2000 MHz VCCRF = VpRF = 2.7 V 1.3 2.0 2.8 mA IPSIF PSIF = PSRF = "L" 0.1 *2 10 µA IPSRF PSIF = PSRF = "L" 0.1 *2 10 µA finIF IF PLL 50 600 MHz finRF RF PLL 200 2250 MHz 3 40 MHz Power supply current Power saving current finIF *3 Operating frequency finRF *3 OSCIN Input sensitivity "L" level input voltage "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current finIF PfinIF IF PLL, 50 system -15 +2 dBm finRF PfinRF RF PLL, 50 system -15 +2 dBm 0.5 VCC VP-P Input available voltage OSCIN "H" level input voltage fOSC VOSC Data LE Clock VIH Schmitt triger input 0.7 VCC + 0.4 V VIL Schmitt triger input 0.3 VCC - 0.4 V PSIF PSRF VIH 0.7 VCC V VIL 0.3 VCC V Data LE Clock PS IIH *4 -1.0 +1.0 µA IIL *4 -1.0 +1.0 µA IIH 0 +100 µA IIL *4 -100 0 µA VCC - 0.4 V 0.4 V OSCIN "H" level output voltage LD/ "L" level output voltage fout VOH VCC = Vp = 2.7 V, IOH = -1 mA VOL VCC = Vp = 2.7 V, IOL = 1 mA "H" level output voltage DoIF "L" level output voltage DoRF VDOH VCC = Vp = 2.7 V, IDOH = -0.5 mA Vp - 0.4 V VDOL VCC = Vp = 2.7 V, IDOL = 0.5 mA 0.4 V IOFF VCC = Vp = 2.7 V VOFF = 0.5 V to Vp - 0.5 V 2.5 nA IOH *4 VCC = Vp = 2.7 V -1.0 mA IOL VCC = Vp = 2.7 V 1.0 mA High impedance cutoff DoIF current DoRF "H" level output current LD/ "L" level output current fout (Continued) 6 MB15F73UL MB15F73UL (Continued) (VCC = 2.4 V to 3.6 V, Ta = -40 °C to +85 °C) Parameter Symbol "H" level output current DoIF *8 DoRF IDOH *4 "L" level output current DoIF *8 DoRF IDOL IDOL/IDOH IDOMT *5 Value Condition Min. Typ. Max. Unit VCC = Vp = 2.7 V, VDOH = Vp / 2, Ta = +25 °C CS bit = "H" -8.2 -6.0 -4.1 mA CS bit = "L" -2.2 -1.5 -0.8 mA VCC = Vp = 2.7 V, VDOL = Vp / 2, Ta = +25 °C CS bit = "H" 4.1 6.0 8.2 mA CS bit = "L" 0.8 1.5 2.2 mA VDO = Vp / 2 3 % vs VDO I 0.5 V VDO Vp - 0.5 V 10 % vs Ta Charge pump current rate IDOTA *7 -40 °C Ta 85 °C, VDO = Vp / 2 5 % DOVD *6 *1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = "L" in locking state. *2 : VCCIF = VpIF = VCCRF = VpRF = 2.7 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode. PSIF = PSRF = GND VIH = VCC, VIL = GND (at CLK, Data, LE) *3 : AC coupling. 1000 pF capacitor is connected under the condition of Min. operating frequency. *4 : The symbol "­" (minus) means the direction of current flow. *5 : VCC = Vp = 2.7 V, Ta = +25 °C (||I3| - |I4||) / [ (|I3| + |I4|) / 2] × 100 (%) *6 : VCC = Vp = 2.7 V, Ta = +25 °C [ (||I2| - |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH) *7 : VCC = Vp = 2.7 V, [||IDO (+85 °C) | - |IDO (­40 °C) || / 2] / [|IDO (+85 °C) | + |IDO (­40 °C) | / 2] × 100 (%) (Applied to both IDOL and IDOH) *8 : When Charge pump current is measured, set LDS = "L" , T1 = "L" and T2 = "H". I3 I1 I2 IDOL IDOH I4 I2 I1 0.5 Vp/2 Vp - 0.5 Vp Charge pump output voltage (V) 7 MB15F73UL MB15F73UL FUNCTIONAL DESCRIPTION 1. Pulse swallow function fVCO = [ (P × N) + A] × fOSC ÷ R fVCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64or 128 for RF-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127, A < N) fOSC : Reference oscillation frequency (OSCIN input frequency) R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. Serial Data Input The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RFPLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually. The serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. The programmable reference counter for the IF-PLL The programmable reference counter for the RF-PLL The programmable counter and the swallow counter for the IF-PLL The programmable counter and the swallow counter for the RF-PLL CN1 0 1 0 1 CN2 0 0 1 1 (1) Shift Register Configuration · Programmable Reference Counter (LSB) 1 2 3 Data Flow 4 5 6 7 8 9 10 11 12 13 (MSB) 14 15 16 17 18 19 20 21 22 23 CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X CS R1 to R14 T1, 2 CN1, 2 X : Charge pump current select bit : Divide ratio setting bits for the programmable reference counter (3 to 16,383) : LD/fout output setting bit : Control bit : Dummy bits (Set "0" or "1") Note : Data input with MSB first. 8 X X X MB15F73UL MB15F73UL · Programmable Counter (LSB) 1 2 Data Flow 3 4 5 6 7 8 (MSB) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CN1 CN2 LDS SWIF/RF FCIF/RF A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 A1 to A7 N1 to N11 LDS SWIF/RF FCIF/RF CN1, 2 : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bits for the programmable counter (3 to 2,047) : LD/fout signal select bit : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF) : Phase control bit for the phase detector (IF : FCIF, RF : FCRF) : Control bit Note : Data input with MSB first. (2) Data setting · Binary 14-bit Programmable Reference Counter Data Setting Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 · · · 16383 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 1 · · · 1 0 · · · 1 0 · · · 1 Note : Divide ratio less than 3 is prohibited. · Binary 11-bit Programmable Counter Data Setting Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 3 0 0 0 0 0 0 0 0 0 1 1 4 · · · 2047 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 1 · · · 1 0 · · · 1 0 · · · 1 Note : Divide ratio less than 3 is prohibited · Binary 7-bit Swallow Counter Data Setting Divide ratio A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 · · · 127 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 1 · · · 1 9 MB15F73UL MB15F73UL · Prescaler Data Setting SW = "H" SW = "L" Prescaler divide ratio IF-PLL 8/9 16/17 Prescaler divide ratio RF-PLL 64/65 128/129 Divide ratio · Charge Pump Current Setting Current value CS ±6.0 mA 1 ±1.5 mA 0 · LD/fout output Selectable Bit Setting LD/fout pin state LDS T1 T2 0 0 0 0 1 0 0 1 1 frIF 1 0 0 frRF 1 1 0 fpIF 1 0 1 fpRF 1 1 1 LD output fout output · Phase Comparator Phase Switching Data Setting FCIF, RF = "H" FCIF, RF = "L" DoIF, RF DoIF, RF fr > fp H L fr < fp L H fr = fp Z Z Phase comparator input Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. High (1) (1) VCO polarity FC = "H" (2) VCO polarity FC = "L" VCO Output Frequency (2) LPF Output voltage Note : Give attention to the polarity for using active type LPF. 10 Max. MB15F73UL MB15F73UL 3. Power Saving Mode (Intermittent Mode Control Circuit) Status PS pin Normal mode H Power saving mode L The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes : · When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs. · PS pin must be set "L" at Power-ON. OFF V CC ON tV 1 µs Clock Data LE tPS 100 ns PS (1) (2) (3) (1) PS = L (power saving mode) at Power-ON (2) Set serial data at least 1 µs after the power supply becomes stable (VCC 2.2 V) . (3) Release power saving mode (PSIF, PSRF : "L" "H") at least 100 ns later after setting serial data. 11 MB15F73UL MB15F73UL 4. Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing. 1st data 2nd data Invalid data Control bit Data MSB LSB Clock t1 t2 t3 t6 t7 LE t4 t5 Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit t1 20 ns t5 100 ns t2 20 ns t6 20 ns t3 30 ns t7 100 ns t4 30 ns Note : LE should be "L" when the data is transferred into the shift register. 12 MB15F73UL MB15F73UL PHASE COMPARATOR OUTPUT WAVEFORM fr IF/RF fp IF/RF t WU t WL LD (FC bit = High) D o IF/RF H Z L (FC bit = Low) H D o IF/RF Z L · LD Output Logic IF-PLL section RF-PLL section LD output Locking state/Power saving state Locking state/Power saving state H Locking state/Power saving state Unlocking state L Unlocking state Locking state/Power saving state L Unlocking state Unlocking state L Notes : · Phase error detection range = -2 to +2 · Pulses on DoIF/RF signals during locking state are output to prevent dead zone. · LD output becomes low when phase error is tWU or more. · LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. · tWU and tWL depend on OSCIN input frequency as follows. tWU 2/fosc : e.g. tWU 156.3 ns when fosc = 12.8 MHz tWU 4/fosc : e.g. tWL 312.5 ns when fosc = 12.8 MHz 13 MB15F73UL MB15F73UL TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) fout Oscilloscope 1000 pF VpIF VCCIF 0.1 µF 1000 pF S.G. 50 0.1 µF 1000 pF LD/fout DoIF VpIF PSIF VCCIF GNDIF XfinIF finIF GND OSCIN 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 DoRF VpRF PSRF VCCRF GNDRF XfinRF finRF LE Data 50 Clock 1000 pF Controller (divide ratio setting) 1000 pF VpRF 0.1 µF VCCRF 0.1 µF Note : The terminal number shows that of TSSOP-20 TSSOP-20. 14 50 S.G. S.G. MB15F73UL MB15F73UL TYPICAL CHARACTERISTICS 1. fin input sensitivity RF-PLL input sensitivity vs. Input frequency 10 PfinRF (dBm) 0 SPEC -10 -20 -30 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC -40 -50 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 finRF (MHz) IF-PLL input sensitivity vs. Input frequency 10 PfinIF (dBm) 0 SPEC -10 -20 -30 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC -40 -50 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 finIF (MHz) 15 MB15F73UL MB15F73UL 2. OSCIN input sensitivity Input sensitivity vs. Input frequency 10 Input sensitivity VOSC (dBm) SPEC 0 -10 -20 -30 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC -40 -50 -60 0 50 100 150 200 Input frequency fOSC (MHz) 16 250 300 MB15F73UL MB15F73UL 3. RF-PLL Do output current · 1.5 mA mode IDO - VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 -10.0 0.0 2.0 1.0 3.0 Charge pump output voltage VDO (V) · 6.0 mA mode IDO - VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 -10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) 17 MB15F73UL MB15F73UL 4. IF-PLL Do output current · 1.5 mA mode IDO - VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 -10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) · 6.0 mA mode IDO - VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 -10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) 18 MB15F73UL MB15F73UL 5. fin input impedance finIF input impedance 4 : 17.586 -152.84 1.7356 pF 600.000 000 MHz 1 : 942.56 -1.0998 k 50 MHz 2 : 102.27 -453.08 200 MHz 3 : 30.813 -231.69 400 MHz 1 2 4 START 50.000 000 MHz 3 STOP 600.000 000 MHz finRF input impedance 4 : 9.8589 -12.918 5.4757 pF 2 250.000 000 MHz 1 : 110.8 -450.61 200 MHz 2 : 10.215 -85.023 1 GHz 3 : 8.248 -46.791 1.5 GHz 4 1 3 START 200.000 000 MHz 2 STOP 2 250.000 000 MHz 19 MB15F73UL MB15F73UL 6. OSCIN input impedance OSCIN input impedance 4 : 25.625 -708.63 2.246 pF 100.000 000 MHz 1 : 12.925 k -13.855 k 3 MHz 2 : 453.87 -3.5288 k 20 MHz 4 1 2 3 START 3.000 000 MHz 20 STOP 100.000 000 MHz 3 : 112.38 -1.7836 k 40 MHz MB15F73UL MB15F73UL REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage) Test Circuit S.G. OSCIN Do LPF fin fVCO = 1607 MHz VCC = 3.0 V KV = 30 MHz/V VVCO = 2.3 V fr = 25 kHz Ta = + 25 °C fOSC = 14.4 MHz CP : 6 mA mode LPF VCO : FUJITSU MEDIA DEVICES (VC-2R3A50-1619 VC-2R3A50-1619) 20 k Spectrum Analyzer VCO 4700 pF 3.6 k To VCO 68 pF 0.039 µF · PLL Reference Leakage ATTEN 10 dB RL -5.0 dBm VAVG 0 10 dB/ MKR -71.34 dB 25.0 kHz MKR 25.0 kHz -71.34 dB CENTER 1.6070000 GHz RBW 1.0 kHz VBW 1.0 kHz SPAN 200.0 kHz SWP 500 ms · PLL Phase Noise ATTEN 10 dB RL -5.0 dBm VAVG 38 10 dB/ MKR -47.16 dB 4.67 kHz MKR D 4.67 kHz S -47.16 dB CENTER 1.60700000 GHz RBW 100 Hz VBW 100 Hz SPAN 20.00 kHz SWP 1.60 s (Continued) 21 MB15F73UL MB15F73UL (Continued) PLL Lock Up time PLL Lock Up time 1607 MHz1631 MHz within ± 1 kHz L chH ch 1.09 ms 1631 MHz1607 MHz within ± 1 kHz H chL ch 1.28 ms 1.631004000 GHz 1.607004000 GHz 1.631000000 GHz 1.607000000 GHz 1.630996000 GHz 1.606996000 GHz 0.00 s 22 2.500 ms 500.0 µs/div 5.000 ms 0.00 s 2.500 ms 500.0 µs/div 5.000 ms MB15F73UL MB15F73UL APPLICATION EXAMPLE OUTPUT VCO from controller LPF 2.7 V 1000 pF 1000 pF 2.7 V 0.1 µF 0.1 µF Clock DATA LE finRF XfinRF GNDRF VCCRF PSRF VpRF DoRF 20 19 18 17 16 15 14 13 12 11 MB 15F73UL 15F73UL 1 2 3 4 5 6 7 8 9 10 OSCIN GND finIF XfinIF GNDIF VCCIF PSIF VpIF DoIF LD/fout Lock Det. 1000 pF 1000 pF 1000 pF 2.7 V 0.1 µF 2.7 V 0.1 µF TCXO OUTPUT VCO LPF Notes : ·Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) . ·The terminal number shows that of TSSOP-20 TSSOP-20. 23 MB15F73UL MB15F73UL USAGE PRECAUTIONS (1) VCCRF, VpRF, VCCIF and VpIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device ORDERING INFORMATION Part number Package MB15F73ULPFT MB15F73ULPFT MB15F73ULPVA MB15F73ULPVA 24 20-pin plastic TSSOP (FPT-20P-M06 FPT-20P-M06) 20-pad plastic BCC (LCC-20P-M05 LCC-20P-M05) Remarks MB15F73UL MB15F73UL PACKAGE DIMENSIONS 20-pin plastic TSSOP (FPT-20P-M06 FPT-20P-M06) Note 1 ) * : These dimensions do not include resin protrusion. Note 2 ) Pins width and pins thickness include plating thickness. * 6.50±0.10(.256±.004) 0.17±0.05 (.007±.002) 20 11 * 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part 1.05±0.05 (Mounting height) (.041±.002) LEAD No. 1 10 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8° +0.03 (0.50(.020) 0.10(.004) C 0.45/0.75 (.018/.030) +.001 0.07 ­0.07 .003 ­.003 (Stand off) 0.25(.010) 1999 FUJITSU LIMITED F20026S-2C-2 F20026S-2C-2 Dimensions in mm (inches) (Continued) 25 MB15F73UL MB15F73UL (Continued) 20-pad plastic BCC (LCC-20P-M05 LCC-20P-M05) 3.00(.118)TYP 3.60±0.10(.142±.004) 16 0.55±0.05 (.022±.002) (Mounting height) 11 11 0.25±0.10 (.010±.004) 16 0.50(.020) TYP 0.25±0.10 (.010±.004) INDEX AREA 3.40±0.10 (.134±.004) 2.70(.106) TYP "D" "A" 1 6 "C" 6 Details of "A" part 0.50±0.10 (.020±.004) 1 0.50(.020) TYP 2.80(.110)REF 0.075±0.025 (.003±.001) (Stand off) 0.05(.002) "B" Details of "B" part 0.50±0.10 (.020±.004) Details of "C" part Details of "D" part 0.50±0.10 (.020±.004) 0.30±0.10 (.012±.004) C0.20(.008) 0.60±0.10 (.024±.004) C 0.30±0.10 (.012±.004) 0.60±0.10 (.024±.004) 0.40±0.10 (.016±.004) 2001 FUJITSU LIMITED C20056S-c-2-1 Dimensions in mm (inches) 26 MB15F73UL MB15F73UL MEMO 27 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 / Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Yan An Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. 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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Strategic Business Development Dept.