MC9S12E128 HCS12 DRM064 T175-8/90 MC9S12E RS232 PWM10 IOC04 PSH02 MH100 PWM12 - Datasheet Archive

 

UPS Using MC9S12E128 Designer Reference Manual HCS12 Microcontrollers DRM064 Rev. 0 09/2004 freescale.com Single Phase On-Line

 

Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Designer Reference Manual HCS12 HCS12 Microcontrollers DRM064 DRM064 Rev. 0 09/2004 freescale.com Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Designer Reference Manual by: Ivan Feno, Pavel Grasblum and Petr Stekl Freescale Semiconductor Czech System Laboratories Roznov pod Radhostem, Czech Republic To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level 09/2004 0 Description Initial release Page Number(s) N/A Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 3 Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 4 Freescale Semiconductor Contents Chapter 1 Introduction 1.1 1.2 1.2.1 1.2.2 1.2.3 1.3 Application Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The UPS Topologies and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC9S12E128 MC9S12E128 Advantages and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 16 17 Chapter 2 System Description 2.1 2.2 System Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Chapter 3 UPS Control 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Charger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Factor Correction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc Step-Up Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inverter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PI and PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase-Locked Loop (PLL) Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 27 28 30 32 33 Chapter 4 Hardware Design 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.3 4.3.1 4.4 4.4.1 4.4.2 4.5 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Charger Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flyback Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and Current Sensing, Current Limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Charger Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary SMPS Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc Step-Up Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc Converter Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc Converter Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Factor Correction and Output Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 36 37 39 39 41 41 41 42 45 47 47 50 61 Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 5 Contents 4.5.1 4.5.2 4.5.3 4.5.4 PFC Booster Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFC Booster Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inverter Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inverter Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 64 68 71 Chapter 5 Software Design 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.2.14 5.2.15 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Variables and Defined Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process PLL Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process RMS Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Mains Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Sine Wave Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Button Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process LED Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Application State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process PFC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Sine Wave Reference (PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process dc Bus Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process dc/dc Step-Up Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Inverter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Battery Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Software Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization of Peripherals and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Time Execution and MCU Load Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Constant Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PI and PID Controller Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 73 73 76 76 76 76 76 76 76 76 77 78 78 78 78 78 78 78 80 83 83 85 85 Chapter 6 Tests and Measurements 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall Efficiency at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall Efficiency at Non-linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage THD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Factor Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response on Step Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 87 88 88 89 90 91 92 92 95 Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 6 Freescale Semiconductor Chapter 7 System Set-Up and Operation 7.1 7.1.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Setting of Mains Line System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Software Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Application Software Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Application PC Master Software Control Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Application Build. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Programming the MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Application Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 On-line Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Battery Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Remote Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Appendix A. Schematics A.1 A.2 A.3 A.4 A.5 A.6 Schematics of Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematics of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematics of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parts List of UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parts List of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parts List of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 115 117 119 123 124 Appendix B. References Appendix C. Glossary Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 7 Contents Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 8 Freescale Semiconductor Figures 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 5-1 Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Concept of UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC9S12E128 MC9S12E128 Controller Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall View of the UPS Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Charger Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFC Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hysteresis Control of Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Push-Pull Converter PWM Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc Step-Up Converter Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sine Wave Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverter Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulated PID Controller Response on Input Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Control of Non-Linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculation of Phase Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Concept of UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UPS Power Stage Block Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Charger Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Charger Transformer Winding Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-Stage Charging Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary SMPSs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolated Flyback Converter for Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flyback Power Transformer Layout of Windings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc Converter Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc Converter Simulation Model Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulated Magnetizing Voltage and Magnetic Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulated Primary Winding Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulated Secondary Winding Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulated Drain-to-Source and Gate-to-Source MOSFETs Voltages. . . . . . . . . . . . . . . . . . dc/dc Power Transformer Layout of Windings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverter MOSFET Power Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rectifier Diode Voltage and Current Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Voltage and Rectified Current Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFC Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFC Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inverter Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverter IGBT Gate Drive Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 16 19 20 20 21 21 22 26 27 28 28 29 30 31 31 32 34 35 36 38 40 41 42 44 47 48 49 51 53 54 55 56 58 59 61 62 63 69 70 74 Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 9 Figures 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 Application State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Background Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Structure of PMF Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Structure of ATD Conversion Complete Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TIM0 CH4 Input Capture Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Structure of TIM0 CH5 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Structure of TIM0 CH6 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CPU Load of UPS Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Non-Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Overall Efficiency at Linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Output Voltage and Current at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Overall Efficiency at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Output Voltage and Current at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Output Frequency in Synchronized Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Output Frequency in Free-running Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Output Voltage and Current at Non-linear Load - Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Output Voltage and Current at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power Factor Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Load Step from 20% to 100% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Load Step from 20% to 100% - Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Load Step from 100% to 20% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Load Step from 100% to 20% - Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 UPS Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 UPS Input and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 UPS Serial Ports and External Battery Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Execute Make Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 UPS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 UPS Project in FreeMaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Block Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Auxiliary Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Control Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 dc/dc Step-Up Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Analog Sensing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PFC and Inverter IGBT Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PFC and Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PFC Current Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 UPS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 10 Freescale Semiconductor Tables 2-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 5-1 5-2 5-3 6-1 A-1 A-2 A-3 On-Line UPS Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Battery Charger Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Input Design Parameters of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Required Parameters of Flyback Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Measured Values on the Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 dc/dc Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 dc/dc Transformer Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Digital PFC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PFC Inductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Design Parameters for Core P/N: T175-8/90 T175-8/90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 dc-bus Capacitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Output Inverter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 MKP 338 4 X2 Capacitor Reference Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Output Filter Inductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Design Parameters for Core P/N: T175-8/90 T175-8/90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Software Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Execution Time of Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Size of UPS Application Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Summary of Measured Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Parts List of UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Parts List of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Parts List of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor Freescale Semiconductor Internal Use Only Draft For Review - September 30, 2004 11 Tables Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 12 Freescale Semiconductor Internal Use Only Draft For Review - September 30, 2004 Freescale Semiconductor Chapter 1 Introduction 1.1 Application Outline This reference design describes the design of a single phase on-line uninterruptable power supply (UPS). UPSs are used to protect sensitive electrical equipment such as computers, workstations, servers, and other power-sensitive systems. This reference design focuses on the digital control of key parts of the UPS system. It includes control of a power factor correction (PFC), a dc/dc step-up converter, a battery charger, and an output inverter. The dc/dc converter and the output inverter are fully digitally controlled. The PFC and the battery charger are implemented by a mixed approach, where an MCU controls the signals for PFC current and battery current demands. The digital control is based on Freescale Semiconductor's MC9S12E128 MC9S12E128 microcontroller, which is intended for UPS applications. The reference design incorporates both hardware and software parts of the system including hardware schematics. 1.2 UPS Topologies and Features UPSs are divided into several categories according to their features, which come from the hardware topologies used. The three basic categories are: · Passive standby UPS · Line-interactive UPS · On-line UPS The category of the UPS defines the basic behaviors of the UPS, mainly the quality of the output voltage and the capability to eliminate different failures on the power line (power sags, surge, under voltage, over voltage, noise, frequency variation, and so on). NOTE Although specific tools, suppliers, and methods are mentioned in this document, Freescale Semiconductor does not recommend or endorse any particular methodology, tool, or vendor. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 13 Introduction 1.2.1 Passive Standby UPS Topology The common topology of the passive standby UPS is depicted in Figure 1-1. LINE FILTER BATTERY CHARGER AC ~ = DC = DC SWITCH AC ~ INVERTER + - Normal operation Backup operation BATTERY Figure 1-1. Passive Standby UPS Topology During normal operation, while the mains line (the power cord for the ac line) is available, the load is directly connected to the mains. The battery is charged by the charger, if necessary. If a power failure occurs, the switch switches to the opposite position, and the load is powered from the batteries. An inverter converts the battery dc voltage level to an ac mains level. The inverter generates a square wave output. The advantage of passive standby topology is its low cost and high efficiency. The disadvantage is limited protection against power failures. Because the load is connected to the mains line through the filter only, the load is saved against short sags and surges. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 14 Freescale Semiconductor UPS Topologies and Features 1.2.2 Line-Interactive UPS Topology The improved topology, called line-interactive, is showed in Figure 1-2. The functionality of the line-interactive UPS is similar to passive standby topology. During normal operation, the load is connected directly to the mains line (the power cord to the ac line). Besides the input filter, there is a transformer with taps connected between the mains line and the load. The transformer usually has three taps. It ensures that the output voltage can be increased or decreased relative to the mains line by typically 10 to 15%. The features of the line-interactive topology are similar to passive standby UPSs. The cost is still quite low and efficiency is high. The protection against power failures is improved by the possibility of keeping the output voltage within limits during under voltage or over voltage using the tap transformer. BYPASS AVR LINE FILTER BATTERY CHARGER AC ~ = DC = DC AC ~ SWITCH INVERTER + - Normal operation Backup operation BATTERY Figure 1-2. Line-Interactive UPS Topology Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 15 Introduction 1.2.3 On-Line UPS Topology Another topology, called on-line, is shown in Figure 1-3. This topology is also called double conversion. This name arises from the operating principle of an on-line UPS. When the UPS works in normal operation mode, while the mains line (or the power cord for the ac line) is available, the input voltage is rectified to the dc bus. The power factor correction ensures a sinusoidal current in phase with the input voltage. Then the UPS behaves as a resistive load. The output inverter converts the dc bus voltage back to a pure sinusoidal voltage. The dc/dc converter is connected to the dc bus and converts the battery voltage to the dc bus level. The converter is activated during a power failure, and delivers the energy stored in the batteries to the dc bus. The dc bus voltage is again converted to a pure sine voltage. A battery charger is used to charge the batteries. The charger can be powered from the mains line or from the dc bus. BYPASS RECTIFIER PFC IN DC = BATTERY CHARGER OUT AC AC ~ ~ DC = = DC INVERTER = DC DC-DC CONVERTER + - Normal operation Backup operation BATTERY Figure 1-3. On-Line UPS Topology As can be seen, the complexity of the on-line UPS is much greater than the other two topologies described in this section. This means that the cost is higher, and the efficiency is lower due to double conversion. However, the on-line UPS brings a much higher quality of delivered energy. The UPS generates a pure sine wave output with tight limits (typically ±2%). Besides the power failures eliminated by previous topologies, the on-line UPS avoids all the failures relating to frequency disturbance, such as frequency variation, harmonic distortion, line noise, or other shape distortions. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 16 Freescale Semiconductor MC9S12E128 MC9S12E128 Advantages and Features 1.3 MC9S12E128 MC9S12E128 Advantages and Features The MC9S12E MC9S12E Family is a 112-/80-pin low-cost 16-bit MCU family very suitable for UPS, SMPS, and motor control applications. All members of the MC9S12E MC9S12E Family contain on-chip peripherals including a 16-bit central processing unit (HCS12 HCS12 CPU), up to 256K bytes of Flash EEPROM, up to 16K bytes of RAM, three asynchronous serial communications interface modules (SCI), a serial peripheral interface (SPI), an inter-IC bus (IIC), three 4-channel 16-bit timer modules (TIM), a 6-channel 15-bit pulse-width modulator with fault protection module (PMF), a 6-channel 8-bit pulse width modulator (PWM), a 16-channel 10-bit analog-to-digital converter (ATD), and two 1-channel 8-bit digital-to-analog converters (DAC). The basic features of the key peripherals dedicated for UPS applications are listed below: · Two 1-channel digital-to-analog converters (DAC) with 8-bit resolution · Analog-to-digital converter (ATD) ­ 16-channel module with 10-bit resolution ­ External conversion trigger capability · Three 4-channel timers (TIM) ­ Programmable input capture or output compare channels ­ Simple PWM mode ­ Counter modulo reset ­ External event counting ­ Gated time accumulation · 6 PWM channels (PWM) ­ Programmable period and duty cycle ­ 8-bit 6-channel or 16-bit 3-channel ­ Separate control for each pulse width and duty cycle ­ Center-aligned or left-aligned outputs ­ Programmable clock select logic with a wide range of frequencies ­ Fast emergency shutdown input · 6-channel pulse width modulator with fault protection (PMF) ­ Three independent 15-bit counters with synchronous mode ­ Complementary channel operation ­ Edge and center aligned PWM signals ­ Programmable dead time insertion ­ Integral reload rates from 1 to 16 ­ Four fault protection shut down input pins ­ Three current sense input pins The MC9S12E MC9S12E Family is powerful enough to control on-line and line-interactive UPS topologies. The passive standby topology can be controlled by a simpler MCU (from the HC08 Family). Digital control has many advantages over separate analog control. Digital control is more flexible and allows easier tuning and changing of the UPS parameters. The intercommunication and interaction between all modules can implemented very efficiently because all modules are controlled by a single MCU. The UPS control area is very wide. Each topology can be implemented by different circuits. The circuits may differ by different control requirements. This reference design shows one of the ways to implement digital control of an on-line UPS. The design mainly focuses on low cost. A low-cost 16-bit MCU is used with simple analog circuits. Using a mixed approach to battery charging can also be cheaper than full digital control, depending on chosen circuit topology. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 17 Introduction Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 18 Freescale Semiconductor Chapter 2 System Description 2.1 System Concept The system concept of the UPS is shown in Figure 2-1. Input consists of a rectifier (D1, D5) and a power factor correction (L1, D2, Q2). The power factor correction is controlled by a mixed approach. The dc-bus voltage control loop of PFC is controlled by the MCU. The output of the voltage controller defines the amplitude of the input current. Based on the required amplitude, the MCU generates a current reference signal. The current reference signal inputs to an external logic, which performs current controller working in hysteresis mode. DC-AC PFC L1 D1 D2 KBU8J IN - Q1 + + Q2 D3 C1 IN C2 + Q3 D4 GND OUT D5 Filter OUT DC-DC Converter D6 D7 L2 D8 L3 Q4 T1 GND Q5 Charger (Flyback Converter) BT1 GND D9 GND Figure 2-1. System Concept of UPS Output is provided by an output inverter (Q1, Q3, D3, D4). The inverter converts the dc bus voltage back to a sinusoidal voltage using pulse-width modulation. The output inverter is fully controlled by the MCU and generates a pure sinusoidal waveform, free of any disturbance. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 19 System Description The battery BT1 supplies a load during the backup mode. There are two 12-V batteries connected in serial. The battery voltage level 24-V is converted to ±390-V by the dc/dc step-up converter (Q4, Q5, D6-D9, L2, L3, and T1) using a push-pull topology fully controlled by the MCU. The last part of a UPS is a battery charger. The battery charger maintains a fully charged battery. It uses a flyback topology controlled by a mixed approach. The flyback converter is controlled by a dedicated circuit and the required output voltage and current limit are set by the MCU. A dedicated circuit is used due to the lower cost compared to direct MCU control. Where a different battery charger topology is used, there is still enough MCU power to provide digital control. Figure 2-2. UPS Power Stage The UPS consists of four PCBs. Most components are situated on the power stage (see Figure 2-2). These are all the power components (diodes, transistors, inductors, capacitors, relays, and so on) and analog sensing circuits. The power stage is connected to the mains line (power cord for the ac line) through an input line filter, realized on the next PCB (Figure 2-3). Figure 2-3. Input Filter Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 20 Freescale Semiconductor System Concept Figure 2-4 shows the user interface PCB. It includes two buttons (ON/OFF, BYPASS), four status LEDs (on-line, on-battery, bypass, and error), and six LEDs indicating output power or remaining battery capacity. There are also two serial RS232 RS232 ports, which can used for communication with the PC. The user interface provides an extension of the serial ports, which are implemented on the MC9S12E128 MC9S12E128 controller board. Figure 2-4. User Interface Figure 2-5. MC9S12E128 MC9S12E128 Controller Board Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 21 System Description Figure 2-5 shows a controller board for the MC9S12E128 MC9S12E128. The MC9S12E128 MC9S12E128 controller board is designed as a versatile development card for developing real-time software and hardware products to support a new generation of applications in UPS, servo and motor control, and many others. The power of the 16-bit MC9S12E128 MC9S12E128, combined with Hall-effect/quadrature encoder interface, circuitry for automatic current profiling, over-current logic and over-voltage logic, and two isolated RS232 RS232 interfaces, makes the MC9S12E128 MC9S12E128 controller board ideal for developing and implementing many motor controlling algorithms, UPS, SMPS, as well as for learning the architecture and instruction set of the MC9S12E128 MC9S12E128 processor. For more detailed information on the MC9S12E128 MC9S12E128 controller board, see [33]. An overall view of the assembled UPS is shown in Figure 2-6. Figure 2-6. Overall View of the UPS Demo 2.2 System Specification The UPS is designed to meet the features and parameters mentioned in Table 2-1. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 22 Freescale Semiconductor System Specification Table 2-1. On-Line UPS Specification Features Parameters Single Phase On-Line UPS using MC9S12E128 MC9S12E128 Architecture and Concept The UPS should be a regenerative 1-phase online type UPS with an automatic bypass feature when self check fails or is overloaded. The UPS is controlled manually from a front panel switch and from PC application software. On-line: If the input power is available, the UPS supplies a load and eliminates all possible defects on the line (online double conversion) Battery: If the input power is not available, the UPS supplies a load from batteries. The backup time is given by battery capacity. Functional Modes Bypass: The UPS directly connects its output and input, so the load is directly connected to the input line. The transition to this mode is set manually or automatically during overload or fault Fault: If any fault is detected, the UPS signals fault, and if it is possible, the bypass is activated. 45 to 65 Hz Operating Frequency Range 120 V (at 25% of load) - 280 V Operating Voltage Range for nominal mains 230 V Input 85 V to 135 V Operating Voltage Range for nominal mains 110 V Power factor at input > 0.95 at nominal voltage Conversion efficiency > 85% at nominal output power Number of output ports 6 in 2 segments Output voltage selectable 110/120/200/220/230/240 V Output power 725 ­ 750 VA at 230 V mains input voltage Output Output power 325 ­ 350 VA at 110 V mains input voltage Output waveform: true sine wave < 5% THD Output frequency 50/60 Hz +/-0.3% Output load regulation +/-2% (at steady state and linear load) Battery Communication Battery 2*12 V Battery 7.2 Ah 2x RS232 RS232 port for communication with host PC with opto-isolation implemented on MC9S12E128 MC9S12E128 Controller Board 4 LED indicators (on-line, battery, bypass, fault) Visual Interface battery level gauge 6 levels (100%) Control Interface 2x buttons for user control (on/off, bypass) Fault Audible warning Overload low battery lasts 5 minute Implementation Coding in C language according to ANSI C standard for software running on MCUs Coding in assembler if needed for software running on MCUs Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 23 System Description Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 24 Freescale Semiconductor Chapter 3 UPS Control 3.1 Control Techniques Generally, a UPS consists of several different converters. So the control techniques differ with the converter topologies used. The presented implementation of on-line UPS includes following topologies: · Battery charger: flyback converter (mixed control) · PFC: boost converter (mixed control) · dc/dc step up converter: push-pull converter (full digital control) · Output inverter: half bridge inverter (full digital control) 3.1.1 Battery Charger Control The battery charger uses a flyback converter topology. As described in Chapter 4 Hardware Design, the flyback converter is controlled by a dedicated circuit in order to reduce cost. The interface between the flyback converter and the MCU incorporates one digital output, which allows the setting of two output voltage levels, and an analog output, which sets the current limit. Using a dedicated circuit greatly simplifies the control algorithm. The functionality of the converter itself is ensured by the dedicated circuit. Therefore, the battery charger software focuses on the charging algorithm, whose software block diagram is shown in Figure 3-1. The algorithm reads the current flowing to the batteries. The current value is compared with the maximal and float thresholds. If the value is close to the maximal value, the battery charger state is set to bulk charging and the output voltage level is set to the higher value (PU7 set to logic 1). If the actual current value is between the maximal and float thresholds, the battery charger is considered to be in the absorption state. The output voltage is still kept at a high level. As soon as the current value reaches the float threshold, the battery charger goes to the float state, and the output voltage is set to the lower level. The current limit is set during initialization, according to the number of batteries and their capacity. The control algorithm is called every 50 ms. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 25 UPS Control MC9S12E128 MC9S12E128 Output Voltage PU7 Charging Current Limit PWM10 PWM10 yes IBAT = Imax no Bulk mode Set HV level yes IBAT > 0.05C no Absorption mode Set HV level Float mode Set LV level Battery Voltage AN03 AN02 Battery current Figure 3-1. Battery Charger Algorithm Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 26 Freescale Semiconductor Control Techniques 3.1.2 Power Factor Correction Control The control algorithm of the PFC is depicted in Figure 3-2. The algorithm includes two control loops. The inner control loop maintains a sinusoidal input current. The outer loop controls the dc bus voltage. The result of the outer control loop is the desired amplitude of the input current. MC9S12E128 MC9S12E128 PFC ENABLE PU8 DA0 UREQ + PI Controller + - SIN REFERENCE SINUS GENERATION IOC04 IOC04 Zero Cross PLL LOCK FAULT1 FAULT0 F I L T E R Top DC Overvoltage Bottom Overvoltage AN07 Top DC Bus Voltage AN08 Bottom DC Bus Voltage Figure 3-2. PFC Control Algorithm The current control loop is partially performed by an external circuit. This control technique is also called "indirect PFC control". The external circuit compares the actual input current with a sine wave reference. If the actual current crosses the lower border of sine waveform, the PFC transistor is switched on. As soon as the input current reaches the upper border, the PFC transistor is switched off. The resulting input current can be seen in Figure 3-3. Maximal switching frequency (50 kHz) corresponds to the hysteresis defined by resistors R664 and R675. (see Figure 4-20) Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 27 UPS Control Sine Reference Hysteresis Levels Input current Figure 3-3. Hysteresis Control of Input Current The software part of the current loop generates the sine wave reference. The sine wave reference is synchronized to be in phase with the input voltage. The sine wave generator is calculated every 50 µs. The sine waveform is generated directly by the D/A converter within the range of the voltage reference. The voltage control loop is fully implemented by software. The sensed dc bus voltage is compared with the required dc bus voltage, 390 V. The difference inputs to the PI controller. The PI controller output directly defines the amplitude of the input current. The PI controller constants were experimentally tuned to get an aperiodic responds to the input step. The constants are P = 100 and T I = 0.016 s. The voltage control loop is calculated every 1 ms. The two hardware faults are immediately able to disable the PWM outputs in case of a dc bus over voltage. The digital output, PU8, enables/disables the external logic providing the current loop. 3.1.3 dc/dc Step-Up Converter Control The dc/dc converter uses push-pull topology, which requires the PWM signals as shown in Figure 3-4. These signals can be generated by one pair of PMF outputs with the following configuration: · even output is set to positive polarity · odd output is set to negative polarity · duty cycle of even output is set to X% · duty cycle of odd output is set to 100 - X% where X is a value from 0 to 50% ­ dead time The required PWM patterns are shown in Figure 3-4. PWM 4 PWM 3 Figure 3-4. Push-Pull Converter PWM Patterns Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 28 Freescale Semiconductor Control Techniques The control algorithm is depicted in Figure 3-5. Both dc bus voltages pass the digital filter, and their sum is compared with the required value of the dc bus voltage. Based on the error, the PI controller sets the desired duty cycle of the switching transistors. During mains line operation, the required value of the dc bus is set to 720 V (2 x 360 V). Because the dc bus is kept by the PFC at 780 V (2 x 390 V), the dc/dc converter is automatically switched off. In case of mains failure, the dc bus voltage will start to fall. As soon as the voltage reaches the value 720 V, the dc/dc converter is activated. At 720 V, there is still 20 V reserve in amplitude to generate a maximum output voltage of 240 V RMS. As soon as the operation from batteries is recognized, the required value of the dc bus voltage is increased back to 780 V. The PI controller maintains the constant voltage on the dc bus independent of the load until the mains is restored or the battery is fully discharged. If the battery is discharged, the UPS output is deactivated and UPS stays in STANDBY ON BATTERY mode. After 1 minute, the UPS is switched off. The PI controller constants were experimentally tuned in the same way as the PFC. The constants are P = 39 and TI = 0.0033 s. The control loop is calculated every 1 ms. MC9S12E128 MC9S12E128 PMF3 Output Transistors UREQ PMF4 + - PI Controller FAULT1 FAULT0 + + F I L T E R Top DC Overvoltage Bottom DC Overvoltage AN07 Top DC Bus Voltage AN08 Bottom DC Bus Voltage Figure 3-5. dc/dc Step-Up Converter Control Algorithm Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 29 UPS Control 3.1.4 Output Inverter Control The output inverter is implemented by two IGBT transistors in half bridge topology. The inverter is fully digitally controlled and generates a pure sine wave voltage. The sine waveform is generated using the pulse-width modulation technique. The sine reference is stored in a look-up table. The table values are periodically taken from the table, and then multiplied by the required amplitude. The resulting value gives the duty cycle of the PWM output. The pointer to the table is incremented by a value, which corresponds to the desired output frequency. All values over one period give sinusoidal modulated square wave output (see Figure 3-6). If such a signal passes through a LC filter, the pure sine wave voltage is generated on the inverter output. +DCBUS -DCBUS Figure 3-6. Sine Wave Modulation The control algorithm can be seen in Figure 3-7. The main control loop comprises of the PID controller and a feed forward control technique. The required value entering the PID controller is generated by a sine wave generator, optionally synchronized with input voltage. The same value is added directly to the output of the PID controller. It is called the feed forward technique, and it improves the responds of control loop. The amplitude of the sine wave reference is corrected by RMS correction, which keeps the RMS value of the output voltage independent of any load. The RMS correction uses the PI controller. The PI constants were experimentally tuned, and set to P = 0 and TI = 0.00936. The PID controller was tuned using simulation in MATLAB. The results of the simulation can be seen in Figure 3-8 and Figure 3-9, with P = 0.6, TI = 0, TD = 0.00071 s, and N = 31. The value N represents the filter level of D portion EQ 3-5. The result of the PID controller, including feed forward, is scaled relative to actual dc bus voltage. Then the exact duty cycle is set to the PMF module. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 30 Freescale Semiconductor Control Techniques Figure 3-7. Inverter Control Algorithm Figure 3-8. Simulated PID Controller Response on Input Step Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 31 UPS Control Figure 3-9. Quality Control of Non-Linear Load 3.1.5 PI and PID Controller The PI controller in a continuous time domain is expressed by following equation: 1u ( t ) = K e ( t ) + -TI t e ( ) d (EQ 3-1) de ( ) d + T D - e ( t ) dt (EQ 3-2) 0 Similarly, the PID controller can be expressed as: t 1u ( t ) = K e ( t ) + -TI 0 In a Laplace domain it can be written as: 1 u ( s ) = K e ( s ) + - e ( s ) sT I (EQ 3-3) 1 u ( s ) = K e ( s ) + - e ( s ) + sT D e ( s ) sT I (EQ 3-4) To improve the response of the PID controller to noisy signals, the derivative portion is often replaced by a derivative portion with filter: sT D sTD -sT D 1 + -N (EQ 3-5) For implementation of algorithms on MCU the equations EQ 3-3 and EQ 3-4 have to be expressed in discrete time domain like: u ( kh ) = P ( kh ) + I ( kh ) + D ( kh ) (EQ 3-6) Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 32 Freescale Semiconductor Control Techniques where P ( kh ) = K e ( kh ) (EQ 3-7) Kh I ( kh ) = I ( kh ­ h ) + - e ( kh ) TI (EQ 3-8) TD KT D N D ( kh ) = - D ( kh ­ h ) ­ - e ( kh ­ h ) T D + Nh T D + Nh (EQ 3-9) e ( kh ) = w ( kh ) ­ m ( kh ) (EQ 3-10) and e(kh) = Input error in step kh w(kh) = Desired value in step kh m(kh) = Measured value in step kh u(k) = Controller output in step kh P(kh) = Proportional output portion in step kh I(kh) = Integral output portion in step kh D(kh) = Derivative output portion in step kh TI = Integral time constant T, h = Sampling time K = Controller gain t = Time s = Laplace variable N = Filter constant 3.1.6 Phase-Locked Loop (PLL) Algorithm The PLL algorithm provides synchronization with the mains line. This synchronization is necessary for the PFC algorithm and can be optionally used for the inverter output. The algorithm consists of two parts: · Frequency lock · Phase lock Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 33 UPS Control The PLL algorithm measures a period from last two zero crossing signals. Because calculation of the phase increment to the sine wave table requires a division instruction EQ 3-11, the phase over one-half period is calculated instead: T Phase Increment = 32767 -Period (EQ 3-11) where T = period of sine wave algorithm (50 µs) 32767 = 180º in sine wave look up table Period = measured period of main line voltage If phase increment just corresponds to the measured period we should get a phase of 180º. If there is some difference, the phase increment must be adjusted (see Figure 3-10). Based on the sign of the phase difference, the phase increment is incremented or decremented by the value which is equal to the phase difference multiplied by the PLL constant. If the phase difference falls below some limit for last 20 periods, the PLL is locked to the line frequency and a frequency locked status bit is set. Actual Period Zerocrossing Signal Actual Phase 180º 0º Actual Phase Increment Phase Difference Figure 3-10. Calculation of Phase Difference Now the PLL is running with the same frequency as the mains line, but the phase is still different. As soon as the frequency status bit is set, the actual phase is adjusted to 0º or 180º according to the previous polarity of the input voltage. The polarity of the input voltage is sensed in the middle of each period. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 34 Freescale Semiconductor Chapter 4 Hardware Design 4.1 System Configuration The single phase on-line UPS reference design is 750 VA UPS representing an on-line topology. The UPS comprises four PCBs (power stage, user interface, input filter, and controller board). The power stage together with the MC9S12E128 MC9S12E128 controller board is shown in Figure 1-2 Figure 4-1. System Concept of UPS The UPS reference design provides both a ready-to-use hardware and a ready-made software development platform for an on-line UPS, under 1000 VA output power, and controlled by a single 16-bit MCU. The UPS power stage consists of several system blocks shown as: · Battery Charger · Auxiliary Power Supplies · Control Board Interface · dc/dc Step-Up Converter · PFC + Inverter Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 35 Hardware Design J101 PSH02 PSH02_02P J100 J104 J103 1 2 J102 Auxiliary Power Supplies +VBAT -5V_TOP GND_TOP +15V_TOP -5V_BOT GND_BOT +15V_BOT +VBAT GND_PFC +15V_PFC FUSE AUTO 40A +5V_A +5V_D +15V 3 4 +5V_REF 1 2 GNDA GND /POWER_EN POWER_EN F101 Battery Charger L J105 L N F102 +5V_A +5V_A GNDA GND 6.3A/fast GNDA /POWER_ON GND F100 +VBAT -VBAT +15V +5V_D +5V_A +15V_TOP -5V_TOP -5V_BOT GND_BOT +15V_PFC GNDA VBAT IBAT J106 GND_TOP +15V_BOT GND HV_BAT_LEVEL IBAT_CONTROL 2A/fast N +VBAT -VBAT GND_PFC +5V_REF -5V_TOP GND_TOP +15V_TOP -5V_BOT GND_BOT +15V_BOT GND_PFC +15V_PFC +5V_A +5V_D +15V L1 L2 N PE PE MH100 MH100 GNDA GND +5V_REF PFC+Inverter PE CONNECTION PWM_TOP PWM_BOT J107 Control Board Interface OUT1 OUT2 N_OUT DCB_POS DCB_NEG RLY_IN RLY_BYPASS RLY_OUT1 RLY_OUT2 FAULT0 FAULT1 AD2 AD3 J108 FAN_PWM V_DCB_TOP V_DCB_BOT V_IN I_IN V_OUT_TOP V_OUT_BOT I_OUT TEMP +5V_D +5V_A +15V PWM10 PWM10 PWM12 PWM12 TIM14 TIM14 TIM15 TIM15 TIM16 TIM16 TIM17 TIM17 DIV1 DIV2 UNI-3 PFC_EN PFC_ZC GND GNDA GND +5V_D +5V_A +15V DA0 DA1 GNDA J109 FAN+ FAN- J110 1 2 AD1 AD4 UNI-3_PWM2 AD5 UNI-3_PWM3 AD6 UNI-3_PWM4 UNI-3 PHAIS UNI-3_PWM5 UNI-3 PHCIS UNI-3 DCBI UNI-3 PFC_EN UNI-3 DCBV UNI-3 SERIAL PSH02 PSH02_02P J111 1 2 PSH02 PSH02_02P UNI-3 BEMFZCA UNI-3 BEMFZCC UNI-3 BEMFZCB UNI-3 PFC_ZC DA0 DA1 Fault1 Fault0 DC-DC Step Up GND GNDA GND GNDA +VBAT -VBAT +VBAT -VBAT DCB_POS DCB_NEG PWM4 PWM5 Figure 4-2. UPS Power Stage Block Schematic 4.2 Battery Charger 4.2.1 Operational Description The battery charger is intended for charging the UPS batteries and supplying all UPS control circuits. The battery charger provides a three-state charging algorithm fully controlled by the MCU. Its operating parameters are listed in Table 4-1. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 36 Freescale Semiconductor Battery Charger Table 4-1. Battery Charger Parameters Input voltage 80 to 280 V / 50 to 60 Hz Output voltage High voltage level Low voltage level 29.4 V 27.4 V Max. value Absorption - float threshold 1.8 A 0.36 A Output current NOTE The output values are set to the values recommended by the battery manufacturer. The current limits can be set to any value by SW. 4.2.2 Battery Charger Topology The battery charger uses a flyback topology, frequently used for its simplicity for output power below 100 W. The charger consists of a flyback converter, battery voltage and current sensing, current limitation, and mains line voltage detection. The schematic of the battery charger is shown in Figure 4-3.The flyback converter uses the dedicated circuit TOP249 for control, which incorporates a MOSFET transistor and control circuit in one package. Using this dedicated circuit allows connection of the control signals to the secondary side of the flyback converter without galvanic isolation. The second advantage of the solution is that UPS power is independent of MCU control, and the UPS is able to run without batteries. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 37 C302 220uF/450V + D302 B250R B250R D303 P6KE200 P6KE200 C301 + L 4.7nF T300 1 R302 1M 9 R306 1M 5 R303 24k D304 - 6 D305 BYV26C BYV26C +VBAT 47uH LINE_OK R301 68k 1N4148 1N4148 TR02/MC145 TR02/MC145 29.4V @ Q4 ON 27.4V @ Q4 OFF L300 13 7 N TP300 TP300 Vbat D301 BYW29E-200 BYW29E-200 R304 39k C303 220uF/50V 100nF C304 R305 1k8 220uF/50V 100u/50 + + R307 620 + C306 C305 R309 2k4 5.05V @ 39V VBAT D 7 GND_TR 2 CONTROL F 4 L301 47uH L TOP249Y R300 0.1 C 1 ISO300 ISO300 SFH615A-2 SFH615A-2 4 X GND_CH 1 3 C316 100n R315 7.5k IBAT1 R329 1K R313 27R 5 3 sense U300 R312 200 G D300 1N4148 1N4148 S -VBAT GND IBAT2 GNDA 2 R314 HV_BAT_LEVEL 100 + C307 47uF/10V C315 100n Q301 MMBF0201NLT1 MMBF0201NLT1 sense R311 33k R310 5K6 R308 3K6 R331 100 IBAT2 5 MC33502 MC33502 U301B U301B 7 8 3 2 + - 100k U301A U301A MC33502 MC33502 220n Q300 8 BC847 BC847 U302 TL431ACD TL431ACD GND C314 N/P R323 1k GND_CH R326 3k9 IBAT R324 1k IBAT_CONTROL LINE_OK R327 560 C311 C310 470nF GND 4.875V @ 2.34A GND R318 1 100K R325 33K GND_CH 1 C300 R320 R322 220 D309 5V1 100nF C308 4 6 + R319 1k6 R321 1k6 +5V_A C309 470nF - IBAT1 R317 33K 6 R316 220 C312 D307 10nF/100V BAV103 BAV103 470nF R328 C313 D308 BAV103 BAV103 100nF/100V GND /POWER_ON 68K D R330 10k GND GND_TR Figure 4-3. Battery Charger Schematics G Q302 S MMBF0201NLT1 MMBF0201NLT1 GND Battery Charger 4.2.3 Flyback Converter Operation The flyback converter consists of the transformer T300, the MOSFET transistor U300 include control circuit and the feedback circuit (R303, R305, R309, R312, Q301, ISO300 ISO300, and U302). When the MOSFET transistor (U300) is switched on, the magnetic field energy is accumulated in the magnetic core of the transformer T300. During this time the output diodes (D301, D304) are reverse biased. As soon as the transistor is switched off, the accumulated magnetic field energy is released through the forward biased output diodes (D301, D304) to the output capacitors (C304, C305), and through the output filter (L300, L301, C306) to the load. The output voltage is sensed by the divider (R303, R305, R309, R312). The voltage from the divider is compared with the internal reference of U302. The U302 creates the control signal-the current flowing through the opto coupler (ISO300 ISO300)-which galvanically isolates the primary and secondary side of the flyback converter. The control signal is connected to the control pin of the control circuit (U300). According to the control signal, the duty cycle of the MOSFET transistor (U300) is set. The MOSFET transistor is switched with a fixed frequency of 66 kHz. The resistor R312 can be shorted by the transistor Q301. This allows setting the output voltage to either 29.4 or 27.4 V by the MCU. 4.2.4 Design of Flyback Converter The design of flyback converter using TOP249 is described in detail in [10], [11] and [12]. The following input parameters were considered during the converter design: Table 4-2. Input Design Parameters of Flyback Converter Input voltage 80 to 280 V / 50 to 60 Hz Max. output voltage 29.4 V Max. output current 1.8 A Switching frequency 66 kHz The calculated parameters of the flyback transformer are specified in Table 4-3. The measured values on the manufactured sample are listed in Table 4-4. To decrease leakage inductance, the interleaved winding layout is used for the primary winding. The complete transformer winding layout is shown in Figure 4-4. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 39 Hardware Design 2.5kV insulation layer 20T Cu f 4x0.315mm 2.5kV insulation layer 12T Cu f 3x0.56mm 2.5kV insulation layer 5T Cu f 2x0.315mm 2.5kV insulation layer 20T Cu f 4x0.315mm L4 L3 L2 L1 14 Core ETD29/16/10 ETD29/16/10 N87 B66358-G-X187 B66358-G-X187 ETD29/16/10 ETD29/16/10 N87 B66358-G500-X187 B66358-G500-X187 Coil former B66359-J1014-T1 B66359-J1014-T1 Yoke B66359-A2000 B66359-A2000 8 L3 1pcs 1pcs 1pcs 2pcs L1 (EPCOS components) L4 L2 1 7 Figure 4-4. Battery Charger Transformer Winding Layout Table 4-3. Required Parameters of Flyback Transformer Magnetizing inductance referred to the primary 328 mH + 3 0 ­ 20% Magnetizing inductance referred to the secondary 31µH + 30 ­ 20% Total leakage inductance referred to the primary > -200W -200W 7.92m 2.208ms 1 W(M3) 2.212ms 2 S(W(M3) 2.216ms 2.220ms 2.224ms 2.228ms 2.232ms Time Figure 4-16. Inverter MOSFET Power Analysis Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 58 Freescale Semiconductor dc/dc Step-Up Converter The use of a single transistor with a higher rated drain current is also possible, however, the copper lead utilization is rather high even though manufacturers define the value around 75 A as a limit for TO220 package leads. 4.4.2.3 Rectifier Diodes Rated diode voltage is given by the voltage waveform applied to the diode. However, diode voltage waveforms are different from that of the MOSFETs since the rectifier diodes are placed in a different topology. As the rectifier is current-loaded there is no natural clamp for over voltage spikes at the instant of a diode reverse recovery. That is why a suitable snubber has to be implemented in order to cut-off the excess energy that could possibly overheat the diode chip by internal avalanche. As dc/dc converter nominal output voltage is 2x390V (Figure 4-18 shows secondary voltage of the power transformer), and during dynamic conditions it can reach 2 x 420 V, the possibility of selecting the diode voltage rating is constrained. Figure 4-17 shows waveforms of the rectifier diode voltage and current. In this case, diodes with a break-down voltage of 1200V are selected. 1 0.5KV 2 1.5A 1.0A 0V 0.5A -0.5KV 0A >> -1.0KV -0.5A 2.3075ms 2.3100ms 1 V(D1:1,D1:2) 2 2.3150ms I(D1) 2.3200ms 2.3250ms 2.3300ms Time Figure 4-17. Rectifier Diode Voltage and Current Waveform When choosing the rectifier current rating, similarly as with the MOSFETs, the anode effective current and switching frequency have to be considered. Simulation results for the nominal anode effective current shows a value of 0.54 A and a 1.3 W power loss. Because the power loss is rather high for a practical usage of the DO241 DO241 package, diodes with a fully-isolated TO220 package are chosen. One possibility is to use of the Fairchild ultrafast diode FFPF05U120S FFPF05U120S with 5-A rated current, 1200 V rated voltage, and 100ns reverse recovery time, which is good enough for 50 kHz switching frequency. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 Freescale Semiconductor 59 Hardware Design 4.4.2.4 Filter Chokes A basic design consideration when implementing a filter choke is to look at the rectified current ripple. For an output current level in the range of 0.5 to 2 A, the relative ripple ri can be considered in the range of 50 to 20%. Let ri equal 30% for nominal conditions. Then the filter choke inductance value is given by EQ 4-30: M AX T T L = V L - = [ ( V IN ­ V LOSS ) p ­ V OU T ] -r i I OUT i (EQ 4-30) ­6 0.98 10 ×10 L = [ ( 24 ­ 1.6 ) 18 ­ 390 ] - = 583 µH 0.3 0.74 (EQ 4-31) where VL = voltage across the choke when active cycle = the time during active cycle i = current ripple VIN = nominal input voltage VLOSS = voltage drop on resistive components (RDS(ON), transformer primary, etc.) p = transformer primary to secondary ratio VOUT = nominal output voltage MAX = maximal switching duty cycle ri = relative current ripple IOUT = nominal output current Filter choke performance is analyzed by simulation, and the results (Figure 4-18) verified a good design procedure. Choke PCV2-564-02 PCV2-564-02 from Coilcraft, with 560 µH inductance and 2 A saturation current, is chosen. Single Phase On-Line UPS Using MC9S12E128 MC9S12E128 60 Freescale Semiconductor Power Factor Correction and Output Inverter 1 800mA 2 1.0KV 400mA 0.5KV 0A 0V -400mA -0.5KV -800mA >> -1.0KV 1.900ms 1 1.905ms 1.910ms 1.915ms I(L16) I(L17) 2 V(R3:2,R4:2) 1.920ms 1.925ms 1.930ms 1.935ms 1.940ms Time Figure 4-18. Secondary Voltage and Rectified Current Waveforms 4.5 Power Factor Correction and Output Inverter 4.5.1 PFC Booster Operational Description This section deals with a design of the power factor correction booster (PFC). The PFC forms the input stage of the UPS. It is a switchmode power converter, which provides an a.c. input current waveform that is sinusoidal and in phase with the line voltage. The power factor is