DPDD16MX8RSAY5 IPC-A-610 30A223-00 A0-A11 A10/AP DPDD16MX8RSBY5 53A004-00 - Datasheet Archive

 

128 Megabit CMOS DDR SDRAM DPDD16MX8RSAY5 DESCRIPTION: FEATURES: · Electrical characteristics meet semiconductor

 

ADVANCE D COM P ON E NTS PACKAG I NG 128 Megabit CMOS DDR SDRAM DPDD16MX8RSAY5 DPDD16MX8RSAY5 DESCRIPTION: FEATURES: · Electrical characteristics meet semiconductor manufacturers' datasheet · Memory organization: (2) 64Mb memory devices. Each device arranged as 16M x 4 bits (4M x 4 bits x 4 banks) · Memory stack organization: 16M x 8 bits (4M x 8 bits x 4 banks) · JEDEC approved, 1 Rank stack pinout and footprint (with 1 CSs and 1 CKEs) · Optimized for RDIMMs · IPC-A-610 IPC-A-610, class 2, manufacturing standards · Lead free manufacturing process · Package: 66-Pin TSOPII stack L PIN NAMES Row Address: Column Address: BA0, BA1 Auto Precharge DQ0-DQ7 Chip Select RAS Row Address Strobe WE Data Write Enable CK, CK Differential Clock Inputs CKE Clock Enable DQS Data Strobe DM Data Mask VDD Power Supply VSS Ground VDDQ DQ Power Supply VSSQ DQ Ground VREF SSTL_2 Reference Voltage NC No Connect DNU Do Not Use 30A223-00 30A223-00 REV. E 2/03 A0-A11 A0-A11 A0-A9 CS CKE RAS CAS WE CK CK VREF DQS DM A0-A11 A0-A11 BA0-BA1 This document contains information on a product presently under development at DPAC Technologies. DPAC reserves the right to change products or specifications herein without prior notice. (4M x 4 bits x 4 banks) FUNCTIONAL BLOCK DIAGRAM (4M x 4 bits x 4 banks) R P (TOP VIEW) VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS Column Address Strobe CS 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 Data In/Data Out CAS 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Bank Select Address A10/AP A10/AP E A0-A11 A0-A11 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD DNU NC WE CAS RAS CS NC BA0 BA1 A10/AP A10/AP A0 A1 A2 A3 VDD 64 Mb DDR SDRAM I M I N A R Y 1 The Memory StackTM series is a family of interchangeable memory devices. The 128 Mb, CMOS DDR Synchronous DRAM assembly utilizes the space saving LP-StackTM technology to increase memory density. This stack is constructed with two 64Mb (16M x 4) DDR SDRAMs. PINOUT DIAGRAM This 128 Mb LP-StackTM, has been designed to fit in the same footprint as the 64Mb (16M x 4) DDR SDRAM VDD 1 66 VSS TSOPII monolithic. This allows system upgrade without DQ0 2 65 DQ7 VDDQ 3 64 VSSQ electrical or mechanical redesign, providing an alternative NC 4 63 NC low cost memory solution. DQ1 5 62 DQ6 DQ0-DQ7 1 128 Megabit CMOS DDR SDRAM DPDD16MX8RSBY5 DPDD16MX8RSBY5 ORDERING INFORMATION DP DD PREFIX TYPE 16M X 8 R S A Y5 MEMORY DESIG MEMORY DESIG I/O TYPE DEVICE PACKAGE DEPTH WIDTH WIDTH - DP - XX X XX SUPPLIER XX MFR ID MFR CLOCK CAS REV SPEED LATENCY CAS LATENCY CLOCK SPEED (ns) BLANK X REVISION NOT SPECIFIED MANUFACTURER DIE REVISION MANUFACTURER CODE * SUPPLIER CODE* STACKABLE TSOP x4 MEMORY BASED SSTL INPUTS/OUTPUTS 64 MEGABIT BASED MEMORY MODULE WITHOUT SUPPORT LOGIC Y DOUBLE DATA RATE SYNCHRONOUS DRAM NOTES: 1. AC Parameters of base memory are unchanged from device manufacturers' specifications. 2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 53A004-00 for further information. 3. For assembly and inspection procedures, refer to application note 53A001-00 53A001-00. 4. Maximum reflow temperature recommendation is 215°C. I N A R * Contact your sales representative for supplier and manufacturer codes. I M MECHANICAL DIAGRAM TOP VIEW PIN 1 INDEX SIDE VIEW BOTTOM VIEW E L 1 .0256 [.65] TYP P R .891 MAX. [22.63 MAX.] .015 [.18] TYP .102 MAX [2.59 MAX] END VIEW END VIEWDETAIL .502±.008 [12.75±.20] COPLANARITY: .004 [.10] from seating plane Inch [mm] 30A223-00 30A223-00 REV. E 2/03 .463 [11.76] TYP Lead Toe-to-Toe per device datasheet DPAC Technologies Products & Services for the Integration Age 7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772 www.dpactech.com Nasdaq: DPAC 2 ©2003 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, LP-StackTM, CS-StackTM are trademarks of DPAC Technologies Corp.