DP83924A 10BASE-T VCE100A DP83924AVCE D10-9 D15-14 - Datasheet Archive

 

DP83924A Quad 10 Mb/s Ethernet Transceiver General Description Features The Quad 10 Mb/s Ethernet Transceiver is a 4-Port

 

October 1997 DP83924A DP83924A Quad 10 Mb/s Ethernet Transceiver General Description Features The Quad 10 Mb/s Ethernet Transceiver is a 4-Port Encoder/Decoder (ENDEC) that includes all the circuitry required to interface four Ethernet Media Access Controllers (MACs) to 10BASE-T 10BASE-T. This device is ideally suited for switch hub applications where 8, 16, 24, or 32 ports are commonly used. s s s s 100 pin package 10BASE-T 10BASE-T and AUI interfaces 4 ports TP interface with TRI-STATE control Single Full AUI and TP Interface on port 1 supports 50 meter drops s Automatic or manual selection of twisted pair or AttachThe DP83924A DP83924A has three dedicated 10BASE-T 10BASE-T ports. ment Unit Interfaces on port 1 There is an additional port that is selectable for either 10BASE-T 10BASE-T or for an Attachment Unit Interface (AUI). In s Direct Interface to NRZ Compatible controllers 10BASE-T 10BASE-T mode, any port can be configured to be Half or s MII-Like Management Interface (Continued) Full Duplex. (Continued) System Diagram RTX REQ Reference TXU+ TXE Transmit Control Interface TXD TXC MDC MDIO Transmit Filter Oscillator Prescaler Output Driver TXUTX+ Transmit AUI Driver Management Control Interface TX- Link Generator Configuration Registers AUI Collision + TP LBK - CD+ CD- AUI Port 1 only X1 Transmit Pre-emphasis/TX Logic Manchester Encoder and Data Ctl. AUI LBK LED_CLK LED Control Interface Heartbeat Jabber Timer Common Analog/PLL for Wave Shapers Collision Decoder TP Rcv + - RXIRX+ - Smart Squelch RXI+ + MUX COL CRS RXD RXC Link Detector RX- AUI Rcv Receive Control Interface Phase Lock Loop Decoder MUX ENDEC-Transceiver Block (replicated 4 times) AUI Port 1 only LED_DATA TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 1997 National Semiconductor Corporation www.national.com DP83924A DP83924A Quad 10 Mb/s Ethernet Transceiver PRELIMINARY General Description (Continued) Features (Continued) The various modes on the transceivers can be configured s Serial management interface for configuration and monand controlled via the MII management interface. This itoring of ENDEC/Transceiver operation management interface makes inter-operability with other s Twisted Pair Transceiver Module manufacturers MAC units relatively easy. If no manage­ On-chip filters for transmit outputs ment interface is desired, some of the critical operating ­ Adjustable Equalization and Amplitude modes of the transceiver can be set via strapping options (latching configuration information during reset). The ­ Low Power Driver ENDEC section of the transceiver also supplies a simple ­ Heartbeat and Jabber Timers Non-Return-to-Zero (NRZ) interface to transmit and ­ Link Disable and Smart Receive Squelch receive data to/from standard 10 Mb/s MACs. ­ Polarity detection and correction The transceivers include on-chip filtered transmit outputs, ­ Jabber Enable/Disable which reduce emissions and eliminate the need for external filter modules. s ENDEC Module (one per port) ­ Low Power Class AB Attachment Unit Interface (AUI) Driver for one port ­ Enhanced Supply Rejection ­ Enhanced Jitter Performance ­ Diagnostic ENDEC Loopback ­ Squelch on Collision and Receive Pair s Serial LED interface for LINK, POLARITY, ACTIVITY, and ERROR s JTAG Boundary Scan per IEEE 1149.1 2 www.national.com Table of Contents 1.0 2.0 3.0 Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin Connection Diagram . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Management Interface . . . . . . . . . . . . . . . . . . . . . . 8 2.2 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . 10 Detailed Functional Description . . . . . . . . . . . . . . . . . 12 3.1 Twisted Pair Functional Description . . . . . . . . . . 12 3.2 ENDEC Module . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Additional Features . . . . . . . . . . . . . . . . . . . . . . . 13 4.0 5.0 6.0 7.0 3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Register Map and Descriptions . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . 5.1 Magnetics Specifications . . . . . . . . . . . . . . . . . . 5.2 Layout Considerations . . . . . . . . . . . . . . . . . . . . AC and DC Electrical Specifications . . . . . . . . . . . . . Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 17 17 17 18 30 www.national.com 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC TDI TMS TRST GND_DIG VDD_DIG LED_CLK LED_DATA LINK_1 LINK_2 GND_2 LINK_3 / INT LPBK / MDC LINK_4 / MDIO X1 GND_CLK VDD_CLK NC NC NC TX+ TXCD+ CDRX+ RXRXI1+ RXI1VDD_TPI_1 GND_TPI_1 TXU1+ TXU1TXU2+ TXU2VDD_TPI_2 GND_TPI_2 RXI2+ RXI2RXI3+ RXI3VDD_TPI_3 GND_TPI_3 TXU3+ TXU3TXU4+ TXU4VDD_TPI_4 GND_TPI_4 RXI4+ RXI4- 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC TCK TDO TXC RXC[1] COL[1] CRS[1] RXD[1] TXE[1] TXD[1] VDD_1 GND_WSPLL_1 VDD_WSPLL_1 VDD_PLL_2 GND_PLL_4 GND_PLL_3 GND_PLL_2 VDD_PLL_1 GND_PLL_1 RXC[2] COL[2] CRS[2] RXD[2] TXE[2] TXD[2] RXC[3] COL[3] GND_1 CRS[3] RXD[3] 1.0 Pin Information 1.1 Pin Connection Diagram DP83924A DP83924A Quad 10Mb/s Ethernet Transceiver 100-Pin PQFP (TOP VIEW) 4 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 NC NC NC TXE[3] TXD[3] RXC[4] COL[4] CRS[4] RXD[4] TXE[4] TXD[4] RESET FDX[4] FDX[3] FDX[2] FDX[1] RTX REQ GND_WS_1 VDD_WS_1 NS Package Number VCE100A VCE100A Order Number DP83924AVCE DP83924AVCE www.national.com 1.0 Pin Information (Continued) 1.2 Pin Description Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE: These pins provide the interface signalling between the Media Access Controller and the transceiver. (30 Pins) Symbol Pin # Type Description TXC 77 O Transmit Clock: This pin outputs a 10 MHz output clock signal synchronized to the transmit data (one pin for all ports). TXD[4] TXD[3] TXD[2] TXD[1] 40 46 56 71 I Transmit Data: The serial TXD contains the transmit serial data output stream. TXE[4] TXE[3] TXE[2] TXE[1] 41 47 57 72 I Transmit Enable: This active high input indicates the presence of valid data on the TXD pins. CRS[4] CRS[3] CRS{2] CRS[1] 43 52 59 74 O, pull-up O, pull-up O, pull-up O, pull-up Carrier Sense: Active high output indicates that valid data has been detected on the receive inputs. COL[4] COL[3] COL[2] COL[1] 44 54 60 75 O, pull-up O, pull-up O, pull-up O, pull-up CRS[3:1] are dual purpose pins. When RESET is active, the value on these pins are sampled to determine the transceiver address for the mgmt interface. These pins have internal pull-ups, a 2.7 k pull down resistor is required to program a logic `0'. Collision: This active high output is asserted when a collision condition has been detected. It is also asserted for 1µs at the end of a packet to indicate the SQE test function. COL[4:1] are dual purpose pins. When RESET is active, these pins are sampled and selects the operating mode for the device. To select the non-default mode(s), a 2.7 k pull down resistor(s) is required. The strappable functions are: COL[4]; selects the number of receive clocks after carrier sense deassertion (5 RXCs or continuous RXCs). Default is 5 RXCs. COL[3]; enables or disables the receive filter. Default is to disable the receive filter. COL[2]; selects the full duplex operating mode (normal or enhanced). Default is normal full duplex mode. COL[1]; selects the LED operating mode (normal or enhanced). Default is normal LED mode. RXC[4] RXC[3] RXC[2] RXC[1] 45 55 61 76 O Receive Clock: This 10 MHz signal is generated by the transceiver, and is the recovered clock from the decoded network data stream. The number of RXCs after the deassertion of CRS is programmable via the Global Configuration Register, GATERXC bit, D0. The options are for 5 RXCs or continuous RXCs. RXD[4] RXD[3] RXD[2] RXD[1] 42 51 58 73 O Receive Data: Provides the decoded receive serial data. Data is valid on the rising edge of RXC. MDC 93 I Management Data Clock: When "normal" full duplex mode is selected (strap option, COL[2]=1), this clock signal (0-2.5 MHz) is the clock for transferring data across the management interface. LPBK LoopBack: When "enhanced" full duplex mode is selected (strap option, COL[2]=0), then this pin is an active high input to configure all ports into diagnostic loopback mode. MDIO 94 I/O LINK_4 Management Data I/O: When "normal" full duplex mode is selected (strap option, COL[2]=1), this Bidirectional signal transfers data on the management interface between the controller and the transceiver. Link Lost Status Port 4: When "enhanced" full duplex mode is selected, (strap option, COL[2]=0), this pin outputs the link lost status for port 4. If link is lost, this output is high. INT 92 OD LINK_3 Interrupt: When "normal" full duplex mode is selected (strap option, COL[2]=1), this output pin is driven low when an interrupt condition is detected within the Quad Transceiver. An interrupt can occur when, link status changes or, LED status changes. This is an open-drain output. And requires an external pull-up resistor. Link Lost Status Port 3: When "enhanced" full duplex mode is selected, (strap option, COL[2]=0), this pin outputs the link lost status for port 3. If link is lost, this output is high. LINK_2 LINK_1 90 89 O Link Lost Status Ports 1,2: These pins indicate the link lost status for ports 1 and 2, when "enhanced" full duplex mode is selected. 5 www.national.com 1.0 Pin Information (Continued) Table 2. NETWORK INTERFACES: Attachment Unit, Twisted Pair Interface (24 Pins) Symbol Pins Type Description RXI4+ RXI4- 29 30 I Twisted Pair Receive Input: This differential input pair receives the incoming data from the twisted pair medium via an isolation transformer. RXI3+ RXI3- 19 20 RXI2+ RXI2- 17 18 RXI1+ RXI1- 7 8 TXU4+ TXU4- 25 26 O TXU3+ TXU3- 23 24 UTP Transmit Outputs: This pair of drivers provide pre-emphasized and filtered differential output for UTP (100 cable). These drivers maintain the same common mode voltage during data transmission and idle mode. TXU2+ TXU2- 13 14 TXU1+ TXU1- 11 12 REQ 33 I Equalization Resistor: An external resistor connects to ground to adjust the equalization on the twisted pair transmit outputs. RTX 34 I Transmit Amplitude Resistor: An external resistor connects to ground to adjust the amplitude of the differential transmit outputs to the unshielded twisted pair cable. Attachment Unit Interface RX+ RX- 5 6 I Port 1 Full AUI Receive Input: In AUI mode this differential input pair receives the incoming data from the AUI medium via an isolation transformer. TX+ TX- 1 2 O Port 1 Full AUI Transmit Output: In AUI mode this differential pair sends encoded data from the AUI transceiver. These outputs are source followers and require 270 Ohm pull down resistors. CD+ CD- 34 I Port 1 Full AUI Collision Detect: In AUI mode, this differential input pair receives the collision detect signals from the AUI medium via an isolation transformer. Table 3. LED & GENERAL CONFIGURATION Pins (8 Pins) Symbol Pins Type Description LED_DATA 88 O LED serial data output: This output should be connected to the input of the 1st serial shift register. LED_CLK 87 O LED Clock: This is the clock for the serial shift registers. X1 95 I External Oscillator Input: This signal is used to provide clocking signals for the internal ENDEC. A 20 MHz oscillator module should be used to drive this pin. RESET 39 I Reset: Active low input resets the transceiver, and starts the initialization of the device. This pin has a noise filter on it's input, which requires that the reset pulse must be greater than 30 TXC's. FDX[4:1] 38 -35 I Full Duplex: This pin is sampled during reset. They control the full duplex (or half duplex) configuration of each port. 6 www.national.com 1.0 Pin Information (Continued) Table 4. SCAN TEST Pins (5 Pins) Symbol Pins Type Description TCK 79 I Test Clock: This signal is used during boundary scan to clock data in and out of the device. TDI 82 I Test Input: The signal contains serial data that is shifted into the device by the TAP controller. An internal pullup is provided if not used. TDO 78 O,Z Test Output: The signal can be set to TRI-STATE and contains serial data that is shifted out of the device by the TAP controller. TMS 83 I Test Mode Select: This selects the operation mode of the TAP controller. An internal pullup is provided if not used. TRST 84 I Test Reset: When this signal is asserted low, it forces the TAP (Test Access Port) controller into a logic reset state. An internal pullup is provided. This pin should be pulled low during normal operation. Table 5. POWER AND GROUND Pins (33 Pins) Symbol Pins Type Table 6. Pin Type Description Description Pin Type NA No Connect NC NC NC NC NC NC NC NC 48 49 50 80 81 98 99 100 VDD_TPI_4 VDD_TPI_3 VDD_TPI_2 VDD_TPI_1 27 21 15 9 P Power for TPI Ports 1-4 GND_TPI_4 GND_TPI_3 GND_TPI_2 GND_TPI_1 28 22 16 10 G Ground for TPI Ports 1-4 VDD_PLL_2 VDD_PLL_1 67 63 P Power for PLL Circuitry GND_PLL_4 GND_PLL_3 GND_PLL_2 GND_PLL_1 66 65 64 62 G Ground for PLL Circuitry VDD_WSPLL_1 68 P Power for Wave Shaper and PLL Circuitry GND_WSPLL_1 69 G Ground for Wave Shaper and PLL Circuitry VDD_WS_1 31 P Power for Wave Shaper Circuitry GND_WS_1 32 G Ground for Wave Shaper Circuitry VDD_DIG 86 P Power for Core Logic GND_DIG 85 G Ground for Core Logic GND_CLK 96 G Ground for Clock Circuitry VDD_CLK 97 P Power for Clock Circuitry GND_2 GND_1 91 53 G Ground for NRZ Circuitry VDD_1 70 P Description Power for NRZ Circuitry I Output Buffer (driven at all times) I/O Bi-directional Buffer O, Z Output Buffer with High Impedance Capability OD 7 Input Buffer O Open Drain-Like Output. Either driven Low or to a High Impedance State www.national.com 2.0 Interface Descriptions Interface Overview During a read operation, the first 14 bits are driven onto MDIO by the host, then the bus is released, allowing the The Quad Transceiver's interfaces can be categorized into DP83924A DP83924A to drive the requested data onto MDIO. the following groups of signals: The serial lines do not require any preamble on these pins, 1. Management Interface - Allows host to read status and however if it is provided it is ignored so long as the 0110 or set operating modes. 0101 pattern is not present. If a continuous MDC is not 2. Media Access Control Interface - Straight forward NRZ supplied, then at the end of each command (read or write), interface to Ethernet MACs. 2 additional MDCs are required in order to allow the inter3. LED Interface - Serial LED interface to off chip shift reg- nal state machine to transition back to it's idle state. Refer to Figure 1. isters. 2.2 MAC Interface 4. Network Interfaces - Integrated 10BASE-T 10BASE-T and AUI. 5. Clock - Allows connection of an external clock module. This interface connects the ENDEC/Transceiver to an Ethernet MAC controller. This interface consists of a serial data transmit interface and a serial receive interface. The This interface is a simple serial interface that is modeled interface clocks data out (on receive) or in (on transmit) on after the MII standard serial interface, though it does not the rising edge of the clock. Refer to Figure 2. All signals adhere to the MII standard completely (the protocol is fol- are active high with rising edge sampling.The recovered lowed, but the register space is not). The interface signals clock (RXC) is selectable for 5 RXCs after the deassertion consist of a clock and data line for transfer of data to and of carrier sense (CRS) or for continuous RXCs after the from the registers. deassertion of CRS. This is programmable through the In a multiple Quad Transceiver system, it is necessary to serial MII or through the COL[4] strapping option. distinguish between the devices in order to access the cor- 2.3 LED Interface rect registers for configuration and status information. This is accomplished by assigning each Quad Transceiver a The LED interface consists of two modes. The first option, unique transceiver address. The lower 3 bits of the trans- normal LED mode, requires an external 8-bit shift register. ceiver address, T[2:0], is latched in during reset based on During every LED update cycle, 8-bits are shifted out to the the logic state of CRS[3:1]. The upper 2 bits of the trans- external shift registers. This allows two status LEDs per ceiver address, T[4:3], must be zero. Therefore, 32 ports port. One LED indicates activity (Tx or Rx) and the second indicates port status (per Table 6). The LEDs attached to can be supported with a single MII bus. the shift register will be on, if the associated port has tx or The register address field indicates which register within rx activity. The status LEDs will blink at different rates the DP83924A DP83924A that is to be accessed (read or write). depending on the associated ports status. During a write operation, all 32 bits are driven onto MDIO by the host, indicating which transceiver and register the data is to be written. 2.1 Management Interface 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 31 32 33 34 MDC MDIO 0 1 prefix 1 0 read T4 T3 T2 T1 T0 A4 A3 A2 A1 A0 transceiver address register address Z 0 D15 turn around D0 data Register Read MDIO 0 1 prefix 0 1 write T4 T3 T2 T1 T0 A4 A3 A2 A1 A0 transceiver address register address 1 0 turn around D15 D0 data Register Write Note 1: The management interface addressing includes a 5 bit field for the Transceiver Address, T[4:0], and a 5 bit field for the register address, A[4:0]. The MII assumes the transceiver address applies to a single port, but in this implementation a single address refers to a single IC. The transceiver address is set by 3 external pins, CRS[3:1]. T[4:3] must be zero to address the transceiver. Thus up to 32 10BASE-T 10BASE-T ports can be addressed from a single interface (8 addr x 4 ports/addr). Note 2: Two MDCs (clocks 33, 34) are required after each read or write in order to allow the internal state machine to transition back to it's IDLE state. Figure 1. Serial Management Interface Timing Diagram (read/write) 8 www.national.com 2.0 Interface Descriptions (Continued) 5 Clocks Transmit Interface SIgnals TXC Setup TXE Hold TXD COL Receive Interface SIgnals RXC Setup Hold CRS RXD Figure 2. NRZ Interface Timing Diagram LED_CLK LED_DATA act.1 act.2 act.3 act.4 stat.1 stat.2 stat.3 stat.4 Note: act.n - Transmit or Receive activity for Port n stat.n - Port n status Signal is active low (LED on) Figure 3. Normal LED Mode Timing Diagram used to support two LEDs. One is a bi-color LED (decode of the FDX and LinkCoded bits) to indicate LINK status. The second LED indicates activity (Tx or Rx). The Tx and Rx bits are not intended to be used as separate LEDs for transmit and receive activity. Refer to the User Information document regarding this mode. As with the first LED option, port 1 status is shifted out first. Refer to Figure 4. Table 8. Enhanced LED Mode - Bit Decode If a port experiences both Bad Polarity and Link Lost, then the LEDs will go to the fast blink state (i.e. Link Lost). Port activity and status are shifted out serially, with port 1 shifted out first. The LED update rate is every 50 ms. The LED clock rate is 1 MHz. All port activity is extended to 50 ms to make it visible. Data is valid on the rising edge of LED_CLK and is active low (LED on). Refer to Figure 3. Table 7. Normal LED Mode LED Condition Status Indication Off Slow Blink (1600 ms) 0 OFF Link Fail, Full Duplex 1 ON Good Link, Full Duplex 1 0 ON Good Link, Half Duplex 1 Bad Polarity Comments 0 Link Lost LED Status 1 OFF Link Fail, Half Duplex Error'd Status Fast Blink (400 ms) LinkCoded 0 Good Status On - Solid FDX The second option, enhanced LED mode, serially shifts a 16-bit stream out of the Quad Transceiver. This option outputs per port data for Rx, Tx, Full Duplex (FDX), and LinkCoded status. These four bits per port are intended to be 9 www.national.com 2.0 Interface Descriptions (Continued) LED_CLK LED_DATA FDX Link FDX Link FDX Link FDX Link Tx.1 Tx.2 Tx.3 Tx.4 Rx.1 Rx2 Rx.3 Rx.4 coded Port.1 coded Port.2 coded Port.3 coded Port.4 Figure 4. Enhanced Mode LED Timing Diagram To select the desired LED mode, the COL [1] pin has a strapping feature. If COL[1] is a logic `0' during reset, then "enhanced" LED mode is enabled. If COL[1] is a logic `1' during reset, then "normal" LED mode is enabled. 2.4 Network Interface 2.4.1 Twisted Pair Interface The Quad 10 Mb/s Transceiver provides two buffered and filtered 10BASE-T 10BASE-T transmit outputs (for each port) that are connected to the output isolation transformer via two impedance matching resistor/capacitor networks. See Figure 5. The twisted pair receiver implements an intelligent receive squelch on the RXI+ differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. This smart squelch circuitry (which is described in detail under the Functional Description) employs a combination of amplitude and timing measurements to determine the validity of data on the twisted pair inputs. Only after these conditions have been satisfied will Carrier Sense (CRS) be generated to indicate that valid data is present. 2.4.2 Attachment Unit Interface A single port (port 1) on the transceiver has a separate (non- multiplexed) AUI interface. This interface is a full 802.3 standard AUI interface capable of driving the full 50m cable. The schematic for connecting this interface to the AUI connector is shown in Figure 6. 1000 pF 1:2 10 TX+ 1000 pF TXRXI+ RXI- 200pF TD+ TDRD+ RD- 10 RJ45 T1 REQ RTX R5 49.9 R3 +5V R4 1:1 Common Mode R6 49.9 Chokes may be required. C1 0.01µF All values are typical and are + 1% Figure 5. Twisted Pair Interface Schematic Diagram 10 www.national.com 2.0 Interface Descriptions (Continued) +12V 1:1 CD+ CDRX+ RXTX+ TXT2 R1 39.2 R2 39.2 R3 39.2 R4 39.2 C1 0.01µF AUI +12V CD+ CDRX+ RXTX+ TXGND DB15 C2 0.01µF Figure 6. Full AUI Interface Schematic If the standard 78 transceiver cable is used, the receive differential input must be externally terminated with two 39 resistors connected in series. In thin Ethernet applications, these resistors are optional. To prevent noise from falsely triggering the decoder, a squelch circuit at the input rejects signals with levels less than -175 mV. Signals more negative than -300 mV are decoded. 2.4.3 Oscillator Clock When using an oscillator, additional output drive may be necessary if the oscillator must also drive other components. The X1 pin is a simple TTL compatible input. See Figure 7. To Internal Circuit Oscillator 20 MHz, 0.01% 40-60% Duty Cycle Drive 2 TTL Loads X1 VCC Oscillator Figure 7. External Oscillator Connection Diagram 11 www.national.com 3.0 Detailed Functional Description This product utilizes the standard 10BASE-T 10BASE-T and AUI interface core building blocks which are replicated on this device, one per port. The basic function of these blocks are described in the following sections. Also described are the common digital blocks. Refer to the "System Diagram" on page 1. 3.1 Twisted Pair Functional Description 3.1.1 Smart Squelch The Smart Squelch is responsible for determining when valid data is present on the differential receive inputs (RXI±). The Twisted Pair Transceiver (TPT) implements an intelligent receive squelch on the RXI± differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. due to noise on the network. The COL signal remains for the duration of the collision. Approximately 1sec after the transmission of each packet a signal called the Signal Quality Error (SQE) consisting of typically 10 cycles of a 10 MHz signal is generated by the transceiver. This 10 MHz signal, also called the Heartbeat, assures the continued functioning of the collision circuitry. The SQE signal is passed on to the MAC via the COL signal and is represented as a pulse. 3.1.3 Link Detector/Generator The link generator is a timer circuit that generates a link pulse as defined by the 10BASE-T 10BASE-T specification that will be sent by the transmitter section. The pulse which is 100ns wide is transmitted on the transmit output, every 16ms, in the absence of transmit data. The pulse is used to check The squelch circuitry employs a combination of amplitude the integrity of the connection to the remote MAU. and timing measurements to determine the validity of data on the twisted pair inputs. The operation of the smart The link detection circuit checks for valid pulses from the remote MAU and if valid link pulses are not received the squelch is shown in Figure 8. link detector will disable the twisted pair transmitter, receiver and collision detection functions. >200ns