DP725 MD-2001 MIL-STD-883 99VREF 01VREF 98VREF 990VREF 502VREF 498VREF 014VREF - Datasheet Archive

 

Quad Digital Potentiometer (DP) with 256 Taps and Microwire Interface DESCRIPTION FEATURES Four 8-bit DPs configured as

 

DP725 DP725 Quad Digital Potentiometer (DP) with 256 Taps and Microwire Interface DESCRIPTION FEATURES Four 8-bit DPs configured as programmable voltage sources in DAC-like applications Independent reference inputs Buffered wiper outputs Non-volatile NVRAM memory wiper storage Output voltage range includes both supply rails 4 independently addressable buffered output wipers 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs The DP725 DP725 is a quad 8-bit digital potentiometer (DP) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. The DP725 DP725 offers four independently programmable DPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DP's output. For Ordering Information details, see page 15. APPLICATIONS Automated product calibration Remote control adjustment of equipment Offset, gain and zero adjustments in selfcalibrating and adaptive control systems Tamper-proof calibrations DAC (with memory) substitute Control of the DP725 DP725 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin allows several DP725 DP725's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the ¯¯¯¯ DP725 DP725's Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM Memory Erase/ Write cycle. PIN CONFIGURATION The DP725 DP725 is available in the 0°C to 70°C com­ mercial and -40°C to 85°C industrial operating temperature ranges and offered in 20-pin plastic surface mount packages. SOIC 20-Lead (W) VREFH2 1 20 VREFH3 VREFH1 2 19 VREFH4 VDD 3 18 VOUT1 CLK 4 17 VOUT2 RDY/¯¯¯¯ BSY 5 16 VOUT3 CS 6 15 VOUT4 DI 7 14 VREFL4 DO 8 13 VREFL3 PROG 9 12 VREFL2 GND 10 11 VREFL1 DP725 DP725 © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice 1 Doc. No. MD-2001 MD-2001 Rev. H DP725 DP725 FUNCTIONAL DIAGRAM VREFH1 VREFH3 VREFH2 VREFH4 2 RDY/BSY 1 20 19 5 CLK CS DI 9 4 6 7 PROGRAM CONTROL DATA CONTROLLER PROG WIPER CONTROL REGISTERS AND NVRAM + + VOUT1 17 VOUT2 ­ + 16 ­ + 24k (ea) H.V. CHARGE PUMP 18 ­ SERIAL DATA OUTPUT REGISTER 15 12 13 VOUT4 ­ 8 11 VOUT3 DO 14 VREFL2 VREFL4 VREFL1 Doc. No. MD-2001 MD-2001 Rev. H VREFL3 2 © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice DP725 DP725 ABSOLUTE MAXIMUM RATINGS Parameters Ratings Supply Voltage* VDD to GND Inputs CLK to GND CS to GND DI to GND ¯¯¯¯ RDY/BSY to GND PROG to GND VREFH to GND VREFL to GND Units -0.5 to +7 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 V V V V V V V V Parameters Ratings -0.5 to VDD +0.5 Operating Ambient Temperature Commercial (`C' or Blank suffix) Industrial (`I' suffix) Junction Temperature Storage Temperature Lead Soldering (10 sec max) V -0.5 to VDD +0.5 Outputs D0 to GND VOUT 1­ 4 to GND Units V 0 to +70 °C -40 to +85 +150 -65 to +150 +300 °C °C °C °C RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min VZAP(2) ILTH(2)(3) Max Units ESD Susceptibility MIL-STD-883 MIL-STD-883, Test Method 3015 2000 V Latch-Up JEDEC Standard 17 100 mA POWER SUPPLY Symbol Parameter Conditions Min Typ Max Units IDD1 Supply Current (Read) Normal Operating - 400 600 µA IDD2 Supply Current (Write) Programming, VDD = 5V - 1600 2500 µA VDD = 3V - 1000 1600 µA VDD Operating Voltage Range 2 .7 - 5.5 V Min Typ Max Units LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD - - 10 µA IIL Input Leakage Current VIN = 0V - - -10 µA VIH High Level Input Voltage 2 - VDD V VIL Low Level Input Voltage 0 - 0.8 V LOGIC OUTPUTS Symbol Parameter Conditions Min Typ Max Units VOH High Level Output Voltage IOH = -40µA VDD -0.3 - - V VOL Low Level Output Voltage IOL = 1 mA, VDD = +5V - - 0.4 V IOL = 0.4 mA, VDD = +3V - - 0.4 V Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from ­1V to V CC + 1V. © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice 3 Doc. No. MD-2001 MD-2001 Rev. H DP725 DP725 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Conditions Min Potentiometer Resistance Typ Max 24 RPOT to RPOT Match - Units k ±0.5 ±1 ±20 Pot Resistance Tolerance % % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin 0 VDD - 2.7 V Resolution 0 .4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 IOUT Buffer Output Current 3 TCRPOT TC of Pot Resistance 300 ppm/ºC CH/CL Potentiometer Capacitances 8/8 pF mA AC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Minimum CS Low Time 150 - - ns tCSS CS Setup Time 10 0 - - ns tCSH CS Hold Time 0 - - ns tDIS DI Setup Time 50 - - ns 50 - - ns Digital tCSMIN CL = 100pF (1) tDIH DI Hold Time tDO1 Output Delay to 1 - - 150 ns tDO0 Output Delay to 0 - - 150 ns tHZ Output Delay to High-Z - 400 - ns tLZ Output Delay to Low-Z - 400 - ns tBUSY Erase/Write Cycle Time - 4 5 ms P ROG Setup Ti me 150 - - ns tPROG Minimum Pulse Width 700 - - ns tCLKH Minimum CLK High Time 500 - - ns tCLKL Minimum CLK Low Time 300 - - ns Clock Frequency DC - 1 MHz C LOAD = 10 pF, VDD = +5V - 3 10 µs CLOAD = 10 pF, VDD = +3V - 6 10 µs tPS fC Analog tDS DP Settling Time to 1 LSB Notes: (1) All timing measurements are defined at the point of signal crossing V DD / 2. (2) These parameters are periodically sampled and are not 100% tested. Doc. No. MD-2001 MD-2001 Rev. H 4 © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice 5 RDY/BSY PROG DO DI CS CLK to to t LZ t DIS t CSS 1 1 t DO1 t DIH 2 2 t PS t CLK H 3 t PROG t CLK L 3 t DO0 4 t BUSY t CSH 4 t HZ t CSMIN 5 5 FROM TIMING TO Min Min MIN/MAX Min Min Rising CLK edge to end of datavalid t LZ Rising PROG edge to next falling CLK edge Falling CS edge to D0 becoming high impedance (T ri-State) t BUSY Falling CLK edge after PR OG=H to rising RD Y/BSY edge t PROG Rising PROG edge to falling PROG edge t PS t HZ Rising CLK edge to D0 = high Rising CS edge to D0 becoming high low impedance (activ output) e t DO0 t DO1 Rising CLK edge to D0 = lo w t DIH Max Min Min (Max) Max (Max) Max Min t DIS Data valid to first rising CLK edge after CS = high Min t CSMIN Falling CS edge torising CS edge t CSS Rising CS edge to ne rising CLK edge xt Falling CLK edge f r last data bit (DI) o to falling CS edge t CSH Min t CLK L Falling CLK edge to CLKrising edge t CLK H Rising CLK edge tofalling CLK edge PARAM NAME DP725 DP725 A.C. TIMING DIAGRAM Doc. No. MD-2001 MD-2001 Rev. H DP725 DP725 PIN DESCRIPTION Pin Name Function 1 2 3 4 5 6 7 8 VREFH2 VREFH1 VDD CLK ¯¯¯¯ RDY/BSY CS DI DO 9 PROG 10 GND Power supply ground 11 12 13 14 15 16 17 18 19 20 VREFL1 VREFL2 VREFL3 VREFL4 VOUT4 VOUT3 VOUT2 VOUT1 VREFH4 VREFH3 Minimum DP 1 output voltage Minimum DP 2 output voltage Minimum DP 3 output voltage Minimum DP 4 output voltage DP 4 output DP 3 output DP 2 output DP 1 output Maximum DP 4 output voltage Maximum DP 3 output voltage CDP/DP addressing is as follows: Maximum DP 2 output voltage Maximum DP 1 output voltage Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin DP OUTPUT A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 Non-volatile Memory Programming Enable Input When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. DEVICE OPERATION The DP725 DP725 is a quad 8-bit configured digital potentiometer (DP/CDP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPs return to the settings stored in non-volatile memory. Each confitured DP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the DP725 DP725's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DP wiper control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. DIGITAL INTERFACE The DP725 DP725 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DP address and data are clocked into the DI pin on the clock's rising edge. Doc. No. MD-2001 MD-2001 Rev. H A0 Because CS functions like a reset the CS pin has been desensitized with a 30ns to 90ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. 6 © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice DP725 DP725 ¯¯¯¯¯ READY/BUSY When saving data to non-volatile memory, the ¯¯¯¯ Ready/Busy ouput (RDY/BSY ) signals the start and duration of the erase/write cycle. Upon receiving a ¯¯¯¯ command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the DP725 DP725 will ignore any data appearing at DI and no data will be output on DO. CLOCK The DP725 DP725's clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DP wiper control register. ¯¯¯¯ RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, ¯¯¯¯ RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. No clock is necessary upon system power-up. The DP725 DP725's internal power-on reset circuitry loads data from non-volatile memory to the DPs without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. DATA OUTPUT Data is output serially by the DP725 DP725, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 725s to share a single serial data line and simplifies interfacing multiple 725s to a microprocessor. VREF VREF, the voltage applied between pins VREFH & VREFL, sets the configured DP's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH & VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. WRITING TO MEMORY Programming the DP725 DP725's non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DP address and eight data bits are clocked into the DP wiper control register via the DI pin. Data enters on the clock's rising edge. The DP output changes to its new setting on the clock cycle following D7, the last data bit. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the falling edge of the clock cycle immediately Figure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 10 11 12 N N +1 N+2 CS NEW DP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DP DATA DO D0 D1 D2 D3 D4 D5 PROG RDY/BSY © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice CURRENT DP VALUE NEW DP VALUE NEW DP VALUE NON-VOL ATILE DP OUTPUT VOLATILE NON-VOL ATILE 7 Doc. No. MD-2001 MD-2001 Rev. H DP725 DP725 following the D7 bit. Two clock cycles after the D7 bit the DP control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The DP725 DP725's nonvolatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. control register been different from that stored in nonvolatile memory then a change would occur at the read cycle's conclusion. TEMPORARILY CHANGE OUTPUT The DP725 DP725 allows temporary changes in DP's output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. READING DATA Each time data is transferred into a DP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DP's output. This feature allows µPs to poll DPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low th before the 13 clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DP wiper control register. Since this value is the same as that which had been there previously no change in the DP's output is noticed. Had the value held in the Figure 3 shows the control and data signals needed to effect a temporary output change. DP settings may be changed as many times as required and can be made to any of the four DPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPs will return to the output values stored in non-volatile memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DP control register prior to programming. This is because the DP725 DP725's internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. Figure 3. Temporary Change in Output Figure 2. Reading from Memory to to 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 12 N N +1 N+2 12 CS CS NEW DP DATA DI 1 A0 DI A1 1 A0 A1 D0 D1 D0 D1 D2 D3 D4 D5 D3 D4 D5 D6 D7 D6 D7 CURRENT DP DATA CURRENT DP DATA DO D2 D6 DO D7 D0 D1 D2 D3 D4 D5 PROG PROG RDY/BSY RDY/BSY DP OUTPUT DP OUTPUT Doc. No. MD-2001 MD-2001 Rev. H 8 CURRENT DP VALUE NEW DP VALUE CURRENT DP VALUE NON-VOL ATILE CURRENT DP VALUE NON-VOL ATILE VOLATILE NON-VOL ATILE © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice DP725 DP725 APPLICATION CIRCUITS +5V VI RI DP INPUT RF VDP GND VOUT 1111 1111 1000 0000 VDP ( RI + R F ) - VI R F 0111 1111 RI 0000 0001 0000 0000 + DP725 DP725 OP 07 -15V VREFL VOUT = LSB For R I = RF VOUT = 2VDP - V I VFS = 0.99VREF 99VREF VREF = 5V VZERO = 0.01VREF 01VREF MSB ­ CONTROL & DATA VREFH ANALOG OUTPUT CODE VDP = V - VZERO + VZERO 255 FS +15V VDD DP OUTPUT RI = RF 255 × 0.98VREF 98VREF + 0.01VREF 01VREF = 0.990VREF 990VREF 255 128 × 0.98VREF 98VREF + 0.01VREF 01VREF = 0.502VREF 502VREF 255 127 × 0.98VREF 98VREF + 0.01VREF 01VREF = 0.498VREF 498VREF 255 1 × 0.98VREF 98VREF + 0.01VREF 01VREF = 0.014VREF 014VREF 255 0 × 0.98VREF 98VREF + 0.01VREF 01VREF = 0.010VREF 010VREF 255 VOUT = +4.90V VOUT = +0.02V VOUT = -0 .02V VOUT = -4.86V VOUT = -4.90V Bipolar DP Output +5V RI RF +15V VDP DP725 DP725 GND + CONTROL & DATA VREFH ­ VDD VOUT OP 07 -15V VREFL R VOUT = (1 + F ) VDP RI Amplified DP Output +5V VDD +5V VREF VDD VREFH FINE ADJUST DP 127RC 127RC +VREF VREFH 127RC 127RC FINE ADJUST DP RC = +V COARSE ADJUST DP GND RC VOFFSET VREFL RC COARSE ADJUST DP + ­ GND VREFL R0 = (+VREF) - (VOFFSET+) 1µA (-VREF) + (VOFFSET+) 1µA +V R0 + RC = -VREF VREF VOFFSET ­ 256 x 1µA -V Fine adjust gives ±1 LSB change in VOFFSET when VOFFSET = VREF/2 Coarse-Fine Offset Control by Averaging DP Outputs for Single Power Supply Systems © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice Coarse-Fine Offset Control by Averaging DP Outputs for Dual Power Supply Systems 9 Doc. No. MD-2001 MD-2001 Rev. H DP725 DP725 V+ I > 2mA VREF = 5.000V VDD CONTROL & DATA VREFH DP725 DP725 GND LT 1029 VREFL Digitally Trimmed Voltage Reference 28 ÷ 32V 15k 10µF 10k 1N5231B 1N5231B VDD CONTROL & DATA VREFH 5.1V DP725 DP725 + MPT3055EL MPT3055EL GND ­ VREFL LM 324 OUTPUT 1.00k 4.02k 10µF 35V 0 ÷ 25V @ 1A Digitally Controlled Voltage Reference Doc. No. MD-2001 MD-2001 Rev. H 10 © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice DP725 DP725 +5V VREF VIN 1.0µF LM339 LM339 + VDD VREFH ­ 10k +5V DP725 DP725 VPP CS WINDOW 1 + ­ DP1 +5V + VIN 1.0µF ­ DI VREF LM339 LM339 10k +5V + WINDOW 2 + VREFH VDD DO DP725 DP725 VPP PROG ­ WINDOW 3 DP1 ­ DP2 + CS + DI ­ DP3 ­ + 10k +5V ­ WINDOW 4 WINDOW 2 + DO 10k +5V DP3 ­ DP4 + PROG + ­ CLK + DP4 ­ ­ GND WINDOW 1 10k +5V CLK 10k + + DP2 ­ +5V ­ +5V VREFL GND 10k VREFL WINDOW 5 10k +5V WINDOW 3 + + ­ ­ VREF WINDOW 1 VOUT1 WINDOW 2 VREFH VOUT2 WINDOW 1 VOUT2 WINDOW 3 VOUT1 WINDOW 2 VOUT3 WINDOW 4 VOUT4 VOUT4 VOUT3 WINDOW 3 WINDOW 5 GND GND WINDOW STRUCTURE WINDOW STRUCTURE Staircase Window Comparator © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice Overlapping Window Comparator 11 Doc. No. MD-2001 MD-2001 Rev. H DP725 DP725 +5V 2.2k VDD VREFH 4.7µF LM385-2 LM385-2.5 ISINK = 2 ÷ 255mA +15V + DP1 1mA steps 2N7000 2N7000 ­ +5V 10k DP725 DP725 39 10k 1W + DP2 5µA steps 2N7000 2N7000 ­ GND 1W 39 CONTROL & DATA VREFL 5M 5M 3.9k 10k 10k ­ TIP30 TIP30 + -15V Current Sink with 4 Decades of Resolution +15V 51k + TIP29 TIP29 ­ 10k 10k +5V VDD VREFH 5M 5M 39 1W 39 1W DP1 ­ BS170P BS170P DP725 DP725 + CONTROL & DATA 5M 5M 1mA steps 3.9k DP2 ­ GND VREFL BS170P BS170P 5µA steps + LM385-2 LM385-2.5 -15V ISOURCE = 2 ÷ 255mA Current Source with 4 Decades of Resolution Doc. No. MD-2001 MD-2001 Rev. H 12 © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice DP725 DP725 PACKAGE OUTLINE DRAWING SOIC 20-Lead 300mils (W) (1)(2) SYMBOL MIN NOM MAX 2.49 2.64 A 2.36 A1 0.10 A2 2.05 b 0.31 0.30 2.55 0.41 0.51 c 0.27 0.33 12.60 12.80 13.00 E E 0.20 D 10.01 10.30 10.64 E1 E1 7.40 7.50 7.60 e 1.27 BSC h L b 0.25 0.40 e 0.75 0.81 1.27 0° PIN#1 IDENTIFICATION 8° 5° 1 15° TOP VIEW D h h 1 A2 A 1 L A1 SIDE VIEW c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013 MS-013. © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice 13 Doc. No. MD-2001 MD-2001 Rev. H DP725 DP725 EXAMPLE OF ORDERING INFORMATION (1) Prefix Device # Suffix DP 725 W Package Optional Company ID W: SOIC I Temperature Range I = Industrial (-40ºC to 85ºC) ­ T1 Tape & Reel T: Tape & Reel 1: 1000/Reel Product Number 725 ORDERING PART NUMBER DP725WI DP725WI Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) This device used in the above example is a DP725WI-T1 DP725WI-T1 (SOIC, Industrial Temperature, Tape & Reel, 1000). Doc. No. MD-2001 MD-2001 Rev. H 14 © NIDEC COPAL ELECTRONICS CORP. Characteristics subject to change without notice REVISION HISTORY Date 03/16/2004 Rev. D Reason Updated Potentiometer Characteristics 07/12/2004 E Updated Functional Diagram Updated Potentiometer Characteristics 07/27/2007 F 10/31/2007 G 12/06/07 H Added Package Outline Drawings Added MD- to document number Updated Package Outline Drawings Update document title Update Logic Output table Update A.C. Timing Diagram Update Writing to Memory NIDEC COPAL ELECTRONICS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. NIDEC COPAL ELECTRONICS CORP. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NIDEC COPAL ELECTRONICS CORP. product could create a situation where personal injury or death may occur. NIDEC COPAL ELECTRONICS CORP. reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. NIDEC COPAL ELECTRONICS CORP. advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. NIDEC COPAL ELECTRONICS CORP. Japan Head Office Nishi-Shinjuku, Kimuraya Bldg., 7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023 Phone: +81-3-3364-7055 Fax: +81-3-3364-7098 www.nidec-copal-electronics.com Document No: MD-2001 MD-2001 Revision: H Issue date: 1 2 / 0 6 /0 7