NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: , LVDS_SSC and DOT_96 output buffers with integrated series terminations 3 - LP differential CPU clock , 35 34 33 32 31 30 29 28 27 26 25 SDA VDD1.5_CORE VDD1.5_IO DOT_96# DOT_96 VSS VSS , 16 DOT_96# O, LP-DIF 0.8V Differential 96.000MHz Clock output. 17 DOT_96 O , Logic PLL2 Frequency Divider DOT_96 PLL3 Frequency Divider LVDS_SSC TEST_MODE , CPU, SRC, DOT_96, LVDS_SS Z = 55 ohms PLL Core CPU#, SRC#, DOT_96#, LVDS_SS# Z = 55 ohms ... | Original |
21 pages, |
SLG8UM610 SLG8 MO-220 CK610 DOT96 SLG8UM610 abstract |
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| Abstract: USB48/FSA USB48/FSA 1 2 4 5 +70 2000 1 3 4 4 1 4 4 3 CPU0# DOT96# 1 5 4 , differential clock output 15 DOT96# OUT 16 FSB IN 17 SRC0 OUT Differential serial , PCIF/PCI USB DOT96 DOT96# REF 1 Normal Normal Normal Normal 33MHz , CPU_STOP# CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF 1 Normal , DOT96 DOT96# REF 48MHz Normal Normal 14.318MHz Low IREF * 2 or float Float ... | Original |
19 pages, |
PCI 6509 DOT96 CK410M 48MHZ pin diagram of intel p4 processor IDTCV111I IDTCV111I abstract |
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| Abstract: (Hi-Z) RW 1 = Enabled DOT_96 & DOT96# 14, 15 NA 7 Reserved RW Type Power , PCI_STOP# CPU_STOP# USB_48 / FS_A REF SMBus Logic PCIF_0 / ITP_EN USB_48 / FS_A DOT_96 DOT , VDD_PCI PCIF_0 / ITP_EN PCIF_1 VTT_PWRGD# / PWRDWN VDD_48 USB_48/FS 48/FS_A VSS_48 DOT_96 DOT_96# FS_B , Ground for Outputs 3.3V Power Supply for PLL Ground for PLL DOT_96 & DOT_96# PCI_STOP# Input , REF DOT_96 USB_48 Note 1 0 1 100MHz 100MHz 33MHz 14.318MHz 96MHz ... | Original |
21 pages, |
PI6C410MAE PI6C410MA PI6C410M osc 48mhz DOT96 240mil CRYSTAL 14.318MHZ PI6C410M abstract |
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| Abstract: , 0 = Disabled (Hi-Z) RW 1 = Enabled DOT_96 & DOT96# 14, 15 NA 7 PCIF_0 Output , / ITP_EN USB_48 / FS_A DOT_96 DOT 96# PLL 2 Div CPU[0:1] CPU[0:1]# 1 VDD_PCI VSS_PCI , VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE SRC_0 SRC_0# SRC_1 SRC_1# VDD_SRC SRC_2 SRC_2# SRC_3 , PCIF_1 PCI[2:5] USB_48 / FS_A DOT_96 & DOT_96# Input / Output Output Output Input / Output , Frequency Selection(1) FS_C FS_B FS_A CPU SRC PCIF / PCI REF DOT_96 USB_48 1 ... | Original |
21 pages, |
PI6C410MAE PI6C410MAAE PI6C410MA PI6C410M DOT96 240mil PI6C410MAAEX PI6C410M/410MA PI6C410M/410MA abstract |
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| Abstract: DOT96# 14, 15 NA 7 PCIF_0 Output Enable 1 = Enabled, 0 = Disabled RW 1 = Enabled , Block Diagram XTAL_IN XTAL_OUT SDA SCL XTAL OSC DOT_96 DOT 96# PLL 2 /2 USB_48 / FS_A , VDD_48 USB_48/FS 48/FS_A VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE SRC_0 SRC_0# SRC_1 SRC_1# VDD_SRC , PCIF_0 / ITP_EN PCIF_1 PCI[2:5] USB_48 / FS_A DOT_96 & DOT_96# Input / Output Output Output , Functionality Frequency Selection(1) FS_C FS_B FS_A CPU SRC PCIF / PCI REF DOT_96 ... | Original |
21 pages, |
PI6C410MAAEX PI6C410M DOT96 240mil PI6C410M/410MA PI6C410M/410MA abstract |
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| Abstract: VDD_48 11 46 SCL USB_48 12 45 VSS_CPU PCIF_1 VSS_48 13 DOT_96 14 SLG84410IE SLG84410IE 48 PCIF_2 44 CPU_0 43 CPU_0# 42 VDD_CPU 41 CPU_1 DOT_96# 15 , USB clock output. 13 VSS_48 GND Ground for outputs. 14 DOT_96 O, DIF 96 MHz DOT clock output. 15 DOT_96# O, DIF 96 MHz DOT clock output. 16 FS_B/TEST_MODE I , Frequency Divider PLL1 DOT_96 Frequency Divider USB_48 SCL, SDA PD PLL3 VTT_PWRGD# ... | Original |
18 pages, |
CK410 SLG84410IE SLG84410IE abstract |
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| Abstract: VDD_48 11 46 SCL USB_48 12 45 VSS_CPU PCIF_1 VSS_48 13 DOT_96 14 SLG84410B SLG84410B 48 PCIF_2 44 CPU_0 43 CPU_0# 42 VDD_CPU 41 CPU_1 DOT_96# 15 , USB clock output. 13 VSS_48 GND Ground for outputs. 14 DOT_96 O, DIF 96 MHz DOT clock output. 15 DOT_96# O, DIF 96 MHz DOT clock output. 16 FS_B/TEST_MODE I , Divider PLL1 DOT_96 Frequency Divider USB_48 SCL, SDA PD PLL3 VTT_PWRGD# FS_A:C ... | Original |
19 pages, |
SLG84410B CK410 SLG84410BE SLG84410B abstract |
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| Abstract: 4 4 3 CPU0# DOT96# 1 5 4 2 1 6 4 1 1 7 4 0 1 8 3 9 +70 , DOT96 OUT 96MHz 0.7 current mode differential clock output 15 DOT96# OUT 96MHz 0.7 , SRC# PCIF/PCI USB DOT96 DOT96# REF 1 Normal Normal Normal Normal 33MHz , CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF 0 Normal Normal , , SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy ... | Original |
16 pages, |
IDTCV110L DOT96 48MHZ IDTCV110L abstract |
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| Abstract: DOT96 1 4 4 3 CPU0# DOT96# 1 5 4 2 1 6 4 1 1 7 4 0 1 8 3 9 , GND 14 DOT96 OUT 96MHz 0.7 current mode differential clock output 15 DOT96# OUT , SRC# PCIF/PCI USB DOT96 DOT96# REF 1 Normal Normal Normal Normal 33MHz , CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF 0 Normal Normal , chip has three PLLs inside for CPU/SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for ... | Original |
16 pages, |
IDTCV110N DOT96 CK410 48MHZ IDTCV110N abstract |
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| Abstract: 4 4 3 CPU0# DOT96# 1 5 4 2 1 6 4 1 1 7 4 0 1 8 3 9 +70 , GND 14 DOT96 OUT 96MHz 0.7 current mode differential clock output 15 DOT96# OUT , DOT96# REF 1 Normal Normal Normal Normal 33MHz 48MHz Normal Normal , PCIF/PCI USB DOT96 DOT96# REF 0 Normal Normal Normal Normal 33MHz , PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock ... | Original |
16 pages, |
IDTCV110L 48MHZ DOT96 IDTCV110L abstract |
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| Abstract: PLL 1 SDA DOT_96 DOT 96# PLL 2 SRC [1:6] SRC [1:6]# CPU2_ITP / SRC7 CPU2_ITP# / SRC7# , VDD_PCI PCIF_0 / ITP_EN PCIF_1 PCIF_2 VDD_48 USB_48 VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE , ] Output 9, 10 PCI[0:5] Output 3, 4, 5, 54, 55, 56 USB_48 Output 12 DOT_96 & DOT_96# Output 14, 15 FS_A Input 18 3.3V LVTTL inputs for CPU frequency selection , SRC PCIF / PCI REF DOT_96 USB_48 Note 1 0 1 100MHz 100MHz 33MHz ... | Original |
16 pages, |
PI6C410VE PI6C410V PI6C410A PI6C410 DOT96 CRYSTAL 14.318MHZ PI6C410 abstract |
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| Abstract: DOT_96 14 SLG84410B SLG84410B 48 PCIF_2 44 CPU_0 43 CPU_0# 42 VDD_CPU 41 CPU_1 DOT_96# 15 FS_B/TEST_MODE 16 VTT_PWRGD#/PD 17 40 CPU_1# FS_A 18 39 IREF , outputs. 14 DOT_96 O, DIF 96 MHz DOT clock output. 15 DOT_96# O, DIF 96 MHz DOT , Frequency Divider SRC_1:7 Frequency Divider PLL1 DOT_96 Frequency Divider USB_48 SCL , DOT_96 USB_48 1 REF REF REF REF REF REF 0 Hi-Z Hi-Z Hi-Z Hi-Z ... | Original |
19 pages, |
SLG84410BF SLG84410BE CK410 49100 SLG84410B SLG84410B abstract |
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| Abstract: clock outputs @ 0.8V · 1 - differential DOT96 clock output @ 0.8V · SRC clocks compliant to , VSS_DOT DOT_96 DOT_96# VDD_27 27MHz 27MHz_SS VSS_27 32-pin QFN 0.50mm pitch 5x5mm *contains , VSS_DOT GND 3 DOT_96 O, DIF 0.8V 96 MHz DOT clock output 4 DOT_96# O, DIF , CKPWRGD Serial Interface & Control Logic PLL2 27M PLL4 DOT_96 Figure 1. Simple Block , Enable 0 = Disabled 1 = Enabled 1 4 RW DOT_96 Output Enable 0 = Disabled 1 = Enabled 1 ... | Original |
20 pages, |
2N3904 BSS138 CK410 ck505 DOT96 SILEGO SLG8LV595 B13b7 SLG8LV595VTR slg8lv595v intel ck505 clock specification CK505 SLG8LV595 abstract |
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| Abstract: differential DOT96/SRC clock output @ 0.7V · Scalable Low Voltage VDD I/O (3.3V to 1.05V) to reduce , Spread Spectrum % 11 54 CPU_0 VDD_I/O 12 53 CPU_0# SRC_0/DOT_96 13 52 VSS_CPU 51 CPU_1_MCH 0 0 0 0 Reserved SRC_0#/DOT_96# 14 0 0 0 1 , /CLKREQ_H# Table 3. SEL_LCDCLK# Input Functional Table SEL_LCDCLK# 0 1 Pin 13/14 DOT_96 / DOT_96 , select output function of pin 13/14 and 17/18. 0 = LCDCLK & DOT_96 for internal graphic controller ... | Original |
24 pages, |
Slg8sp5 CK410 BSS138 2N3904 SILEGO 2n3904 sot23 slg8sp514 ck505 SLG8SP514 CK505 SLG8SP514 abstract |
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| ) [Frame Rate Control: 4 levels, Pulse Width Modulation: 4 levels] Output for full-dot: 96 www.datasheetarchive.com/files/nec/displays/series/upd16677.htm |
NEC | 17/12/1998 | 8.55 Kb | HTM | upd16677.htm |
| ="PARA"> www.datasheetarchive.com/files/texas-instruments/asl_data/aslbooks/graphics/scbs303c/scbs303c.sgm |
Texas Instruments | 19/08/1996 | 68.56 Kb | SGM | scbs303c.sgm |
| > www.datasheetarchive.com/files/texas-instruments/asl_data/aslbooks/graphics/scbs093g/scbs093g.sgm |
Texas Instruments | 07/09/1996 | 64.36 Kb | SGM | scbs093g.sgm |