DM9131 100BASE-TX 10BASE-T IEEE802 10BASE-TX DM9131-DS-F01 DM9101E 10BTCSR - Datasheet Archive

 

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver General Description The DM9131 is a physical-layer, single-chip,

 

DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver General Description The DM9131 DM9131 is a physical-layer, single-chip, lowpower transceiver for 100BASE-TX 100BASE-TX and 10BASE-T 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Cable 5 (UTP5) for 100BASE-TX 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T 10BASE-T Ethernet, and it also provides PECL interface to connect the external fiber optical transceiver. Through the Media Independent Interface (MII), the DM9131 DM9131 connects to the Medium Access Control (MAC) layer, ensuring a high interoperability among products from different vendors. The DM9131 DM9131 uses a low-power and high-performance CMOS process. It contains the entire physical layer functions of 100BASE-TX 100BASE-TX as defined by IEEE802 IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9131 DM9131 provides a strong support for the autonegotiation function utilizing automatic media speed and protocol selection. Furthermore, due to the builtin wave-shaping filter, the DM9131 DM9131 needs no external filter to transport signals to the media in 100M or 10M Ethernet operation. Block Diagram 100Base-FX PECL Interface 100Base-TX Transceiver 100BaseTX PCS MII Interface 10Base-T TX/RX Module LED Driver Auto-Negotiation Clock Circuit Block Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 Biasing/ Power Block MII Register MII Management Control 1 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Table of Contents General Description .1 DAVICOM Specified Interrupt Register - 21. 20 Block Diagram.1 Features .3 Pin Configuration: DM9101E DM9101E LQFP .4 Pin Description .5 Normal MII Interface, 21 pins.5 Media Interface, 5 pins .6 LED Interface, 5 pins .6 Mode, 11 pins .7 Bias and Clock, 6 pins .7 Power and Others, 52 pins.8 DAVICOM Specified Receive Error Counter Register (RECR) - 22 . 20 DAVICOM Specified Disconnect Counter Register (DISCR) - 23 . 20 T T T T T T Absolute Maximum Ratings. 21 Operating Conditions. 21 Functional Description Transmit Section .9 100Base-TX Operation .9 MII Serial Management Interface.9 Management Interface ­ Read Frame Structure .9 Management Interface ­ Write Frame Structure .9 T T T T T T T T T T PHY ID Identifier Register #2 (PHYIDR2) - 03 .13 Auto-negotiation Advertisement Register (ANAR) - 04.14 T PHY ID Identifier Register #1 (PHYIDR1) - 02 .13 T T Basic Mode Status Register (BMSR) - 01 .12 AC Electrical Characteristics & Timing Waveforms . 22 TP Interface . 22 Oscillator/Crystal Timing . 22 MDC/MDIO Timing. 23 MDIO Timing when OUTPUT by STA . 23 MDIO Timing when OUTPUT by DM9131 DM9131 . 23 MII 100Base-TX Transmit Timing Parameters. 24 MII 100Base-TX Transmit Timing Diagram. 24 MII 100Base-TX Receive Timing Parameters. 24 MII 100Base-TX Receive Timing Diagram. 25 MII 10Base-T Nibble Transmit Timing Parameters . 25 MII 10Base-T Nibble Transmit Timing Diagram . 25 MII 10Base-T Receive Nibble Timing Parameters . 26 MII-10Base-T Receive Nibble Timing Diagram. 26 Auto-negotiation and Fast Link Pulse Timing Parameters . 26 Auto-negotiation and Fast Link Pulse Timing Diagram . 27 T T T T T T T Basic Mode Control Register (BMCR) - 00.11 T MII Register Description.10 - Key To Default .10 DC Electrical Characteristics . 22 Package Information . 28 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05.15 Auto-negotiation Expansion Register (ANER) - 06.16 Ordering Information . 29 Disclaimer . 29 Company Overview. 29 DAVICOM Specified Configuration Register (DSCR) - 16.16 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 .18 Product . 29 Warning . 29 Contact Windows . 29 10Base-T Configuration / Status (10BTCSR 10BTCSR) - 18 .19 2 Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 3 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Features T T T T T T T T T T T T T T T T 4 Fully compliant with IEEE 802.3u 10Base-T/100BaseTX Compliant with ANSI X3T12 X3T12 TP-PMD 1995 standard Support Auto-Negotiation function, compliant to IEEE 802.3u Single-chip fully integrated Physical layer interface directly to magnetic Integrated 10Base-T and 100Base-TX transceiver On-chip filtering, no need for external filters Selectable repeater or node mode Far end fault signaling option in FX mode Selectable twisted-pair or fiber mode output Selectable full-duplex or half-duplex operation MII management interface with maskable interrupts output capability Provides Loopback mode for easy system diagnostics Status LED output provides Link & Activity, Speed10/100 and Full-duplex/Collision LED Low-Power, Single-Supply 3.3V CMOS technology Compatible with 3.3V and 5.0V tolerant I/O 100-pin LQFP Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver NC AVCC NC SD NC AGND DGND NC XT1 XT2 NC DVCC NC OSCIN/REF_CLK OSCSEL NC DGND NC PHYADR0 PHYADR1 PHYADR2 PHYADR3 PHYADR4 TESTMODE NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Pin Configuration NC 1 75 NC BGRESG 2 74 NC BGRES 3 73 RESET# NC 4 72 NC AVCC 5 71 DVCC AVCC 6 70 NC RX+/FXRD+ 7 69 RXEN RX-/FXRD- 8 68 RXER/RXD[4]/RPTR AGND 9 67 RXDV AGND 10 66 COL AGND 11 65 CRS/BP4B5B AGND 12 64 RXCLK TX+/FXTD+ 13 63 MDINTR# TX-/FXTD- 14 62 NC NC 15 61 RXD[0] AVCC 16 60 RXD[1] PLLVCC 17 59 RXD[2] NC 18 58 RXD[3] PLLGND 19 57 NC DGND 20 56 DVCC NC 21 55 NC OPMODE0 22 54 MDIO OPMODE1 23 53 MDC OPMODE2 24 52 NC NC 25 51 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 RMII PWRDWN NC DVCC TRFLED# FDX/COLLED# SPEEDLED# LINK&ACTLED# LINKLED DGND NC TXER/TXD[4] TXD[3] TXD[2] TXD[1] TXD[0] TXEN NC DVCC NC TXCLK NC DGND NC DM9131 DM9131 5 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Pin Description I : Input, O : Output, LI : Latch input when power-up/reset, Z : Tri-State output Normal MII interface, 21 pins Pin No. Pin Name 38 TXER/TXD[4] I/O Description I Transmit Error/The fifth TXD data bit In 100Mbps mode, when the signal actives high and TXEN actives, the HALT symbol is substituted for the actual data nibble. In 10Mbps, the input is ignored. In bypass mode (bypass BP4B5B), TXER becomes the TXD[4] pin, the fifth TXD data bit of the 5B symbol. I Transmit Data 4 bits nibble data input (synchronous to the TXCLK) when in 10/100Mbps nibble mode. In 10Mbps serial mode, the TXD[0] pin is used as the serial data input pin, and TXD[1:3] are ignored. 42,41,40,39 TXD[0:3] 43 TXEN I 47 TXCLK O,Z 53 MDC I 54 MDIO I/O 61,60,59,58 RXD[0:3] O,Z 63 MDINTR# O 64 RXCLK O,Z 65 6 CRS/( BP4B5B ) O,Z /LI Transmit Enable Active high to indicate the presence of valid nibble data on the TXD[0:3] for both 100Mbps and 10Mbps nibble mode. In 10Mbps serial mode, active high indicates the presence of valid 10Mbps data on TXD[0]. Transmit Clock The transmitting clock provides the timing reference for the transfer of the TXEN, TXD, and TXER. TXCLK is provided by the PHY. 25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode, 10MHz in 10Mbps serial mode. Management Data Clock Synchronous clock for the MDIO management data. This clock is provided by management entity, and it is up to 2.5MHZ Management Data I/O Bi-directional management data that may be provided by the station management entity or the PHY. Receive Data Output 4 bits nibble data output (synchronous to RXCLK) when in 10/100Mbps nibble mode. In 10Mbps serial mode, the RXD[0] pin is used as the serial data output pin, and the RXD[1:3] are ignored. Status Interrupt Output: Asserted low whenever there is status change.(link, speed, duplex) Receive Clock, The received clock provides the timing reference for the transfer of the RXDV, RXD, and RXER. RXCLK is provided by PHY. The PHY may recover the RXCLK reference from the received data or it may derive the RXCLK reference from a nominal clock. 25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode, 10MHz in 10Mbps serial mode. Carrier Sense Detect/Bypass 4B/5B encoder/decoder Asserted high to indicate the presence of carrier dues to receive or Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 66 COL O,Z 67 RXDV O,Z 68 RXER/RXD[4] O,Z /(RPTR/NODE) /LI 69 RXEN I 73 RESET# I Media interface, 5 pins Pin No. Pin Name 7,8 RX+/FXRD+ RX-/FXRD- 13,14 TX+/FXTD+ TX-/FXTD- 97 SD LED interface, 5 pins Pin No. Pin Name 31 TRFLED# 32 FDXLED /COLLED# Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 transmit activities in 10BASE-T 10BASE-T or 100BASE-TX 100BASE-TX half-duplex mode. In repeater mode or full-duplex mode, this signal is asserted high to indicate the presence of carrier due only to the receive activity. This pin is also used as bypass 4B/5B encoder/decoder.(power up reset latch input) 0 = normal operation 1 = bypass 4B5B Collision Detection Asserted high to indicate that detection of the collision conditions in 10Mbps and 100Mbps half-duplex mode. In full-duplex mode, this signal is always logical 0. Receive Data Valid Asserted high to indicate that the valid data is present on the RXD[0:3]. Receive Data Error/The fifth RXD data bit of the 5B symbol Asserted high to indicate that an invalid symbol has been detected. In decoder bypass mode (bypass BP4B5B), RXER becomes RXD[4], the fifth RXD data bit of the 5B symbol. These pins are also used to select Repeater or Node mode. (power up reset latch input). 0 = node mode (default) 1 = repeater mode Receive Enable : Active high enable for receive signals RXD[0:3], RXCLK, RXDV and RXCLK. A low on this input tri-states these output pins. For normal operation in a node application, this pin should be pulled high. In repeater application, this pin may be connected to a repeater controller. Reset Active low input that initializes the DM9131 DM9131. I/O Description I Differential receive pair/PECL receive pair Differential data is received from the media. Differential Pseudo ECL signal is received from the media in fiber mode. O Differential transmit pair/PECL transmit pair Differential data is transmitted to the media in TP mode. Differential Pseudo ECL signal transmits to the media in fiber mode. I Fiber-optic signal detect PECL signal which indicates whether or not the fiber-optic receive pair is receiving valid signal levels. I/O Description O Traffic LED Active low. It flashes when the DM9131 DM9131 is transmitting or receiving data. O Full-Duplex LED/Collision LED : Active low. Indicates full-duplex mode for 100Mbps and 10Mbps operation. It is changed to collision LED function when bit 4 of register 16 is set to 1. 7 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 33 34 35 Mode, 11 pins Pin No. 22,23,24 SPEEDLED# O Speed LED: Driven low when operating in 100Mbps and high when operating in 10Mbps. When bit 6 of Register 16 is set, it controls the SPEEDLED as 100BaseTX SD signal output. For debug only. LINK&ACT LED# O Link LED & Activity LED : Active low to indicate good link for 10Mbps and 100Mbps operation. It is also a activity LED function when transmit or receive data. LINKLED O Link LED Active high to indicate good link for 10Mbps and 100Mbps operation Pin Name OPMODE0~2 I/O Description LI OPMODE0~OPMODE2 : These pins are used to control the forced or advertised operating mode of the DM9131 DM9131 according to the following table. The value is latched into the DM9131 DM9131 registers at power-up/reset. OP2 27 I 28 PWRDWN I 77 TESTMODE I 82~78 8 RMII PHYADR[0:4] I OP1 OP0 Function 0 0 0 auto negotiation enable with all capabilities 0 0 1 manual select 100TX 100TX FDX 0 1 0 manual select 100TX 100TX HDX 0 1 1 manual select 10TX FDX 1 0 0 manual select 10TX HDX 1 0 1 manual select 100FX 100FX FDX 1 1 0 manual select 100FX 100FX HDX 1 1 1 dual speed 100/10 HDX Reduced MII enable: This pin is used to select Normal MII or Reduced MII. "0"= Normal MII, (default) "1"= Reduced MII. This pin always pull-low except that DM9131 DM9131 is used as reduced MII. Power down control Assert high to force DM9131 DM9131 into power down mode. When in power down mode, most of the DM9131 DM9131 circuit block's power is truned off, only the MII management interface (MDC, MDIO) logic is available (the PHY should respond to management transactions and should not generate spurious signals on the MII). To leave power down mode, DM9131 DM9131 need the hardware or software reset with the PWRDWN pin to low. Test mode control pin. 0 = normal operation 1 = enable test mode PHY address PHY address sensing input pins. Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Bias and clock, 6 pins Pin No. Pin Name 2 BGRESG 3 BGRES 86 OSCSEL 87 OSCIN / REF_CLK 91 XT2 92 XT1 Power and others, 52 pins Pin No. Pin Name 5,6,16,99 AVCC 9,10,11,12,95 AGND 30,45,56,71, DVCC 89 20,36,49,84 DGND ,94 17 PLLVCC 19 PLLGND 1,4,15,18,21, NC 25,26,29,37, 44,46,48,50, 51,52,55,57, 62,70,72,74, 75,76,83,85, 88,90,93,96, 98,100 Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 I/O P P I I Description Bandgap Ground Bandgap Voltage Reference Resistor 6.2K ohm Oscillator or Crystal selection. "0" = Crystal, "1" = Oscillator Oscillator input (25MHz) or Reduced MII Reference Clock Input (50MHz for Reduced MII only). O Crystal Output I Crystal Input I/O P Analog Power P Analog Ground P Digital Power Description P Digital Ground P Analog Power P Analog Ground Not connected. 9 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Functional Description The DM9131 DM9131 Fast Ethernet single-chip PHY transceiver, provides the functionality as specified in IEEE802 IEEE802.3, integrates the complete 100BASE-TX 100BASE-TX module and the complete 10BASE-T 10BASE-T module. The DM9131 DM9131 also provides a standard Media Independent Interface (MII) to connect a media access controller and a network media. The DM9131 DM9131 performs all PCS, PMA, and TP-PMD sub-layer as defined by specification. MII Serial Management Interface The serial management interface uses a simple, twowired serial interface to obtain and control the status of the physical layer through an MII interface (MDC and MDIO pins). The Management Data Clock (MDC) is equipped with a maximum clock rate of 2.5MHz, while Management Data Input /Output (MDIO) works as a bi-directional, open-drain pin shared by up to 32 devices. Transmit Section DM9131 DM9131's management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) and the registers 0 through 6 with vendor-specific registers 11,15,16,17,18. The transmit section consists of the following blocks: - PCS Transmit - Clock Generator - NRZ to NRZI. MLT3 encoder and driver - MANCHESTER encoder - 10BASET-TX 10BASET-TX filter and driver In read/write operation, the management data frame is 64-bit long start with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a pattern followed by the operation code (OP): indicates Read operation and indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Resistor Address field and Data field is provided for MDIO to avoid contention. "Z" stands for high impedance state. Following turnaround time, a 16-bit data is read from or written onto management registers. 100BASE-TX 100BASE-TX Operation The 100BASE-TX 100BASE-TX transmitter receives 4-bit nibbledata clocked in at 25MHz at the MII and outputs scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The on-chip clock circuit converts 25MHz clock into a 125MHz clock for internal use. Management Interface - Read Frame Structure MDC / / MDIO Read 32 "1"s Idle 0 Preamble 1 SFD 1 0 A4 Op Code A3 A0 PHY Address R4 R3 R0 Register Address 0 Z D15 D14 Turn Around D1 Data Read Write / / D0 Idle Management Interface - Write Frame Structure MDC MDIO Write 32 "1"s Idle 10 Preamble 0 1 SFD 0 Op Code 1 A4 A3 PHY Address A0 R4 R3 Register Address Write R0 1 0 Turn Around D15 D14 D1 Data D0 Idle Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver MII Register Description 01 02 03 04 05 06 16 17 18 21 22 23 Name CONTROL 15 Reset 14 Loop back STATUS T4 TX FDX Cap. Cap. PHYID1 0 0 PHYID2 1 0 Auto-Neg. Next FLP Rcv Advertise Page Ack Link Part. LP Next LP Ability Page Ack Auto-Neg. Expansion Aux. BP BP Config. 4B5B SCR Aux. 100 100 Conf/Stat FDX HDX 10T Rsvd LP Conf/Stat Enable MDINTR INTR Rsvd PEND Rcv Error Counter Disconnect Counter 13 Speed select TX HDX Cap. 0 1 Remote Fault LP RF 12 11 10 9 8 7 6 Auto-N Power Isolate Restart Full Coll. Enable Down Auto-N Duplex Test 10 FDX 10 HDX Reserved Pream. Cap. Cap. Supr. 0 0 0 0 1 1 0 1 1 0 Model No. Reserved FC T4 TX FDX TX HDX 10 FDX Adv Adv Adv Adv Adv Reserved LP LP LP LP LP FC T4 TX FDX TX HDX 10 FDX Reserved 5 4 3 2 Reserved 1 Reserved Disconnect Counter In the register description that follows, the default column takes the form: , / : RO = Read only RW = Read/Write Where : 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset : SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 0 Auto-N Remote Auto-N Link Jabber Extd Compl. Fault Cap. Status Detect Cap. 0 0 0 0 0 0 Version No. 10 HDX Advertised Protocol Selector Field Adv LP Link Partner Protocol Selector Field 10 HDX Pardet LP Next Next Pg New Pg LP AutoN Fault Pg Able Able Rcv Cap. BP BP_AD Repeat TX/FX FEF RMII Force SPDLE Rsvd FDXLE Reset Pream. Sleep Remote ALIGN POK mode Select Enable Enable 100LNK 100LNK D_CTL D_CTL St. Mch Supr. mode LoopOut 10 10 HDX Reserved PHY ADDR [4:0] Auto-N. Monitor Bit [3:0] FDX HBE SQUE JAB 10T Reserved Polarity Enable Enable Enable Serial Reverse Rsvd Rsvd FDX SPD Link INTR Rsvd Rsvd Rsvd FDX SPD Link INT INTR Mask Mask Mask Mask Change Change Change Enable Status Receive Error Counter Key to Default ' ADD 00 11 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Basic Mode Control Register (BMCR) - 00 Bit 0.15 Default 0, RW/SC 0.14 Loopback 0, RW 0.13 Speed selection 1, RW 0.12 Autonegotiation enable Power down 1, RW 0.11 0.10 Isolate 0,RW 0.9 12 Bit Name Reset Restart autonegotiation 0,RW/SC 0, RW Description Reset: 1=Software reset 0=Normal operation This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed Loopback: Loop-back control register 1 = Loop-back enabled 0 = Normal operation When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appear at the MII receive outputs Speed select: 1 = 100Mbps 0 = 10Mbps Link speed may be selected either by this bit or by auto-negotiation. When auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected media type. Auto-negotiation enable: 1 = Auto-negotiation is enabled, bit 8 and 13 will be in autonegotiation status Power Down: While in the power-down state, the PHY should respond to management transactions. During the transition to power-down state and while in the power-down state, the PHY should not generate spurious signals on the MII. 1=Power down 0=Normal operation Isolate: 1 = Isolates the DM9131 DM9131 from the MII with the exception of the serial management. (When this bit is asserted, the DM9131 DM9131 does not respond to the TXD[0:3], TX_EN, and TX_ER inputs, and it shall present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RX[0:3], COL and CRS outputs. When PHY is isolated from the MII it shall respond to the management transactions) 0 = Normal operation Restart auto-negotiation: 1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning a value of 1 until autonegotiation is initiated by the DM9131 DM9131. The operation of the autonegotiation process will not be affected by the management entity that clears this bit 0 = Normal operation Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 0.8 Duplex mode 1,RW 0.7 Collision test 0,RW 0.6-0.0 Reserved 0,RO Duplex mode: 1 = Full duplex operation. Duplex selection is allowed when Autonegotiation is disabled (bit 12 of this register is cleared). With auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation Collision test: 1 = Collision test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN 0 = Normal operation Reserved: Write as 0, ignore on read Basic Mode Status Register (BMSR) - 01 Bit 1.15 Bit Name 100BASE-T4 100BASE-T4 Default 0,RO/P 1.14 100BASE-TX 100BASE-TX full duplex 1,RO/P 1.13 100BASE-TX 100BASE-TX half duplex 1,RO/P 1.12 10BASE-T 10BASE-T full duplex 1,RO/P 1.11 10BASE-T 10BASE-T half duplex 1,RO/P 1.10-1.7 Reserved 0,RO 1.6 MF preamble suppression 0,RO 1.5 Autonegotiation Complete Remote fault 0,RO 1.4 1.3 1.2 Autonegotiation ability Link status Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 0, RO/LH 1,RO/P 0,RO/LL Description 100BASE-T4 100BASE-T4 capable: 1 = DM9131 DM9131 is able to perform in 100BASE-T4 100BASE-T4 mode 0 = DM9131 DM9131 is not able to perform in 100BASE-T4 100BASE-T4 mode 100BASE-TX 100BASE-TX full duplex capable: 1 = DM9131 DM9131 is able to perform 100BASE-TX 100BASE-TX in full duplex mode 0 = DM9131 DM9131 is not able to perform 100BASE-TX 100BASE-TX in full duplex mode 100BASE-TX 100BASE-TX half duplex capable: 1 = DM9131 DM9131 is able to perform 100BASE-TX 100BASE-TX in half duplex mode 0 = DM9131 DM9131 is not able to perform 100BASE-TX 100BASE-TX in half duplex mode 10BASE-T 10BASE-T full duplex capable: 1 = DM9131 DM9131 is able to perform 10BASE-T 10BASE-T in full duplex mode 0 = DM9131 DM9131 is not able to perform 10BASE-TX 10BASE-TX in full duplex mode 10BASE-T 10BASE-T half duplex capable: 1 = DM9131 DM9131 is able to perform 10BASE-T 10BASE-T in half duplex mode 0 = DM9131 DM9131 is not able to perform 10BASE-T 10BASE-T in half duplex mode Reserved: Write as 0, ignore on read MII frame preamble suppression: 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed Auto-negotiation complete: 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed Remote fault: 1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9131 DM9131 implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0 = No remote fault condition detected Auto configuration ability: 1 = DM9131 DM9131 is able to perform auto-negotiation 0 = DM9131 DM9131 is not able to perform auto-negotiation Link status: 13 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 1.1 Jabber detect 0, RO/LH 1.0 Extended capability 1,RO/P 1 = Valid link is established (for either 10Mbps or 100Mbps operation) 0 = Link is not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface Jabber detect: 1 = Jabber condition detected 0 = No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9131 DM9131 reset. This bit works only in 10Mbps mode Extended capability: 1 = Extended register capable 0 = Basic register capable only PHY ID Identifier Register #1 (PHYID1) - 02 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9131 DM9131. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E 00606E. Bit 2.15-2.0 Bit Name OUI_MSB Default Description OUI most significant bits: This register stores bit 3 to 18 of the OUI (00606E 00606E) to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2) PHY Identifier Register #2 (PHYID2) - 03 Bit 3.15-3.10 Bit Name OUI_LSB Default , RO/P 3.9-3.4 VNDR_MDL , RO/P 3.3-3.0 MDL_REV , RO/P 14 Description OUI least significant bits: Bit 19 to 24 of the OUI (00606E 00606E) are mapped to bit 15 to 10 of this register respectively Vendor model number: Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) Model revision number: Four bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3) Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Auto-negotiation Advertisement Register(ANAR) - 04 This register contains the advertised abilities of this DM9131 DM9131 device as they will be transmitted to its link partner during Auto-negotiation. Bit 4.15 Bit Name NP 4.14 ACK 4.13 RF 4.12-4.11 Reserved 4.10 FCS 4.9 T4 4.8 TX_FDX 4.7 TX_HDX 4.6 10_FDX 4.5 10_HDX 4.4-4.0 Selector Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 Default 0,RO/P Description Next page indication: 0 = No next page available 1 = Next page available The DM9131 DM9131 has no next page, so this bit is permanently set to 0 0,RO Acknowledge: 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9131 DM9131's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. 0, RW Remote fault: 1 = Local device senses a fault condition 0 = No fault detected X, RW Reserved: Write as 0, ignore on read 0, RW Flow control support: 1 = Controller chip supports flow control ability 0 = Controller chip doesn't support flow control ability 0, RO/P 100BASE-T4 100BASE-T4 support: 1 = 100BASE-T4 100BASE-T4 is supported by the local device 0 = 100BASE-T4 100BASE-T4 is not supported The DM9131 DM9131 does not support 100BASE-T4 100BASE-T4 so this bit is permanently set to 0 1, RW 100BASE-TX 100BASE-TX full duplex support: 1 = 100BASE-TX 100BASE-TX full duplex is supported by the local device 0 = 100BASE-TX 100BASE-TX full duplex is not supported 1, RW 100BASE-TX 100BASE-TX support: 1 = 100BASE-TX 100BASE-TX is supported by the local device 0 = 100BASE-TX 100BASE-TX is not supported 1, RW 10BASE-T 10BASE-T full duplex support: 1 = 10BASE-T 10BASE-T full duplex is supported by the local device 0 = 10BASE-T 10BASE-T full duplex is not supported 1, RW 10BASE-T 10BASE-T support: 1 = 10BASE-T 10BASE-T is supported by the local device 0 = 10BASE-T 10BASE-T is not supported , RW Protocol selection bits: These bits contain the binary encoded protocol selector supported by this node. indicates that this device supports IEEE 802.3 CSMA/CD. 15 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Auto-negotiation Link Partner Ability Register (ANLPAR) ­ 05 This register contains the advertised abilities of the link partner When received during Auto-negotiation. Bit 5.15 Bit Name NP 5.14 ACK 5.13 RF 5.12-5.11 Reserved 5.10 FCS 5.9 T4 5.8 TX_FDX 5.7 TX_HDX 5.6 10_FDX 5.5 10_HDX 5.4-5.0 Selector 16 Default 0, RO Description Next page indication: 0 = Link partner, no next page available 1 = Link partner, next page available 0, RO Acknowledge: 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9131 DM9131's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit. 0, RO Remote Fault: 1 = Remote fault indicated by link partner 0 = No remote fault indicated by link partner X, RO Reserved: Write as 0, ignore on read 0, RW Flow control support: 1 = Controller chip supports flow control ability by link partner 0 = Controller chip doesn't support flow control ability by link partner 0, RO 100BASE-T4 100BASE-T4 support: 1 = 100BASE-T4 100BASE-T4 is supported by the link partner 0 = 100BASE-T4 100BASE-T4 is not supported by the link partner 0, RO 100BASE-TX 100BASE-TX full duplex support: 1 = 100BASE-TX 100BASE-TX full duplex is supported by the link partner 0 = 100BASE-TX 100BASE-TX full duplex is not supported by the link partner 0, RO 100BASE-TX 100BASE-TX support: 1 = 100BASE-TX 100BASE-TX half duplex is supported by the link partner 0 = 100BASE-TX 100BASE-TX half duplex is not supported by the link partner 0, RO 10BASE-T 10BASE-T full duplex support: 1 = 10BASE-T 10BASE-T full duplex is supported by the link partner 0 = 10BASE-T 10BASE-T full duplex is not supported by the link partner 0, RO 10BASE-T 10BASE-T support: 1 = 10BASE-T 10BASE-T half duplex is supported by the link partner 0 = 10BASE-T 10BASE-T half duplex is not supported by the link partner , RO Protocol selection bits: Link partner's binary encoded protocol selector Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Auto-negotiation Expansion Register (ANER)- 06 6.15-6.5 Reserved X, RO 6.4 PDF 0, RO/LH 6.3 LP_NP_ABLE 0, RO 6.2 NP_ABLE 0,RO/P 6.1 PAGE_RX 0, RO/LH 6.0 LP_AN_ABLE 0, RO Reserved: Write as 0, ignore on read Local device parallel detection fault: PDF = 1 : A fault detected via parallel detection function. PDF = 0 : No fault detected via parallel detection function Link partner next page able: LP_NP_ABLE = 1 : Link partner, next page available LP_NP_ABLE = 0 : Link partner, no next page Local device next page able: NP_ABLE = 1 : DM9131 DM9131, next page available NP_ABLE = 0 : DM9131 DM9131, no next page DM9131 DM9131 does not support this function, so this bit is always 0. New page received: A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management. Link partner auto-negotiation able: A "1" in this bit indicates that the link partner supports Autonegotiation. DAVICOM Specified Configuration Register (DSCR) - 16 Bit 16.15 Bit Name BP_4B5B 16.14 BP_SCR 16.13 BP_ALIGN 16.12 BP_ADPOK 16.11 REPEATER 16.10 TX Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 Default Description (Pin#xx), RW Bypass 4B5B encoding and 5B4B decoding : The value of the BP4B5B pin(xx) is latched into this bit at powerup/reset. 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation 0, RW Bypass scrambler/descrambler function : 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 0, RW Bypass symbol alignment function: 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions ( symbol encoder and scrambler) bypassed 0 = Normal operation 0, RW BYPASS ADPOK : Force signal detector (SD) active. This register is for debug only, not release to customer. 1=Force SD is OK, 0=Normal operation (Pin#xx),RW Repeater/Node mode : The value of the Repeater/Node pin(xx) is latched into this bit at power-up/reset. 1 = Repeater mode 0 = Node mode 1, RW 100BASE-TX 100BASE-TX or FX mode control: 1 = 100BASE-TX 100BASE-TX operation 0 = 100BASE-FX 100BASE-FX operation 17 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 16.9 16.8 RMII_Enable 16.7 F_LINK_100 16.6 SPLED_CTL 16.5 16.4 Reserved FDXLED_CTL 16.3 SMRST 16.2 MFPSC 16.1 SLEEP 16.0 18 FEF RLOUT 0, RW Far End Fault enable : Control the Far End Fault mechanism associated with 100Base-FX operation. 1 = Enable 0 = Disable (Pin#xx), RW Reduced MII enable : Select normal MII or reduced MII. The value of the RMII pin(xx) is latched into this bit at power-up/reset. 0 = Normal MII 1 = Enable Reduced MII 0, RW Force good link in 100Mbps: 0 = Normal 100Mbps operation 1 = Force 100Mbps good link status This bit is useful for diagnostic purposes. 0, RW Speed LED Disable : 0 : Normal SPEEDLED output to indicate speed status 1 : Disable SPEEDLED output and enable SD signal monitor (for internal debug). When this bit is set, it control the SPEEDLED as 100BASE-X 100BASE-X SD (not fiber mode) signal output .For debug only. Reserved 0, RO Full-duplex LED mode select : 0,RW 0 = FDXLED output is configured to indicate full-duplex status 1 = COLLED output is configured to indicate the presence of collision activity operation. Reset state machine: 0, RW When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed. MF preamble suppression control: 0, RW MII frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off Sleep mode: 0, RW Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset Remote loopout control: 0, RW When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DAVICOM Specified Configuration and Status Register (DSCSR) - 17 Bit 17.15 Bit Name 100FDX 100FDX Default 1, RO 17.14 100HDX 100HDX 1, RO 17.13 10FDX 10FDX 1, RO 17.12 10HDX 10HDX 1, RO 17.1117.9 17.8-17.4 Reserved 0, RO PHYADR[4:0] (PHYADR), RW 17.3-17.0 ANMB[3:0] 0, RO Description 100M full duplex operation mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M full duplex mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode. 100M half duplex operation mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M half duplex mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode. 10M full duplex operation mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode. 10M half duplex operation mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M half duplex mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode. Reserved: Write as 0, ignore on read PHY address Bit 4:0: The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY. Auto-negotiation monitor bits: These bits are for debug only. The auto-negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal_link_ready Parallel detects signal_link_ready fail Auto-negotiation completed successfully 19 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 10BASE-T 10BASE-T Configuration/Status (10BTCSR 10BTCSR) - 18 Bit 18.15 Bit Name Reserved Default 0, RO 18.14 LP_EN 1, RW 18.13 HBE 1,RW 18.12 SQUELCH 1, RW 18.11 JABEN 1, RW 18.10 10BT_SER 0,RW 18.9-18.1 Reserved 0, RO 18.0 POLR 0, RO 20 Description Reserved: Write as 0, ignore on read Link pulse enable: 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation. Heartbeat enable: 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9131 DM9131 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode). Squelch enable : 1 = normal squelch 0 = low squelch Jabber Enable: Enables or disables the Jabber function when the DM9131 DM9131 is in 10BASE-T 10BASE-T full duplex or 10BASE-T 10BASE-T transceiver loopback mode 1 = Jabber function enabled 0 = Jabber function disabled 10BASE-T 10BASE-T serial mode: 1 = 10BASE-T 10BASE-T serial mode selected 0 = 10BASE-T 10BASE-T nibble mode selected Serial mode is not supported for 100Mbps operation. Reserved: Write as 0, ignore on read Polarity reversed: When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is set and cleared by 10BASE-T 10BASE-T module automatically. Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DAVICOM Specified Interrupt Register ­ 21 Bit 21.15 Bit Name INTR PEND Default 0, RO 21.1421.12 21.11 Reserved 0, RO FDX mask 1, RW 21.10 SPD mask 1, RW 21.9 LINK mask 1, RW 21.8 INTR mask 1, RW 21.7-21.5 21.4 Reserved FDX change 0, RO 0,RO/LH 21.3 SPD change 0, RO/LH 21.2 LINK change 0, RO/LH 21.1 INTR enable 0, RW 21.0 INTR status 0, RO/LH Description Interrupt pending : Indicates that the interrupt is pending and is cleared by the current read. This bit shows the same result as bit 0. (INTR Status) Reserved Full-duplex interrupt mask : When this bit is set, the Duplex status change will not generate the interrupt Speed interrupt mask : When this bit is set, the Speed status change will not generate the interrupt Link interrupt mask : When this bit is set, the link status change will not generate the interrupt Master interrupt mask : When this bit is set, no interrupts will be generated under any condition. Reserved Duplex status change interrupt : "1" indicates a change of duplex since last register read. A read of this register will clear this bit. Speed status change interrupt : "1" indicates a change of speed since last register read. A read of this register will clear this bit. Link status change interrupt : "1" indicates a change of link since last register read. A read of this register will clear this bit. Interrupt enable : "1" = enable the interrupt mode, "0" = disable Interrupt status : The status of MDINTR# . "1" indicates that the interrupt mask is off that one or more of the change bits are set. A read of this register will clear this bit. DAVICOM Specified Receive Error Counter Register (RECR) ­ 22 Bit 22.15-0 Bit Name Rcv_Err_Cnt Default 0, RO Description Receive error counter : Receive error counter that increments upon detection of REER DAVICOM Specified Disconnect Counter Register (DISCR) ­ 23 Bit 23.1523.8 23.7-23.0 Bit Name Reserved Default 0, RO Disconnect Counter 0, RO Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 Description Reserved Disconnect Counter that increments upon detection of disconnection. 21 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Absolute Maximum Ratings Absolute Maximum Ratings ( 25°C ) ° Symbol DVCC, AVCC VIN VOUT Tstg PD LT Parameter Supply Voltage DC Input Voltage (V IN) DC Output Voltage(VOUT) Storage Temperature Rang (T stg) Power Dissipation (PD) Lead Temp. (TL, Soldering, 10 sec.) Min. -0.3 -0.5 -0.3 -40 - Max. 3.6 5.5 3.6 +125 0.43 240 Unit V V V °C W °C Conditions Min. 3.135 - Max. 3.465 85 115 25 125 44 76 Unit V °C mA mA mA mA mA Conditions Operating Conditions Symbol DVCC,AVCC Tc PD (Power Dissipation) Parameter Supply Voltage Case Temperature 100BASE-TX 100BASE-TX 100BASE-FX 100BASE-FX 10BASE-T 10BASE-T TX 10BASE-T 10BASE-T idle Auto-negotiation 3.3V 3.3V 3.3V 3.3V 3.3V Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the 22 operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DC Electrical Characteristics (VCC = 3.3V) Symbol Parameter Min. Typ. Max. Unit Conditions TTL Inputs (TXD0~TXD3, TXCLK, MDC, MDIO, TXEN, TXER, RXEN, TESTMODE, RMII, OSCSEL, PHYAD0~4, OPMODE0-2, RPTR, BP4B5B, RESET# ) VIL Input Low Voltage -0.8 V VIH Input High Voltage 2.0 -V IIL Input Low Leakage Current -10 uA VIN = 0.4V IIH Input High Leakage Current -10 uA VIN = 2.7V MII TTL Outputs ( RXD0-RXD3, RXDV, RXER, CRS, COL, MDIO) VOL Output Low Voltage -0.4 V IOL = 4mA VOH Output High Voltage 2.4 -V IOH = -4mA Non-MII TTL Outputs (LINKLED#, SPEEDLED#, FDXLED#, MDINTR#) VOL Output Low Voltage -0.4 V IOL = 1mA VOH Output High Voltage 2.4 -V IOH = -0.1mA Receiver VICM RX+/RX- Common mode Input Voltage -0.9 -V 100 Termination Across Transmitter VTD100 VTD100 100TX 100TX+/- Differential Output Voltage 1.9 2.0 2.1 V Peak to Peak VTD10 VTD10 10TX+/- Differential Output Voltage 4.4 5 5.6 V Peak to Peak ITD100 ITD100 100TX 100TX+/- Differential Output Current · 19· · 20· · 21· mA ITD10 ITD10 10TX+/- Differential Output Current · 44· · 50· · 19· mA VOH PECL Output Voltage ­ High VOL PECL Output Voltage ­ Low IFD100 IFD100 100FX 100FX+/- Differential Output Current VCC1.05 VCC1.81 · 17· VCC0.88 VCC1.62 · 19· mA Min. 3.0 0 0 Typ. - Max. 5.0 0.5 0.5 Unit ns ns ns 0 0 - 1.4 5 ns % Min. 39.998 16 16 Typ. 40 20 20 Max. 40.002 24 24 Unit ns ns ns · 18· V V AC Electrical Characteristics & Timing Waveforms TP Interface Symbol Parameter tTR/F 100TX 100TX+/- Differential Rise/Fall Time tTM 100TX 100TX+/- Differential Rise/Fall Time Mismatch tTDC 100TX 100TX+/- Differential Output Duty Cycle Distortion tT/T 100TX 100TX+/- Differential Output Peak-to-Peak Jitter XOST 100TX 100TX+/- Differential Voltage Overshoot Oscillator/Crystal Timing Symbol Parameter tCKC OSC Cycle Time tPWH OSC Pulse Width High tPWL OSC Pulse Width Low Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 Conditions Conditions 50ppm 23 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver MDC/MDIO Timing Symbol Parameter t0 MDC Cycle Time t1 MDIO Setup Before MDC t2 MDIO Hold After MDC t3 MDC To MDIO Output Delay Min. 80 10 10 0 Typ. - Max. -300 Unit ns ns ns ns Conditions When OUTPUT By STA When OUTPUT By STA When OUTPUT By DM9131 DM9131 MDIO timing when OUTPUT by STA MDC t0 10ns (Min) t1 10ns (Min) t2 MDIO MDIO timing when OUTPUT by DM9131 DM9131 MDC 0 - 300 ns t3 MDIO 24 Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 100BASE-TX 100BASE-TX Transmit Timing Parameters Symbol tTXc tTXh, tTXl tTXs tTXh tTXOD t1 t2 tTXpd tTXr/f Parameter TXCLK Cycle Time TXCLK High/Low Time TXD[0:3], TXEN, TXER Setup To TXCLK High TXD[0:3], TXEN, TXER Hold From TXCLK High TXCLK to Output Delay TXEN Sampled To CRS Asserted TXEN Sampled To CRS De-asserted TXEN Sampled To TX+/- Out(Tx Latency) 100TX 100TX Driver Rise/Fall Time Min. 39.996 16 15 15 Typ. 40 20 - -3 4 4 8 4 Max. 40.004 24 -25 -5 Unit ns ns ns ns ns BT BT BT ns Conditions 90% To 10%, Into 100ohm Differential 1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing. + 100BASE-TX 100BASE-TX Transmit Timing Diagram TXCLK tTXc t TX S tTXh t TX h TXD [0:3], TXEN, TXER tTXOD t2 t1 CRS t TX r/f t TX pd 100TX 100TX+/- 100BASE-TX 100BASE-TX Receive Timing Parameter Symbol tRXc tRXh, tRXl tRXs Parameter RXCLK Cycle Time RXCLK High/Low Time RXD[0:3), RXDV, RXER Setup To RXCLK High Min. 39.996 16 10 tRXh tRXpd t1 t2 t3 t4 t5 RXD[0:3], RXDV, RXER Hold From RXCLK High RX+/- In To RXD[0:3] Out (Rx Latency) CRS Asserted To RXD[0:3], RXDV, RXER CRS De-asserted To RXD[0:3], RXDV, RXER RX+/- In To CRS Asserted RX+/- Quiet To CRS De-asserted RX+/- In To COL De-Asserted 10 10 14 14 Typ. 40 20 15 4 0 - Max. 40.004 24 - Unit 14 18 18 Conditions ns BT BT BT BT BT BT ns 1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing. + Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 25 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver MII 100BASE-TX 100BASE-TX Receive Timing Diagram RXCLK t TX pd tRXS tRXh tRXh tRXc RXD [0:3], RXDV, RXER t1 t2 t4 CRS t3 RX+/- t5 t5 COL MII 10BASE-T 10BASE-T Nibble Transmit Timing Parameters Symbol TTXs TTXh t1 t2 TTXpd Parameter TXD[0:3), TXEN, TXER Setup To TXCLK High TXD[0:3], TXEN, TXER Hold From TXCLK High TXEN Sampled To CRS Asserted TXEN Sampled To CRS De-asserted TXEN Sampled To 10TXO 10TXO Out (Tx Latency) Min. 5 5 Typ. - Max. - Unit ns ns - 2 15 2 4 20 4 Conditions BT BT BT MII 10BASE-T 10BASE-T Nibble Transmit Timing Diagram TXCLK t T Xh tT X S TXD [0:3], TXEN, TXER t2 t1 CRS t T X pd 10TX+/- 26 Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver MII 10BASE-T 10BASE-T Receive Nibble Timing Parameters Symbol tRXs Parameter RXD[0:3), RXDV, RXER Setup To RXCLK High Min. 5 Typ. - Max. - Unit ns tRXh tRXpd t1 t2 t3 t4 RXD[0:3], RXDV, RXER Hold From RXCLK High RXI In To RXD[0:3] Out (Rx Latency) CRS Asserted To RXD[0:3], RXDV, RXER CRS De-asserted To RXD[0:3], RXDV, RXER RXI In To CRS Asserted RXI Quiet To CRS De-asserted 5 -1 -1 1 -7 14 -2 10 -20 3 4 15 Conditions ns BT BT BT BT BT MII 10BASE-T 10BASE-T Receive Nibble Timing Diagram RXCLK t T X pd tR XS tR Xh RXD [0:3], RXDV, RXER t1 t2 CRS t4 t3 RX+/- Auto-negotiation and Fast Link Pulse Timing Parameters Symbol t1 t2 t3 t4 t5 - Parameter Clock/Data Pulse Width Clock Pulse To Data Pulse Period Clock Pulse To Clock Pulse Period FLP Burst Width FLP Burst To FLP Burst Period Clock/Data Pulses in a Burst Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 Min. -55.5 111 8 17 Typ. 100 62.5 125 2 Max. -69.5 139 24 33 Unit ns us us ms ms pulse Conditions DATA = 1 27 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Auto-negotiation and Fast Link Pulse Timing Diagram NLPs t3 FLP Burst FLP Burst FLP Bursts t4 t5 Clock Pulse FAST LINK PULSES Data Pulse Clock Pulse t1 t1 t2 t3 FLP Burst FLP Burst 10TX0 10TX0+/t4 t5 28 Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Package Information LQFP 100L Outline Dimensions Unit: Inches/mm Symbol Dimensions In Inches Dimensions In mm A 0.063 Max. 1.60 Max. A1 0.004 ± 0.002 0.1 ± 0.05 A2 0.055 ± 0.002 D y 1.40 ± 0.05 b 0.009 ± 0.002 0.22 ± 0.05 c 0.006 ± 0.002 0.15 ± 0.05 D 0.551 ± 0.005 14.00 ± 0.13 E 0.551 ± 0.005 14.00 ± 0.13 e 0.020 BSC. 0.50 BSC. F 0.481 NOM. 12.22 NOM. GD 0.606 NOM. 15.40 NOM. HD 0.630 ± 0.006 16.00 ± 0.15 HE 0.630 ± 0.006 16.00 ± 0.15 L 0.024 ± 0.006 0.60 ± 0.15 L1 0.039 Ref. 1.00 Ref. y 0.004 Max. 0.1 Max. 0° ~ 12° 0° ~ 12° Note: 1. Dimension D & E do not include resin fins. 2. Dimension GD is for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system. Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000 29 DM9131 DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Ordering Information Part Number DM9131 DM9131 Pin Count 100 Package LQFP DAVICOM's terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer's orders shall be based on these terms. Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM deserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. Company Overview DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that re the industry's best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5798858 Taipei Sales & Marketing Office: 8F, No. 3, Lane 235, Bao-chiao Rd., Hsin-tien, Taipei, Taiwan, R.O.C. TEL: 02-29153030 FAX: 02-29157575 Email: sales@davicom.com.tw Davicom USA Sunnyvale, California 1135 Kern Ave., Sunnyvale, CA94086 CA94086, U.S.A. TEL: 1-408-7368600 FAX: 1-408-7368688 Email: sales@davicom8.com WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. 30 Final Version: DM9131-DS-F01 DM9131-DS-F01 April 7, 2000