DM560P DM6580 DM6581 DM6582 DM6583 DM560P-DS-F01 DM6581/82 IS-101 DM6581/DM6582

V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set General Description The DM560P integrated modem is a four chipset

DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set General Description The DM560P DM560P integrated modem is a four chipset design that provides a complete solution for stateof-the-art, voice-band Plain Old Telephone Service (POTS) communication. The modem provides for Data (up to 56,000bps), Fax (up to 14,400bps), Voice and Full Duplex Speaker-phone functions to comply with various international standards. The design of the DM560P DM560P is optimized for desktop personal computer applications and it provides a low cost, highly reliable, maximum integration, with the minimum amount of support required. The DM560P DM560P modem can operate over a dial-up network (PSTN) or 2 wire leased lines. The modem integrates auto dial and answer capabilities, synchronous and asynchronous data transmissions, serial and parallel interfaces, various tone detection schemes and data test modes. The DM560P DM560P modem reference design is preapproved for FCC part 68 and provides minimum design cycle time, with minimum cost to insure the maximum amount of success. The simplified modem system, shown in figure below, illustrates the basic interconnection between the MCU, DSP, AFE and other basic components of a modem. The individual elements of the DM560P DM560P are: · · · · DM6580 DM6580 Analog Front End (AFE). 28-pin PLCC package DM6581 DM6581 ITU-T V.90 Transmit Digital Signal Processor (TX DSP). 100-pin QFP package DM6582 DM6582 ITU-T V.90 Receive Digital Signal Processor (RX DSP). 100-pin QFP package DM6583 DM6583 Modem Controller (MCU) built in Plug & Play (PnP). 100-pin QFP package Block Diagram LED Address & Data Bus DM6583 DM6583 29.4912 MHz ISA Bus Micro Controller Unit MSCLK PnP DM6581 DM6581 TX DSP DM6582 DM6582 RX DSP V.24 Interface Ring Detector 40.32MHz TxD RxD SCLK DIT DOT TFS DIR DOR RFS TxBCLK TxSCLK*2 RxBCLK RxSCLK 20.16MHz TxDCLK RxDCLK DM6580 DM6580 RxIN TxA1 Analog Front End SPKR DAA Lin e TxA2 Speaker Driver Microphone Driver V.24 Interface Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 1 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set Table of Contents General Description 1 Block Diagram 1 Features 3 Chipset Chip 1: DM6583 DM6583 Modem Controller Unit with PnP DM6583 DM6583 Description DM6583 DM6583 Block Diagram DM6583 DM6583 Features DM6583 DM6583 Pin Configuration DM6583 DM6583 Pin Description DM6583 DM6583 Functional Description 1. Operating Mode Selection 2. Micro-controller Program Memory 3. Micro-controller Register Description 4. UART (16550A) Emulation Registers 5. Plug and Play (PnP) Module DM6583 DM6583 Absolute Maximum Ratings DM6583 DM6583 DC Electrical Characteristics DM6583 DM6583 AC Electrical Characteristics & Timing Waveforms 4 4 4 5 6 8 8 8 8 11 16 24 24 2 30 30 30 30 30 DM6581/82 DM6581/82 Absolute Maximum Ratings 31 DM6581/82 DM6581/82 DC Electrical Characteristics 31 DM6581/82 DM6581/82 AC Electrical Characteristics & Timing Waveforms 31 Chip 3: DM6580 DM6580 Analog Front End 26 26 26 27 28 29 29 29 29 29 DM6580 DM6580 Description DM6580 DM6580 Block Diagram DM6580 DM6580 Features DM6580 DM6580 Pin Configuration DM6580 DM6580 Pin Description DM6580 DM6580 Functional Description DM6580 DM6580 Absolute Maximum Ratings DM6580 DM6580 DC Electrical Characteristics DM6580 DM6580 AC Electrical Characteristics & Timing Waveforms DM6580 DM6580 Performance 33 33 34 34 35 35 37 37 Package Information 24 Chip 2: DM6581 DM6581 ITU-T V.90 TX DSP Chip 3: DM6582 DM6582 ITU-T V.90 RX DSP DM6581/82 DM6581/82 Description DM6581/82 DM6581/82 Block Diagram DM6581/82 DM6581/82 Features DM6581/82 DM6581/82 Pin Configuration DM6581/82 DM6581/82 Pin Description DM6581/82 DM6581/82 Functional Description 1. System Clock 2. DSP Clock 3. CODEC Clock 4. Serial Port 5. Dual Port RAM 6. Interrupt 7. CoProcessor 8. Power Down Mode 9. Eye Pattern Registers 39 Ordering Information 41 Disclaimer 41 Company Overview 41 Products 41 Contact Windows 41 Warning 41 38 38 Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set Features s Compatibility - ITU-T V.90 (56000 to 28000 bps) - ITU-T V.34 (33600 to 2400 bps) - CCITT V.32bis (14400, 12000, 9600, 7200, 4800bps) - CCITT V.32 (9600, 4800bps) - CCITT V.22bis (2400, 1200bps) - CCITT V.22 (1200bps) - CCITT V.23 (1200/75bps) - Bell 212A (1200bps) - Bell 103 (300bps) s - TIA/EIA 578 Fax Class 1 command set - TIA/EIA IS-101 IS-101 Voice command set s s s Video-phone modem interface V.80(Developing) V.8bis (Developing) Integrated UART 16550 s Parallel and Serial interfaces - 6, 7 and 8 bit character support - Even, odd, mark and none parity detection and generation - 1 and 2 stop bit support - Auto DTE data speed detection through "AT" s Caller identification (Caller ID) support s Speakerphone Fax - CCITT V.17 (14400, 12000, 7200bps) CCITT V.29 (9600, 7200bps) CCITT V.27ter (4800, 2400bps) CCITT V.21 Channel 2 (300bps) Group III, Class 1 s Selectable world wide call progress tone detection s 16 Bit over-sampling codec s Data Error Correction s - MNP Class 4 - CCITT V.42 LAPM Compromise and adaptive equalizer providing channel impairment compensation s Plug and Play (PnP) support Data Compression s Enhanced 8032 compatible micro-controller s Power Management (power down mode) s 8 selectable interrupts s Access up to 256K bytes external program memory s Access up to 64K bytes external data memory s NVRAM to store two user configurable, selectable profiles with three programmable telephone numbers s Full duplex data mode test capabilities - Analog loop test s - MNP Class5 - CCITT V.42bis s Voice compression - 2 and 4 bit ADPCM - IMA ADPCM (Developing) - 8 Bit PCM s DTE Interface - DTE speed up to 115200bps s Enhanced AT command set and S registers - TIA/EIA 602, ITU V.25 ter AT command set. Chipset The DM560P DM560P integrated modem device set contains 4 VLSI devices as described below: 1. DM6583 DM6583 Modem Controller Unit with PnP for ISA 2. DM6580 DM6580 Analog Front End (AFE) 3. DM6581 DM6581 ITU-T V.90 Transmit Digital Signal Processor (TX DSP) 4. DM6582 DM6582 ITU-T V.90 Receive Digital Signal Processor (RX DSP) Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 3 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set Chip 1: Modem Controller Unit with PnP for ISA The DM6583 DM6583 MCU performs general modem control DM6583 DM6583 Description functions, and is also designed to provide Plug and Play capability for ISA bus systems. The Plug and Play logic supports software or automatic Plug and Play selectable I/Os to allow users to configure the internal modem card without jumpers. The DM6583 DM6583 Modem Control Unit is designed for use in high speed internal and external modem applications. The DM6583 DM6583 interface is compatible with the DM6581/DM6582 DM6581/DM6582 Transmit and Receive Digital Signal Processors. The DM6583 DM6583 incorporates a 80C32 80C32 micro-controller, a virtual 16550A UART with FIFO mode, and Plug & Play control logic. DM6583 DM6583 Block Diagram Mode Selection PC Data Bus PC Address Bus PnP Control Logic Virtual 16550 UART External ROM, RAM Interface I/O Control Logic IRQ & R/W Control 8032 Micro-Controller Modem Control Interface RS 232 Interface DM6583 DM6583 Features · · · · · · · 4 Control interface support Supports parallel and serial interfaces Includes a 80C32 80C32 micro-controller 256K bytes maximum external program memory 64K bytes maximum external data memory Provides automatic Plug and Play or software configuration capabilities 8 selectable Interrupts · · Conflict free I/O base address selection Virtual 16550A UART compatible parallel interface · Fully programmable serial interface: - 6, 7 or 8-bit characters - Even, odd, mark and none parity bit generation and detection - 1 and 2 stop bit generation - Baud rate generation - Includes I/O control logic for modem control interface Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set Voice Sel1 /POR RXRCLK TXRCLK 88 87 86 D3 voice sel2 89 D2 A12 90 81 A13 91 D1 A14 92 82 A15 93 83 /PNPEN 94 GND GND 95 D0 /TUCS 96 84 PS1 97 85 EXT/INTB 98 V DD 100 99 DM6583 DM6583 Pin Configuration UD0 1 80 D4 UD1 2 79 D5 UD2 3 78 D6 UD3 4 77 D7 UD4 5 76 CA0 UD5 6 75 CA1 UD6 7 74 CA2 UD7 8 73 CA3 /IOR 9 72 CA4 GND 10 71 CA5 /IOW 11 70 CA6 /AEN 12 69 CA7 A11 13 68 GND A10 14 67 CA8 A9 15 66 CA9 A8 16 65 CA10 DM6583 DM6583 Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 50 /LCS EEROM3 51 49 30 48 V DD RESET EEPROM2 52 EEPROM1 29 47 RXD IRQ10 IRQ10 /VOICE 53 46 28 /OH TXD IRQ7 45 54 /DTR 27 44 ALE/P IRQ5 /RI 55 43 26 T1 /PSEN IRQ4 42 56 T0 25 41 /WR V DD GND 57 40 24 CA16 /RD A0 39 58 /RUCS 23 38 IRQ3 A1 CA17 CA15 59 37 60 22 /PWR 21 A2 36 A3 V DD CA14 35 61 IRQ15 IRQ15 20 34 CA13 A4 IRQ12 IRQ12 62 33 19 IRQ11 IRQ11 CA12 A5 32 CA11 63 31 64 18 XTAL2 17 XTAL1 A7 A6 5 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set DM6583 DM6583 Pin Description Pin No. 1-8 I/O I/O 9 /IOR I 10, 41, 68, 85, 96 11 GND P /IOW I 12 /AEN I 13 - 24 A11 - A0 I 25, 36, 52, 100 26, 27, 28, 29, 33, 34, 35, 59 VDD P IRQ4, IRQ5, IRQ7, IRQ10 IRQ10, IRQ11 IRQ11, IRQ12 IRQ12, IRQ15 IRQ15, IRQ3 O 30 RESET I 31 32 37 XTAL1 XTAL2 /PWR I O O 51 /LCS I 39 /RUCS O 40,38 CA16,CA17 O 42 6 Pin Name UD0 - UD7 T0 I Description Data Bus Signal, for internal modem: These signals are connected to the data bus of the PC I/O. They are used to transfer data between the PC and the DM6583 DM6583. Modem Control Output, for external modem: Memory address mapping of the controller is E800H E800H. I/O Read: An active low input signal used to read data from the DM6583 DM6583. Ground I/O Write: An active low input signal used to write data to the DM6583 DM6583. Address Enable: This is an active low signal to enable the system address for DM6583 DM6583. System Address: These signals are connected to the bus of PC I/O. They are used to select DM6583 DM6583 I/O ports. A0~A7:Modem Control Input for external modem. Memory address mapping of the controller is E800H E800H. +5V Power Supply Interrupt Request: These are the interrupt request pins. Only one pin, which is decoded from Configuration Register can be active. The active pin will go high when an interrupt request is generated from the DM6583 DM6583. Reset: An active high signal used to reset the DM6583 DM6583. Crystal Oscillator Input Crystal Oscillator Output Controller Program Write Enable: This pin is used to enable FLASH ROM programming. In configurations with no FLASH memory, this pin is not connected. Loop Current Detection. Modem Input Control: This pin is mapped to bit0 of address D000H D000H. RX DSP Register Select Output: Memory address mapping of the controller is E400H E400H. Bank Switch Control: These signals are used to switch external program memory between banks. CA16 CA17 Bank 0 0 0 Bank 1 1 0 Bank 2 0 1 Bank 3 1 1 Controller Counter 0 Input Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set DM6583 DM6583 Pin Description (continued) Pin No. 43 44 45 46 47 Pin Name T1 /RI /DTR /OH /VOICE I/O I I I O O 48-50 53 54 55 EEPROM 1-3 RXD TXD ALE/P I/O I O O 56 /PSEN O 57 58 60 - 67 69 - 76 77 - 84 86 87 88 89, 90 O O O O I/O I I O O 91 - 94 /WR /RD CA15 - CA8 CA7 - CA0 D7 - D0 TXRCLK RXRCLK /POR VOICE Se1 1 VOICE Se1 2 A12 - A15 95 /PNPEN I 97 /TUCS O 98 PS1 O 99 EXT/INTB I Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 I Description Controller Counter 1 Input Ring Signal Input DTR Input Pin (P1.1) Hook Relay Control (P1.2) Voice Relay Control. Modem Control Output (memory map is bit 3 of DAA) EEPROM Control Pins (P1.4-P1.6) Controller Serial Port Data Input Controller Serial Port Data Output Controller Address Latch Enable: Output pulse for latching the low byte of the address during accesses to the external memory. Controller Program Store Enable: This output goes low during a fetch from external program memory. Controller External Data Memory Write Control Controller External Data Memory Read Control Controller Address Bus Controller Address Bus Controller Data Bus Transmitter Baud Rate Clock Input (Controller INT 0) Receiver Baud Rate Clock Input (Controller INT 1) DSP Reset Output Modem Control Output (Memory map is bit 1-2 of DAA at memory address D000H D000H) System Address: These signals are connected to the bus of the PC I/O. They are used to select the DM6583 DM6583 I/O ports. PnP Mode Enable: This pin selects PnP mode. When connected to ground, the DM6583 DM6583 will enter PnP mode when it receives the PnP initiation key sequence. When disconnected, an internal pull up will disable the Plug and Play function. TX DSP Register Select Output: Memory address mapping of the controller is F000H F000H. Modem Control Port Select Output: Memory address mapping of the controller is D800H D800H. Select Pin: Used to select internal or external operation. 0: internal modem 1: external modem 7 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set DM6583 DM6583 Functional Description Micro-controller Power Down Mode 1. Operating Mode Selection An instruction that sets the register PD (PCON.1) will cause the 80C32 80C32 to enter power down mode. There are three ways to wake up the 80C32 80C32 (1) Positive pulse signal occurring at the reset pin of the 80C32 80C32 (2) Negative pulse occurring at /RI (P1.0) of the 80C32 80C32 (3) Programming the PnP Wake Up Controller Register. The DM6583 DM6583 MCU can be used in both internal and external modem applications. When operating as an internal modem, the EXT/INTB input (pin 99) must be attached to ground. When the DM6583 DM6583 is operating as an external modem, the EXT/INTB input (pin 99) must attached to VDD. 2. Micro-controller Program Memory The DM6583 DM6583 supports two bank switch control pins to switch external program memory among four banks. The DM6583 DM6583 can access a total of 256K of external program memory. Address mapping: bank0: 00000H 00000H - 0FFFFH bank1: 10000H 10000H - 1FFFFH bank2: 20000H 20000H - 2FFFFH bank3: 30000H 30000H - 3FFFFH For bank switching, three instructions must be included in software. Enhanced Internal direct Memory Switch to bank1: CLR P1.3 SETB P1.7 JMP BANK 1 ADDRESS By setting 8F.2H the system can switch program and data memory. If the system uses FLASH memory as program memory this function is used to reflash program code by downloading the program to data memory then switching them. Switch to bank2: CLR P1.7 SETB P1.3 JMP BANK 2 ADDRESS Example: SETB LJMP Switch to bank3: CLR P1.7 CLR P1.3 JMP BANK 3 ADDRESS Return to bank 0: SETB P1.7 SETB P1.3 JMP BANK 0 ADDRESS There are two 128 byte banks of internal direct memory in the 80C32 80C32. The system uses the lower 128 bytes under normal conditions. Switching to the upper bank is achieved by loading register 8FH.1 (SFR of the 80C32 80C32) with 1. Switching to the lower bank can be achieved by loading the same register with 0. Reflash Program Memory 8FH.2 0000H 0000H 3. Micro-controller Register Description UART Clock Register: Address D4000H D4000H Reset State: 06H Write Only bit7 X bit6 bit5 bit4 bit3 bit2 Bit1 dat6 dat5 dat4 dat3 dat2 dat1 bit0 0 * For detailed information about the micro-controller, refer to the Programmer's Guide to 8032. 8 Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set UART Clock Modem Output Port Register: Address D000H D000H The internal clock of the virtual UART logic is fixed at 1.8432MHz. The clock is derived from the MSCLK signal from the DM6582 DM6582 DSP, or an external 30Mhz crystal. The UART 1.8432MHz clock will be obtained by division. When the operating frequency of the DM6583 DM6583 controller changes, the divider should be changed accordingly. This divider is specified by the Configuration Register which can be written by the DM6583 DM6583 controller. The address mapping of the register is D400H D400H: (DM6583 DM6583 controller memory mapping) Write only bit7 bit6 Bit 0: Always 0. Bit 6-1: define the clock divider range from 2 to 64 (even number). Bit 7: Not used. UART Baud Generator Divisor Latch Register: Address EC00H EC00H Read only bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 By reading this register, the micro-controller can monitor the value of the low byte divisor latch of the virtual UART baud generator (see DLL in next section) and determine the baud rate clock itself. Modem Status Control Register (MSCR): Address E000H E000H Write only bit7 bit6 0 0 bit5 0 bit4 0 bit3 bit2 bit1 /CTS /DSR /DCD bit0 /RI This register contains information about the line status of the modem. The available signals are Ring Detect (/RI), Carrier Detect (/DCD), Data Set Ready (/DSR) and Clear To Send (/CTS). Final Version: DM560P-DS-F01 DM560P-DS-F01 October 5, 2000 bit5 bit4 bit3 bit2 bit1 bit0 /Voice Voice Voice /POR -sel2 -Sel1 These 4 bits control the DM6583 DM6583 output ports. PnP Isolation & Resource Data Port: Address F800H F800H Write only The PnP isolation and resource data can be bytesequentially written to the corresponding memory through this register. Auto-configuration Register: Address F400H F400H bit2 bit1 bit0 IRQ bit5 bit4 bit3 I/O 0 0 0 3 0 0 0 03F8-03FF 03F8-03FF(COM1) 0 0 1 4 0 0 1 02F8-02FF 02F8-02FF(COM2) 0 1 0 5 0 1 0 03E8-03EF 03E8-03EF(COM3) 0 1 1 7 0 1 1 02E8-02EF 02E8-02EF(COM4) 1 0 0 10 1 0 0 03F0-03F7 03F0-03F7(COM5) 1 0 1 11 1 0 1 02F0-02F7 02F0-02F7(COM6) 1 1 0 12 1 1 0 03E0-03E7 03E0-03E7(COM7) 1 1 1 15 1 1 1 02E0-02E7 02E0-02E7(COM8) The default I/O base and IRQ data stored in 93C46 93C46 is loaded to this register by the micro-controller. The micro-controller can also get the current I/O base and IRQ information settings by performing a read from this register. The configuration determined by this register will be disabled when the register detects the Initiation Key described in the next section. Bit 6: This bit is set to inform micro-controller that the current I/O base and IRQ data should be stored to 93C46 93C46 as the default setting for the next power-on reset through programming the Auto-configuration Register. This bit will be cleared by micro-controller. Bit 7: When bit 7 is set, it enables the hardware configuration to be set according to bit 0-bit 5 (Jumperless mode) and loads the proper value into the PnP Registers including I/O and Interrupt Configuration Registers. This bit will be reset, when it receives PnP Initiation Key sequence. 9 DM560P DM560P V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set Auto-configuration Register: Address F400H F400H (continued) * When a reset condition occurs, the I/O and Interrupt configuration registers must be reset to the default value according to bit 0 - bit 5. RxDataBits Register: Address DC00H DC00H Write only Once the RxDataBit set to 1, the data in the RxBuffer will be transferred to RxFIFO. The transfer bit number is the same as the programming value of RxDataBits Register. RxBuffer: Address DC01H DC01H Write only Receive data will be written to the RxBuffer and will be input to the RxHDLC circuit. The RxBuffer is 16 bytes wide. RxFIFO: Address DC01H DC01H Read only After the data has been passed from the RxBuffer to the RxHDLC circuit, the RxHDLC circuit will remove the 7eH patterns and transfer the results to the RxFIFO. There RxFIFO is 21 bytes wide. TxDataBits Register: Address DC02H DC02H Write only Data written to TxDataBits will be presented to the TxFIFO. The data in TxFIFO will be transferred to TXHDLC circuit. The transfer bit number is the same as the value of TxDataBits register. If the TxFIFO is empty, a 7e pattern will be loaded to the TxFIFO. If TxFIFO is not empty and the data frame has the pattern of five consecutive "1" , then the TXHDLC circuit will insert "0" automatically. TxFIFO Register: Address DC03H DC03H Write only The original HDLC frame data will be loaded to the TxFIFO, presented to the input of the TxHDLC circuit. The TxFIFO is 21 bytes wide. TxBuffer: Address DC03H DC03H Read only According to TxDataBits, the TxHDLC circuit will transfer the same number data bits to the TxBuffer. The TxBuffer is 16 bytes wide. 10 HDLC CNTL/STATUS Register: Address DC04H DC04H Bit0: TxReady0 0: indicates the data in the TxFIFO has deceased to zero and the HDLC circuit has transferred the 1st 7eH pattern. 1: indicates that the TxFIFO data is greater than or equal to the threshold value. Bit1: Rxdata 0: all the data in the RxBuffer has been read. 1: Programed by software to indicate that all data in the RxDataBits register has been written to the RxBuffer. Bit2: TxFIFO Threshold 0: TxFIFO threshold No. = 11 1: TxFIFO threshold No. = 16 Bit3: TxFIFO Status 0: data No. in TxFIFO >= threshold 1: data No. in TxFIFO