AN2116 uPSD3300 DK3300-ELCD AN1943 AN2116/0405 DK3300 UPSD3300 uPSD33xx AI08875 - Datasheet Archive

 

APPLICATION NOTE uPSD3300 Series Design Guide for DK3300-ELCD Using RIDE INTRODUCTION This application note is based upon AN1943

 

AN2116 AN2116 APPLICATION NOTE uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE INTRODUCTION This application note is based upon AN1943 AN1943 and has been updated for the DK3300-ELCD DK3300-ELCD Development Kit and, in addition, this document focuses on the use of the DK3300-ELCD DK3300-ELCD with RIDE Tools. It provides guidelines for the creation and development of applications for the Turbo uPSD Family of devices and shows a number of key steps to follow for creating a design based on the DK3300-ELCD DK3300-ELCD Development Kit. The Kit has all the requirements for using the sample code and examples supplied. Here, the basic flow is provided for creating a project using the Raisonance Integrated Development Environment (RIDE) tools. A simple application included in the Kit is demonstrated using RIDE and shows the key features of RIDE. The key steps in designing an application are enumerated in this document. PSDsoft, a key tool in using Turbo uPSD, is explained in detail by illustrating the Design used for the demonstration section. PSDsoft has been upgraded to connect to ST's JTAG programming cable (FlashLINK) or Raisonance's JTAG programming cable (RLINK-ST) As shown in Figure 1, the uPSD3300 uPSD3300 family is a series of 8051-class microcontrollers (MCUs) containing a new fast Turbo 8032 core with a large dual-bank flash memory, a large SRAM, many peripherals, programmable logic, and JTAG In-System Programming (ISP). It is important to make the correct selection in PSDsoft, using the HW Setup configuration menu. Please see the uPSD on-line resources page for latest documentation and other referenced User guides and Application notes at the URL listed below. Rev. 1.1 AN2116/0405 AN2116/0405 1/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE TABLE OF CONTENTS IINTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 uPSD3300 uPSD3300 FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 uPSD3300 uPSD3300 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 DK3300-ELCD DK3300-ELCD DEVELOPMENT KIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Contents of DK3300 DK3300 Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 PROJECT CREATION AND SAMPLE DESIGN DEVELOPMENT PROCESS. . . . . . . . . . . . . . . . 10 3.1 Key Design Development Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Software Installation and Connections: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.2 Physical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.3 Installing RIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.4 RLINK-ST (USB /JTAG dongle) Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 USING RIDE AND RLINK-ST FOR CREATING A NEW PROJECT . . . . . . . . . . . . . . . . . . . . . . . . 13 5 SAMPLE DESIGN AND DEMONSTRATION CODE FOR RIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Compile Project and Program Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Single-Step and Source-Level Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Device Specific Formatted Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Symbolic Debugging and Variables Watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Code Iteration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Instruction Tracing, near Real-Time Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 SAMPLE DESIGN EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 ENTERING DESIGN IN PSDsoft EXPRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 2/83 1 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chip-Select Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 User-Defined Node Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Additional uPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Fitting Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Merging 8032 Firmware with uPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 7.9 JTAG Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.10Watch It Run On DK3300-ELCD DK3300-ELCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 APPENDIX A.DK3300-ELCD DK3300-ELCD JUMPERS SELECTION AND DEFAULTS . . . . . . . . . . . . . . . . . . . . . . 64 APPENDIX B.INTERFACE DISPLAY WINDOWS AND CODE VIEW . . . . . . . . . . . . . . . . . . . . . . . . . 65 APPENDIX C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Importing an external application into RIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Importing a Keil Project into RIDE for Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Running the application on the target hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Specifying the PSDsoft Express INI file information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Executing simple commands such as Erase, Program and Blank-Check. . . . . . . . . . . . . . . . 72 Debugging the application on the hardware target from RIDE . . . . . . . . . . . . . . . . . . . . . . . . . 73 APPENDIX D.PSDSOFT REPORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Project.frp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Project.sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 1 UPSD3300 UPSD3300 FAMILY Figure 1. General Block Diagram of the uPSD33xx uPSD33xx uPSD33xx uPSD33xx (3) 16-bit Timer/ Counters (2) External Interrupts P3.0:7 Turbo 8032 Core PFQ & BC Programmable Decode and Page Logic I2C 1st Flash Memory: 64K, 128K, or 256K Bytes 2nd Flash Memory: 16K or 32K Bytes SRAM: 2K, 8K, or 32K Bytes UART0 (8) GPIO, Port A (80-pin only) P1.0:7 (8) GPIO, Port 1 (8) 10-bit ADC Optional IrDA Encoder/Decoder UART1 SYSTEM BUS (8) GPIO, Port 3 General Purpose Programmable Logic, 16 Macrocells PA0:7 (8) GPIO, Port B PB0:7 (2) GPIO, Port D PD1:2 (4) GPIO, Port C PC0:7 JTAG ICE and ISP SPI 16-bit PCA (6) PWM, CAPCOM, TIMER P4.0:7 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset (8) GPIO, Port 4 VCC, VDD, GND, Reset, Crystal In MCU Bus Dedicated Pins AI08875 AI08875 4/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 1.1 uPSD3300 uPSD3300 Family Overview The uPSD3300 uPSD3300 family is a turbo 4-clock per instruction 8032 MCU capable of being clocked up to 40MHz at 3.3V or 5.0V at industrial operating temperature range. Currently there are twelve family members that contain different combinations of flash memory size, operating voltage, and packaging (please see the full datasheet). In this Application Note, uPSD3334D40U6 uPSD3334D40U6 is used as the example. The term "Turbo uPSD" is used throughout the remainder of the document for brevity (see the Turbo uPSD3334 uPSD3334 block diagram shown in Figure 2). The Turbo uPSD family has a unique memory structure that includes two independent flash memory arrays (Main and Secondary) capable of read-while-write operation. This is ideal for In-Application Programming (IAP) because the 8032 can fetch instructions from one flash array while erasing/writing the other array. Individual sectors of each flash memory array can be mapped to virtually any 8032 address by the Decode PLD (DPLD) for total flexibility. The Turbo uPSD also contains a Page Register whose outputs feed the inputs of the DPLD. This allows paging (or banking) of flash memory to break the 8032's inherent limit of 64 Kbyte addresses. The 8032 may write to the Page Register at runtime. For more complex designs, the Turbo uPSD is capable of placing each of the flash memory arrays (Main or Secondary) into 8032 code address space, into 8032 data space, or into both code and data space on the fly. Mapping flexibility like this supports IAP because either flash array may be temporarily placed into data space while the firmware is updated, then moved back into code space when finished, all under control of the 8032. Many peripherals are available in this Turbo uPSD, including: two UART channels, one IrDA channel, one SPI channel, one I2C channel, six PWM channels, eight 10-bit ADC channels, nine Timer/Counters, a watchdog timer, low-VCC detection with reset-out, a general purpose PLD, many GPIO and a USB-JTAG Debugger. All of the peripherals on Ports 1, 3, and 4 are controlled using 8032 Special Function Registers (SFRs). I/O Signals on ports A, B, C, and D are controlled one of two ways: 1. by a block of xdata memory mapped control registers, whose base address (csiop) can be mapped anywhere using the DPLD; and 2. by the programmable logic. In addition, Turbo uPSD offers a Cross-Bar I/O, which means that Peripheral functions on Port 1 are also available on Port 4 (cross-bar switch), providing more flexibility. There is no need to sacrifice one peripheral function when two functions are available on a single pin, just use the other port. The JTAG channel on Port C is used for ISP and debug of the 8032 MCU core. ISP is ideal for rapid code iterations during firmware development and for Just-In-Time inventory management during manufacturing. JTAG ISP eliminates the need for sockets and pre-programmed devices, and requires no participation of the 8032. JTAG debug eliminates the need for expensive and intrusive hardware In-Circuit Emulator (ICE). 5/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 2. uPSD3334D uPSD3334D Block Diagram Turbo PSD33XX PSD33XX Turbo 8032 MCU (7) Vcc and GND Divide or Pass 256 byte SRAM/SFRs (2) Crystal Connection (1) Reference Voltage Input (80-pin only) Port 1: Available Functions (8) 10-bit ADC SPI (8) GPIO (2) 8032 Timer 2 (2) UART1 - IrDA (4) SPI UART1 w/IrDA (3) 16-bit Timer/Cntrs Port 3: Available Functions UART0 (8) GPIO 8032 Interrupts Local MCU Bus (8) ADC (These 8 signals are alternately avalable on Port 4) I2C PCA: (6) 16-bit Timer/ Counter Units. CAPCOM, PWM (2) 8032 Timer 1 (2) UART0 (2) Interrupts (2) I2C Port 4: Available Functions (8) GPIO 10mA (2) PCA Clk Inputs (2) 8032 Timer 2 (6) PCA: PWM / (2) UART1 - IrDA CAPCOM (4) SPI (8) 8032 Data/Lo Addr (8) MCU AD0-AD7 (80-pin Pkg Only) (4) 8032 Hi Address (4) MCU A8-A11 A8-A11 (80-pin Pkg Only) Supervisor, WDT/LVD (1) Reset Input System Reset Port C: Available Functions JTAG Debug and ISP Memory Interface with Prefetch & Branch Cache Memory Bus General PLD, 16 Macrocel Main Flash: 64K / 128K / 256K bytes 2nd Flash: 16 / 32K bytes Decode PLD & Page Logic 1 (2) Extended JTAG (2) SRAM Batt B/U Port A: Available Functions (80-pin Only) (8) GPIO (8) PLD I/O Port B: Available Functions Sector Selects (8) GPIO (8) PLD I/O SRAM: 2K / 8K / 32K bytes 256 Control Registers 6/83 (4) GPIO (4) Dedicated JTAG Port D: Available Functions (2) GPIO - 80-pin (1) GPIO - 52-pin (2) Chip-selects - 80-pin (1) Chip-select - 52-pin uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 2 DK3300-ELCD DK3300-ELCD DEVELOPMENT KIT 2.1 Overview A picture of the DK3300-ELCD DK3300-ELCD board, including the important connections, is shown in Figure 3. A list of jumpers JP0 - JP16 and their functions can be found on the DK3300-ELCD DK3300-ELCD board's silk screen. For more detailed information on these jumpers, please refer to APPENDIX A., DK3300-ELCD DK3300-ELCD JUMPERS SELECTION AND DEFAULTS or the DK3300-ELCD DK3300-ELCD User's Guide. Board layout and schematics are available. Connectors CON1, CON2, and CON3 provide easy access to all Turbo uPSD signals for expansion or testing. UARTs are available on connectors marked UART0 and UART1. The FlashLINK/ RLINK-ST/ ULINK JTAG ISP cable connects at the connector, JTAG. The DK3300-ELCD DK3300-ELCD has a graphical LCD interface and a fully-featured real-time clock with a back-up battery, a serial EEPROM, IrDA transceiver, PWM giving control over the LCD brightness, and a rotary encoder knob for selection of various demo applications. Board layout and schematics are available. The sample design example code used for this application note is a RIDE based project which shows use of the PWM and ADC function blocks within the uPSD3300 uPSD3300 device. A pulse width modulated signal output from the PWM circuit is tied to an RC circuit resulting in a DC voltage that is proportional to the pulse width. This DC voltage is input to an ADC channel and is read after each time the pulse width out of the PWM is changed. The PWM setting and the ADC value read is displayed on the LCD. The purpose of using this simple design project is to illustrate and demonstrate the use of Raisonance RIDE software and tools with the RLINK-ST adapter on a uPSD development board. The RIDE tools provide many features for editing, compiling, programming, and debugging a uPSD3300 uPSD3300 MCU Series from STMicroelectronics. In the following sections, some of the main features are described to give you a feel for the simplicity and capabilities of the tools used for this sample design. A brief overview to the methods involved in importing applications developed with the Keil compiler and debugging on DK3300-ELCD DK3300-ELCD using Ride Debugger is also provided in the appendices of this document. 7/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 3. DK3300-ELCD DK3300-ELCD Development Board Components Expansion Connectors IRDA Transceiver uPSD3334 uPSD3334 14-pin JTAG Connector JTAG LED Tamper Detect Switches Real Time Clock SPI Flash Reset Switch RS232 RS232 Connectors New Graphic LCD Display Rotary Encoder Switches and LEDs 8/83 1 9V DC Power Input On/Off Switch and Power LED PS/2 Keyboard connector and LEDs uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 2.2 Contents of DK3300 DK3300 Kit STMicroelectronics provides a DK3300-ELCD DK3300-ELCD Development Kit which is shipped with the following contents: ­ Circuit Board: uPSD DK3300-ELCD DK3300-ELCD Development Board- with a uPSD3334D-40U6 uPSD3334D-40U6 MCU with Enhanced Graphic LCD RLINK-ST, a USB-based JTAG adapter from Raisonance for debugging with Raisonance Integrated Development Environment (RIDE) ULINK, a USB-based JTAG adapter from Keil for debugging with Keil's uVision Tools USB Cables and RS232 RS232 Cables 110/220V 110/220V Universal Power Supply Adapter ­ Software and Tools CD's: RKit Development Suite CD from Raisonance contains: ­ ­ RIDE Debugger Utility (no code size limit) ­ uPSD3300 uPSD3300 sample projects and Application Note ­ ­ RIDE C-Compiler and Assembler (limited to 4 Kbytes code size) Also includes ST's PSDsoft Express software for configuring the Programmable Logic inside the uPSD3300 uPSD3300 DK3300-ELCD DK3300-ELCD CD from STMicroelectronics contains: ­ STMicroelectronics Datasheets, Tools, Software, uPSD3300 uPSD3300 sample projects ­ User Manual and Application Notes ­ Keil uVision 2 Software and support Tools ( Demo Version) for uPSD - (Limited to 2 Kbytes code size) Note: This Application Note assumes that you have access to the Development Kit and software tools. 9/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 3 PROJECT CREATION AND SAMPLE DESIGN DEVELOPMENT PROCESS In the sections below you will be introduced to the process of using RIDE for creating application Code using the Development board and the associated tools supplied with the Kit. The key steps for creating a new project with RIDE are described. This is followed by section that uses the RIDE environment and DK3300-ELCD DK3300-ELCD board to demonstrate the sample design. The main features of RIDE and its usage are then shown by loading and debugging the sample application. This way you gain familiarity with the board and the development to design your own applications. The unique feature of Turbo uPSD requires understanding of PSDsoft Express tool from STMicroelectronics. Any Turbo uPSD-based design requires having a good understanding and features of this tool. Following a detailed description of the process and features of PSDsoft used in this simple design, the design block diagram and the memory map are then explained where PSDsoft is used to set up set up the various components, interfaces and the programmable logic. 3.1 Key Design Development Steps Design and development of applications using Turbo uPSD Family of products require use of both Development Boards from STMicroelectronics or hardware developed by the user in conjunction with Software and Tools that support uPSD Devices. It is important to follow some simple steps and guidelines for successful implementation of the project. STMicroelectronics provides full support with Hardware Development Kits and Software Tools, utilities and support through the Support Website. The key design development steps for using RIDE tools are as follows: Identify and select the right development Kits and Tools Design a Block Diagram of your Application in relation to the Turbo uPSD Design the Logic and connections to be used for the PLD available in uPSD Create Memory Maps and inputs for programming devices using PSDsoft Express tools Develop your application Code for the chosen Compiler (the Raisonance 8051 C Compiler is used here) Verify the project needs and match with the device used Compile and create the firmware and applications Code Enter data from the Block diagram and memory maps using PSDsoft Express Design flow Merge MCU and PSDsoft project to get the object file Flash the Code and Data using Tools including JTAG - ISP ( RLINK-ST / Flashlink) Debug, make changes, reprogram and finalize the project Test and qualify the design This application note provides guidelines for design by showing the key steps as mentioned above. The document has been divided into sections that cover various areas. It is expected 10/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE that the reader has previous experience of programming and applications development including the use of compilers. First, an introduction to the Turbo uPSD. The family basic block diagram and features are introduced, followed by an overview of the DK3300-ELCD DK3300-ELCD Development Kit (Board). This hardware is used with the RIDE Tools to demonstrate ideas for project creation and design development. A simple example is used for demonstration and explained in detail to provide an understanding of the RIDE tools and the DK3300-ELCD DK3300-ELCD Development Kit. It is hoped that with this information and other supporting documents available from STMicroelectronics, you can design and develop your application/project using Turbo uPSD. 3.2 Requirements In order to follow the examples and processes described here you will need a DK3300-ELCD DK3300-ELCD Development Kit as described above (Refer to section 2.2, Contents of DK3300 DK3300 Kit). Note: The DK3300-ELCD DK3300-ELCD Development Kit meets all the requirements for use in the example described here. To use RLINK-ST, you will need a USB port and a Windows Operating System supporting the USB (Win98SE, Win2000, Me, XP). RLINK-ST is a Full-Speed device (12Mbit/s). It is delivered with a standard USB cable. Note: Win95, Win98 First Edition and NT4.0 do NOT support USB. IMPORTANT: You must install PSDsoft Express 8.10 or later to have the capability to program a uPSD device. For more information on how to use all the features of RIDE please see Ride.pdf (available in the directory Ride\Doc or by selecting Help | PDF | RIDE General | RIDE). 3.3 Software Installation and Connections: 3.3.1 Software Installation Insert the Raisonance disc supplied with DK3300-ELCD DK3300-ELCD Development Kit in your CD drive. The auto-run will bring up the program installation menu. First Install PSDsoft Express, taking all the default choices. Next install RIDE, taking all the default choices. Remove the Raisonance Disc and then insert the DK3300-ELCD DK3300-ELCD Disc from STMicroelectronics in the CD drive. Navigate the screens and bring up Menu page with "Copy Device Drivers and Demo Code". Click on it and then: Unzip the file pointing to C:\ root directory in your drive. 11/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 3.3.2 Physical Connections Connect RLINK-ST to your PC/Laptop using the supplied USB cable and let the USB driver install on Windows. Connect RLINK-ST ribbon cable to the JTAG connector on the DK3300-ELCD DK3300-ELCD circuit board. Make sure that the Board is powered up using the Universal Adapter supplied with the kit and ensure that it is functioning. (See that the LCD display shows the text). Make sure that the Jumpers are set correctly. (Refer to APPENDIX A. at the end of the document for Jumper settings). 3.3.3 Installing RIDE Note: the RIDE software must be installed before connecting the RLINK-ST dongle for the first time. The "RKit-Installation" program (INSTALL.EXE) installs all the necessary files and correctly configures the environment for running RIDE. You can install the kit from CD-ROM or from a network. The files on the distribution disc are compressed and so the installation program both uncompresses and copies them to your hard disk. Before installing RIDE, make sure that your computer meets the minimum system and close any other running applications. The "README.TXT" file, contains important information about the installation procedure. 3.3.4 RLINK-ST (USB /JTAG dongle) Installation To install the RLINK-ST driver, you must proceed as follows: 1. Install RIDE and make sure that you instruct it to install the RLink driver. 2. Plug the Raisonance RLINK-ST into a USB connector. When the RLINK-ST Device is connected all the LED must be ON. Then the BUSY LED should shift OFF after a second. This verifies that the device is correctly connected and recognized by the PC. 3. On Windows 98SE or Millenium, the first time you connect your RLINK-ST dongle to your computer, your Windows system will pop-up a "Detect New Hardware" window: ­ Select 'Search for a suitable driver for my device' then 'Locate Driver Files - Specify a location'. Select the file RLINKDRV_WDP.INF located into the Ride\driver\RLinkDrv directory. 12/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 4 USING RIDE AND RLINK-ST FOR CREATING A NEW PROJECT In this section the key steps for using RIDE to create a new project are shown. It is assumed that you have knowledge of basic operations of the Tools being used. 1. As shown in the section 3.1, Key Design Development Steps, there are a number of recommended steps involved in creating a new uPSD project using the RIDE 8051 software development tool from Raisonance. Please also refer to the general Users Guide for RIDE (included on the RIDE CD). 2. Select "New" from the "Project" pulldown menu in RIDE and enter the project name, path, and family as shown below (Figure 4). In this example, the name "New_uPSD_project" is used. Figure 4. Entering New Project Name And Directory 3. Click "Next" and the uPSD device selection dialog appears (Figure 5). Select the correct uPSD device from within the ST folder. (Here, uPSD3334D-40 uPSD3334D-40 is selected as these are used in the ST Development boards DK3300-ELCD DK3300-ELCD) 13/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 5. Turbo uPSD Device selection 4. Click "Finish" and RIDE will create the new project copying the needed uPSD files into your project directory and RIDE will also automatically add the "startup.a51" and "uPSD_Init.c" files to your RIDE project folder. These files comprise the firmware that is executed by the 8032 upon a power-up or a reset event. It will also create a PSDsoft directory and copy a default project into the PSDsoft directory. This is reflected in the RIDE environment as shown in Figure 6 below. The created files and start up files are shown in the project window (circled in blue). 14/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 6. RIDE Environment RIDE will also generate a default PSDsoft project by creating a folder and the PSDsoft project files. This PSDsoft project will always be named "project.ini" and will reside in the folder named "PSDsoft". This new "PSDsoft" folder will always reside in your RIDE project folder. In this example, the path to the generated PSDsoft project is C:\RIDE\EXAMPLES\new_upsd_project\PSDsoft. There are certain settings in RIDE that depend on this structure so it is best not to change the name of the generated PSDsoft project or its path. This PSDsoft project is examined later in this document. 5. Now click "Make All" in RIDE (Figure 6) above. RIDE will generate the dependent header files that are specified within the "startup.a51" and "uPSD_Init.c" files. Header files for this example are "upsd3300.h", "uPSD3300 uPSD3300.inc", and "uPSD3300 uPSD3300_hardware.h". At this point, all the essential files for a new project have been created, and you just have to add your application specific code. These generated files are based on assumptions about common usage and this is a great place to start. However, if your system requirements are not met by these assumptions, these files must be edited. 15/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Two examples of editing to fit your system specification: 1. You'll need to edit the file "uPSD3300 uPSD3300_hardware.h" to change the definition for the variable "FREQ_OSC" if your system does not use a 40MHz crystal. 2. If you make any changes to the memory mapping in RIDE, you must also edit the PSDsoft project in the "Chip-Select Equation" section. For example, if in RIDE you move the starting address of XDATA, you must also change your PSDsoft project so the chip-select for the SRAM (rs0) matches the XDATA location that is specified in RIDE. It is very important that settings in RIDE match the configurations in PSDsoft. All the generated files for this example are shown below (Figure 7). Figure 7. New RIDE Project Files and folders Now that all the start up firmware and PSDsoft configurations are complete, you will need to create and add your own application C code to the RIDE project. In other words, create and compile your own "main.c" file and any dependent files referenced by "main.c". Also, be sure to add to your code the include statements that reference any header files created by RIDE. When you are ready to try your code, click "Make All" to compile and build the project, and generate a HEX file containing the 8032 firmware. This HEX file will be used to program the Flash memory sectors in the uPSD. Next, you must specify within PSDsoft the name and location of the HEX file that was just created by RIDE. PSDsoft needs to know the path to this HEX file so it can merge the 8032 firmware with the PLD and memory map equations to create one single file that is to be programmed into the uPSD device. To do this you must invoke PSDsoft and double click on the "Specify Project" box at the top of the PSDsoft Design Flow screen (Figure 8) 16/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 8. PSDsoft Express Design Flow You will get the Open Project Screen as shown below (Figure 9). Click on browse and now open the project that was created by RIDE. In this example, the name of the PSDsoft project is "project.ini" and the path C:\RIDE\Examples\New_upsd_project\PSDsoft. 17/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 9. PSDsoft Open Project Screen Once the project is open in PSDsoft, you can modify it to make use of the general purpose programmable logic or change the memory mapping. But remember, any changes to the memory mapping must match any memory specifications that you made in the RIDE project. As an example, click on the "Define Pin/Node Functions" box in the main PSDsoft flow diagram (shown in Figure 8). You'll see a pin definition screen pop up. Scroll down to the bottom of the right half of this screen and click "Next". Now you will see the Design Assistant screen. Click on the "Chip-Select Equation" tab for verifying design (Figure 10 below). 18/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 10. PSDsoft Design Assistant (Chip Select Equations) Screen There are 8 main Flash memory sectors (fs0-fs7), each 32 Kbytes in length; 4 secondary Flash memory sectors (csboot0-csboot3), each 8 Kbytes in length; 1 SRAM segment (rs0) which is 8 Kbytes long; and a group of 256 registers (csiop) used to control I/O ports and the PLD. You can click on each of these chip-select names to see where they are mapped. Refer to section 7, ENTERING DESIGN IN PSDsoft EXPRESS to see how the sample design is implemented in PSDsoft. Make sure that the physical memory chip-select equations all match the new RIDE example project. Now click "Done" to get back to the main Design flow diagram (Figure 8). Click the box "Fit Design to Silicon" and PSDsoft will generate all the configuration data based on the memory map choices and also produces a report. Close the report and you will see the main Design flow diagram again. Click the "Merge MCU Firmware" box. You will see a warning message stating that memory paging is used in this example so please be aware that several Flash memory segments reside in the same physical memory range, but on different pages. Just click "OK" and you'll see the screen shown in Figure 11 19/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 11. Merge MCU Firmware with PSDsoft You will find in this Merge screen (Figure 11) a place to specify a HEX file name for each and every segment of Flash memory (fs0-fs7 and csboot0-csboot3) by scrolling the slide bar on the right. Here is where you browse to assign a HEX firmware file to a Flash memory segment, and PSDsoft will take this input and create a single file to program into the uPSD using JTAG. It is your choice to specify the same HEX file name for all Flash memory segments, and PSDsoft will automatically extract from that file only the relevant portion for each segment. Alternatively, you can specify a different HEX file name for each segment. It just depends on how you build your project in RIDE. For this simple example, one HEX file name is specified to be assigned to the main Flash memory segment, fs0. In the screen shown above you will see the "Your Hex File Here" statement (circled in blue) on the line for fs0. Click the "Browse" button and point to the HEX file that is created by this example project . This assumes you have added your "main.c" to the RIDE project and have successfully compiled and generated a HEX file. Click "OK" on the Merge screen and a single file will be generated that can be used to program the uPSD over JTAG. After you have completed this task, you will not need to use PSDsoft again unless you want to change some configuration setting regarding the memory map, the general purpose PLD, or 20/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE other configurations in PSDsoft. But instead, you can stay in the RIDE environment from now on to edit, compile, and program the uPSD using the RLINK-ST JTAG/USB adaptor. Now return to RIDE and program the uPSD. RIDE is already configured with the location settings of the PSDsoft project files because it initially created them and the folder in which they reside. So to program the uPSD using RLINK-ST, you may go to a dedicated screen shown in Figure 11 or you can invoke the RLINK-ST Debugger. Figure 12. RIDE Title Bar Click on the "Debug" pull down menu in the RIDE Title bar (shown above) and select "Options" to get the Debugger Options screen shown below (Figure 13). 21/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 13. RIDE uPSD Debugger Options In the "Actions" area, make sure that the "Erase and Download" and "Merge PLD with Program code" and "Debug" boxes are all checked as shown in Figure 13 In the "JTAG Device Chain" area, you only need to click the "Custom Device Chain" if there is more than one uPSD device in the JTAG chain. Typically this is not the case, and "Single" is fine. In the "Merge Options" area, it is important that the PSDsoft project file is correctly specified. This is how RIDE calls PSDsoft in the background for JTAG programming. When you start a new project in RIDE, this path and the PSDsoft project name is automatically specified. But if for some reason you move the PSDsoft project or rename it, you must adjust this link to match. In the "Debug Options" area of Figure 13, you specify the base address of the uPSD CSIOP registers. This is needed for debugging a project that uses paged memory so the Debugger 22/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE can keep track of the active memory page number. By default, this address is set to 0x7F00 when you create a new project in RIDE and this matches the CSIOP address specified in the PSDsoft project that was created. But if you change CSIOP address in PSDsoft, you must change it in the option window shown in Figure 13, and you must also edit the file uPSD3300 uPSD3300_hardware.h and change the address definition of PSD_REG_ADDR to match. In the middle section of the screen, you can specify which portions of the uPSD will be affected by Program and Erase operations. The first time you program you must have "Erase Full Chip" and "Download Full Chip" selected. Afterwards you can select "Erase Flash Sectors" and "Download Flash Sectors" so that the PLD will not be erased and programmed, saving time. If any changes to PLD are made in PSDsoft, you will have to go back to "Full Chip" operations again. The "Instant Checks" area is where the USB/JTAG operations are tested and executed. Here you can run communication tests as well as Program and Erase operations. Once these settings of Figure 13 are made, each time the Debugger is started the uPSD will be erased/programmed as you have specified. To start the Debugger, click on the "Debug" button: Figure 14. Debug Button If this is the first time to run the debugger for this project, you will be presented with the following debug options (Figure 15). Figure 15. Debug Options Select the "Real Machine" option, Select in the CTools" list, RLINK-ST-uPSD. Click "OK" to proceed. 23/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE If you click on "Advanced Options", the uPSD Debugger Options window (Figure 13) will be presented and you can adjust settings as outlined previously. The above steps provide the flow for creating a design using RIDE. To further explain this in the following sections, the Sample design example is used (to be described in detail later) using RIDE and demonstrated on the DK3300-ELCD DK3300-ELCD board. The steps described show the key features of RIDE as well as providing a basic understanding of the DK3300 DK3300 and Software tools. 24/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 5 SAMPLE DESIGN AND DEMONSTRATION CODE FOR RIDE 5.1 Purpose The demonstration application code is a RIDE-based project that shows the use of the PWM and ADC function blocks within the uPSD3300 uPSD3300 device. A pulse-width modulated signal output from the PWM circuit is tied to an RC circuit resulting in a DC voltage that is proportional to the pulse width. This DC voltage is input to an ADC channel and is read after each time the pulsewidth signal from the PWM is changed. The PWM setting and the read ADC value is displayed on the LCD. This simple demonstration project will illustrate the powerful software development tools based upon Raisonance RIDE software, and the RLINK-ST adapter, which provides many features for editing, compiling, programming, and debugging a uPSD3300 uPSD3300 MCU Series from STMicroelectronics. This demo will quickly illustrate the specific features below to give you a feel for their simplicity and capability: Project Compilation and Flash Programming Single-Step Execution and Source-Level Debugging Device-Specific Formatted Displays Breakpoints Symbolic Debugging and Variables Watch Code Iteration Instruction Tracing approaching Real-Time performance The RLINK-ST kit, and the DK3300-ELCD DK3300-ELCD Development Board or your own designed circuit board with a uPSD3300 uPSD3300 MCU is all that is needed to develop code. RIDE's debugger utility can be used to symbolically debug 8051 code generated from almost any 8051 compiler. So the choice is to either keep your existing 8051 compiler and debug with the RIDE debugger (no code size limit), or upgrade the evaluation version of the RIDE compiler on the CD so you can compile with no limits and debug code all within the RIDE environment. See the RIDE CD insert, or go to http://www.raisonance.com for more information on RIDE and upgrades. 5.2 Compile Project and Program Flash Memory Launch RIDE from the Windows programs menu (Raisonance Kit 6.1) or from the RIDE icon. Next you'll see a blank work area with the RIDE title menu bar as shown here: Figure 16. RIDE Title Bar Open the demo project. In title menu bar click "Project", then "Open". Next double-click the project named pwm_adc.prj, from the folder: \ - 25/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE ELCD\PWM_ADC\pwm_adc.prj The RIDE environment will display with multiple windows and icons. (Refer to APPENDIX B., Figure 53) for help as you follow along. The left window will show the project files. Click on the "+" to expand the project component files and then double-click on "pwm_adc.c" to open the file (Refer to Figure 17). Figure 17. Project Window Click "Make All". This compiles and builds the project. Start the Debugger by clicking "Start". This programs the Flash and refreshes the RIDE environment showing actions in the "Debug / Action/Messages Window" (See APPENDIX B. Figure 53). The blue line indicates where MCU execution has stopped at the first line of executable code in the main program, now waiting for your debugging command. 5.3 Single-Step and Source-Level Debugging Click "Go" to see that program runs full speed with the DK3300-ELCD DK3300-ELCD Display showing the following lines text PWM to ADC DEMO PWM = xx ADC = yyy where xx and yyy change with each execution of the program loop. Click 26/83 1 "Reset" and the program returns to first line of the main program. uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Click "Step-Over" to execute one line of C code. You can scroll down to see more lines of code in the program. Click When the blue line is on timer0_init(), click " called function, timer0_init(). Double click "Disassembly Code" in left debugger window. This opens a display named, "code (pwm_adc)" showing both C and Assembly code source instructions. Click "Step-Over" a few times to see that code execution can be stepped one assembly instruction at a time. Click "Step-Over" again, which passes you over, and continue until "timer0_init()". "Step-In". The debugger is now in the "Reset" to return to main program, pwm_adc.c 5.4 Device Specific Formatted Displays Double-click "Main Registers" in left debugger window to show contents of MCU core registers (Refer to Figure 18). Double-click on I/O port 1. Go back to the file, pwm_adc.c by clicking on tab at bottom of the main display window (Refer to APPENDIX B., Figure 53), and expand the window view back to full screen. "Port 1" in the left debugger window to show current value of pins Figure 18. MCU Registers 27/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 5.5 Breakpoints Four hardware breakpoints are available on uPSD3300 uPSD3300. Set one breakpoint by clicking on the green dot on the left of the line of code (printfLCD(msg_buff);). The green dot and the selected line will both highlight in red as shown in APPENDIX B., Figure 53 Click Click "Go" repeatedly. See that the display value changes for PWM and ADC after each cycle. You will see increasing values for PWM and decreasing values for ADC each time one loop of code is executed within the while(1) loop construct. "Go", the program will run until hitting breakpoint. 5.6 Symbolic Debugging and Variables Watch With the mouse, highlight the entire variable name "ADC_result", then right-click on it, then select "Add Watch" to add this variable to the Watch Window which appears at bottom left of screen (Refer to APPENDIX B., Figure 53 - and Figure 19). . Figure 19. Watch Window Select K the same way and add to watch window. These variables show values of PWM and ADC Result. Set the Breakpoint the same way as above . Click Click "Go" and see that the values change in watch window (Refer to Figure 19) and the LCD Display. Repeat this a couple of times . You will see that for each loop the PWM value changes by 10. Click 28/83 1 "Reset". "Reset". uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 5.7 Code Iteration Make this code change in Flash memory. Close the Debugger by clicking on Now you are in the editor. Go to file pwm_adc.c by clicking on its file tab and change the following C code statement from: printfLCD("PWM to ADC DEMO"); (this is same icon that "starts" the Debugger). to printfLCD("PWM - ADC DEMO"); Click "Make All" to recompile and rebuild the program. Start the Debugger by clicking memory. Click Go back to editor. Go to file pwm_adc.c and change text back to original printfLCD("PWM to ADC DEMO") Click Start the Debugger by clicking memory. Click DEMO" "Go" and see that LCD display now shows original text "PWM to ADC Click "Reset". "Start" to re-program this new code into Flash "Go" and see that LCD display now shows "PWM - ADC DEMO " "Make All" to recompile and rebuild the program. "Start" to re-program this new code into Flash 5.8 Instruction Tracing, near Real-Time Performance The uPSD will rapidly stream a record of all the MCU instruction steps out to the RLINK-ST adaptor. From this data, RIDE will create a formatted file to help you find even the most stubborn bugs, showing an MCU execution history depth of 256,000 instruction steps. To enable Trace, select from the title bar "Debug" then "Trace", and select trace "Options" as shown in Figure 20 29/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 20. Trace Options Open the Trace Display. Select from the title bar "Debug", then "Trace", then "View". A blank Trace Display will appear. (Refer to Figure 21) A Trace Display file can display program source code in both C and Assembly formats. Tracing runs in the background with little impact to real-time performance in this project. 30/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 21. Blank Trace Go back to the file pwm_adc.c by clicking on its file tab. Set one breakpoint at line of code ( printfLCD(msg_buff); ) as shown in APPENDIX B., Figure 53 by clicking on the green dot on the left of the line of code. The green dot and the selected line will both highlight in red. Click "Go", and the MCU will run until hitting the breakpoint, then a window will open showing the Assembly source code, as shown in APPENDIX B., Figure 53 Note that the red line indicates where the breakpoint is set (MCU Program Counter value 01BA), and the blue line indicates the next instruction to execute. Now open the Trace Display window by clicking on the file tab "Trace(pwm_adc)" as shown in APPENDIX B., Figure 55). At the bottom of the Trace Display is the last instruction that was executed (MCU Program Counter at 01BA). Above this line is the history of all the instructions that the MCU has executed before hitting the breakpoint. Examining the Trace Display window further, you'll see the source C and Assembly statements at each step to assist you in finding a bug. 31/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Go back to the file pwm_adc.c and remove the breakpoint by clicking on the red dot at the left of the red highlighted line of code. Click "Go" and notice that the LCD display shows continuous changes in values of PWM and ADC as the loop is executed multiple times while tracing is occurring in the background. This is seen by changing vales of PWM and ADC in the LCD display. After about 10 seconds click "Stop". A window will appear containing messages recording the actions (Figure 22). This window shows the number of non-sequential instructions traced. Open the Trace Display window again, "Trace(pwm_adc)". At the bottom-left you should see that over 50,000 MCU instruction steps have been recorded. Figure 22. Messages Window Now that you have had a feel for the sample design example, the Design itself is examined by describing the details of implementing it using PSDsoft. During the steps, the whole PSDsoft design flow process is fully detailed, explaining the features and its relevance to the design. Also, the key points are highlighted to ensure you consider and match with your own applications using DK3300 DK3300, or your own designed board, with the RIDE environment and PSDsoft tools. 32/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 6 SAMPLE DESIGN EXAMPLE 6.1 Description This simple design chosen for this example and demonstrated earlier uses the Code and the memory maps for the PWM-ADC application supplied as a demo with the DK3300-ELCD DK3300-ELCD. As explained in the Design flow the key step is to first develop the application relationships and configurations. Here the example demonstration is represented by the block diagram in Figure 23 and the associated memory map is shown in Figure 24. The main Flash memory is paged, and few of the 8032 interfaces (e.g., ADC, PWM) are configured and used. The idea is to touch several aspects of the uPSD that may be unfamiliar to a typical 8032 user and to give you an idea of how to use the design tools as well as giving an overview of the Turbo uPSD3334 uPSD3334 architecture. The design is based upon DK3300-ELCD DK3300-ELCD Development Board. And the application code is developed and compiled using RIDE. Please refer to the general Users Guide for RIDE, the DK3300-ELCD DK3300-ELCD Quick Start, the DK3300ELCD DK3300ELCD User Guide and the User Guide for PSDsoft as needed. Figure 23. Design Example Block Diagram 8 Latch 15 ADC DPLD fs0 - fs7 256KB 256KB Main Flash 8 Page Reg 8 (from Control Regs) AD0-AD7 DATA pin _RESET 32KB 2ndary Flash 4 13 8032 pin XTAL1 csboot0 csboot3 13 _RESET_IN RESET XTAL1 Data Bus Repeater pin P3.1 (TxD) JTAG ISP 2 pin PC3 (tstat) pin PC4 (_terr) pin PC5 (tdi) 8 csiop pin PC6 (tdo) 1 XTAL2 16 pin P3.0 (RxD) pin PC1 (tck) 1 psel0 psel1 256 Control Regs pin XTAL2 pin PC0 (tms) rs0 8KB SRAM 40 MHz pins MCUAD0-MCUAD7 8 16 ADDR ADC 4 DATA PWM Jumper pins MCUA8-MCUA11 MCUA8-MCUA11 ADDR 16 16 8 PMW uPSD3334D-40U6 uPSD3334D-40U6 ADDR A8 - A15 Initial count RxD TxD ALE 16 PLD MarcoCells Down counter UART 0 UART1 pin PB4(LCD_E2) RS-232 RS-232 Transceiver pin PB3(LCD_E1) Pin PB0 (term_count) pin PB2(LCD_RW) P2 E1 R/W pin PB1(LCD_A0) P1 E2 8 pins PA0 - PA7 (LDC_d0 - LCD_d7) D/I (A0) GRAPHIC LCD MODULE (ELCD) D0 - D7 33/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE The 8032 outputs a repetitive PWM pulse train with a slowly varying pulse-width to an RC network which converts the pulse train into a slowly sweeping DC voltage (0V to 3.3V). This DC signal is looped back into an ADC input. The 8032 will write the resulting HEX ADC conversion value to the LCD so you can watch the results. The RC network and loop back is implemented with two jumper blocks (JP14 and JP15) on the DK3300-ELCD DK3300-ELCD board. Additionally and independently, a 4-bit, auto-reloading down-counter is created using PLD MicroCells. The 8032 directly loads the initial count value into four MicroCells, and that count is automatically loaded into another four MicroCells that create the 4-bit down-counter. Reloading occurs each time the counter reaches the terminal count of zero. Terminal count is indicated externally by a pulse on a Turbo uPSD output pin. The down-counter is clocked by an ALE signal (although in this example ALE was a random choice, it could be any signal). The 8032 may load a different initial count at anytime, creating a variable divider of the ALE signal. The Graphic LCD module (ELCD) is connected to the Turbo uPSD3334 uPSD3334 via Port A for data and Port B for some glue logic and chip-select signals. Port A operates in a special data bus repeater mode for this example, called Peripheral I/O mode. MCU8032 MCU8032 data will pass through Port A only for a given address range. The details for entering into PSDsoft and the equations used are described later into this document. (Refer to AN2028 AN2028 Application Note for further details of the Graphic LCD Driver and the Hardware Interface with Turbo uPSD.). Figure 24. Design Example Memory Map Code Space FFFF Page 0 Page 1 Page 2 Page 3 Page 4 X Data Page 5 Page 6 FFFF csboot3 8 Kbytes Secondary Flash fs1 fs2 fs3 fs4 fs5 fs6 fs7 csboot2 E000 DFFF 8 Kbytes 32 K bytes 32 K bytes 32 K bytes 32 K bytes 32 K bytes 32 K bytes Secondary Flash 32 K bytes csboot1 C000 BFFF 8 Kbytes Secondary Flash Main Flash Main Flash Main Flash Main Flash Main Flash Main Flash Main Flash csboot0 Secondary Flash fs0 32 Kbytes 0000 Main Flash 9FFF 8 Kbytes 8000 7FFF A000 control regs for ports A,B,C,D LCD_E1, LCD_E2 and psel0 CSIOP chip select and databus repeater ELCD rs0 8K PSD SRAM (xdata) 8000 7F00-7FFF 7F00-7FFF 7E00-7EFF 7E00-7EFF 0000-1FFF 0000-1FFF The memory map in Figure 24 shows that in this design example, 32K byte secondary flash memory is used for Xdata space, and the 256K byte main flash memory is mapped into the Code space with fs1-fs7, banked over 7 pages. The nomenclature fsx, csbootx, rs0, csiop, and psel in Figure 24 refer to the individual internal Turbo uPSD memory segments. The Turbo uPSD main flash memory has a total of eight 32 Kbyte segments (fs0.fs7) (256Kbyte-Total). 34/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE The Turbo uPSD secondary Flash memory has a total of four 8 Kbyte segments (csboot0 csboot3). All segments are being used in the example code supplied for this design. The Turbo uPSD 8 Kbyte SRAM has a single segment (rs0). A group of uPSD control registers which control I/O ports A, B, C, and D lie in a 256-byte xdata address space whose base address is named csiop. The Turbo uPSD has a data bus repeater feature that is enabled over a given address range as specified by psel. Figure 23 also shows external memory select signals (LCD_E1 and LCD_E2) required by the ELCD Module. This memory map is specified using the software tool PSDsoft Express. Each memory segment can be placed at virtually any address, which provides an infinite number of mapping schemes. In a later section all the equations used are listed and the mapping for the various signals as used by PSDsoft. The key PSDsoft screens are shown and explained for this example. For simplicity in this particular application note, the 8032 will "boot" and run code contained completely within the 32 Kbyte main flash segment in Code space (fs0) and the 256 Kbyte main flash is treated as Code space paged into multiple pages. The font code required resides is in secondary flash segment csboot3 of the xdata mapped memory space. However, you can define alternate memory maps to meet the needs of your particular project. The uPSD memory space can be re-configured to use the secondary as Code space and the primary 256KB 256KB flash as Xdata space. (Refer to Turbo uPSD Datasheets and related documentation for further details). A special register, called the VM Register within the csiop register block, is used to "reclassify" the main flash memory from code space to data space. The VM Register can be accessed by the 8032 at runtime to perform a variety of manipulations. PSDsoft is used to set the initial value of the VM Register upon power-up. 35/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 7 ENTERING DESIGN IN PSDSOFT EXPRESS As shown earlier the key to a successful implementation is defining the desired memory map and then entering the design into PSDsoft. A demonstration design is used to navigate through the steps in the PSDsoft express tool and highlights the key items in this particular example. This way, it is possible to illustrate both the PSDsoft capabilities as well as provide a better understanding and use of PSDsoft's key features in the implementation of the design. Emphasis on setting up the various pin configurations and the associated equations for the PLD portions will be displayed. PSDsoft generates many reports that are very useful for review and analysis. In APPENDIX D. some of the key reports have been given for this project and can be easily correlated to the Design's block diagram and Memory map (Refer to Figures 23 & 24). PSDsoft Express is a free tool available from STMicroelectronics, and you will need to download and install the latest version (v8.10 or later) from STMicroelectronics' website at www.st.com/psd, then look for "Software Downloads". In the following, the key inputs of the sample design are highlighted by showing the Design flow and then by integrating with application code (hex files) to generate the object file which will be programmed using the PSDsoft JTAG. PSDsoft Design Express is shown and explained below: Start PSDsoft Express. - You will get the main design flow screen as shown in Figure 25. This is your starting point. Refer to PSDsoft Users guides for more details 36/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 25. PSDsoft Express Design Flow Click on "Specify Project". You will get the screen shown in Figure 26. Figure 26. PSDsoft Specify Project Screen Select "Open an existing project" (as the demonstration example is being used) and a number of entries will be shown. Next, select the correct PSDsoft project folder which in this case is: 37/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE and you will be shown this screen. Note the filename used by PSDsoft for this example is project.ini Figure 27. PSDsoft OPen Project Screen This verifies that you have made the right selection. Next go to the second step in the design flow "Define PSD and MCU/DSP". This step defines the MCU selected. As RIDE is used, all the necessary parameters are identified in the project.ini file. This step is performed to verify that the entry is correct. You should see the following screen: 38/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 28. Select MCU and Initial Placement of Flash in Code Space or Data Space Notice that all items compare with the design block diagram. The key items are circled. Here you can set the parameters if your design and memory map are different. The key items (fields) for this screen are: 1. Select the MCU. In this case it is STMicroelectronics, then uPSD33xx uPSD33xx, then uPSD3334D uPSD3334D. 2. Select the main flash memory to reside in 8032 program space at power-up (this means that the 8032 _PSEN signal is routed to the secondary flash array). 3. Select the secondary flash to reside in 8032 code space at power-up (this means that the 8032 _RD and _WR signals are routed to secondary flash array). Make sure that screen looks like as shown above. 4. Click OK. Now and then go to the next stepin the Design Flow "Define PSD/Pin/Node Functions". This is described in detail in the next section. 39/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 7.1 Pin Definitions You will be shown the Pin Definitions screen. The entry is normally a 3-step process: 1. Select the pin based upon the selected device output. 2. Add or update the pin function and features, name as shown the second portion. 3. Complete all pin definitions and then continue to the next step. Since the example design is completed, this will show all the pin definitions as shown in the block diagram (Figure 23). Click through the pins and see how they are configured and how they relate to the design. You will notice that upon clicking on the radial button the associated pin name is shown in the Step-2 portion and identifies how the pin function is configured (whether as CPLD input/ output or as other mode.) For the sample design, the key signal names will be shown as related to interfacing with ELCD screen and their relationship to Design block diagram. (Refer to the Block diagram and the LCD pin connections: Figure 23 and Figure 24. See that they are similar for the design) You will also notice that you cannot change the definition of some pins because they have a fixed function. PSDsoft already take cares of this. In this design the pin configurations for Port A and Port B[1.4] are shown below. Port A should be in the Peripheral mode; (Figure 29) Port B, pins 1 and 2 should be in the Combinational Logic Output mode (Figure 30) and Port B, pins 3 and 4 should be in the External Chip-Select, Active-High mode (Figure 31). Here is a sample of each: 40/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 29. Pin definitions for Port A 41/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 30. Pin definitions for Port B (Pins 1-2) 42/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 31. Pin definitions for Port B (Pins 3-4) Walk through some of the pins to verify each pin definitions and get an overview of the design implementation. Click "Next" in step-3 (final step) to move on to the Design Assistant for memory mapping and logic equations. You will see the Design Assistant Screen with the following tabs: Page Register definition Chip Select Equations I/O Logic Equations User-defined Node Equations This is a key part of the design process and requires careful entry for the pin definitions and associated memory maps and logic equations. Since this determines how PSDsoft maps the memory Address space and makes the PLD connections it is imperative that the memory map matches the chip selects for individual memory elements of the Turbo uPSD (memory external to the 8032 core). Definition of the use of the Turbo uPSD Page Register is also required. 43/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Four memory blocks (Main flash, Secondary flash, SRAM, and Control Registers) external to the 8032 core are available and are individually selected segment-by-segment when 8032 addresses are presented to the Decode PLD (DPLD). Each of these memory segments has its own chip-select name (fs0, fs1. csboot1, rs0, csiop, and so forth). Equations for these chipselects, and for any external chip-selects, must be specified using PSDsoft Express. For this example, chip-selects are defined to match the memory map. 7.2 Page Register Paging bits may be used for other types of memory manipulation (such as memory swapping), but that will be discussed in other application notes. Select this bit for memory paging. Use one bit to define two memory pages, use two bits to define four pages, three bits for eight pages and so on. Select enough bits to cover the number required pages. Always start with pgr0 and add more bits going upward, as these bits are an extension of the MCU's or DSP's natural address bits. The MCU/DSP reads and writes the PSD page register bits at run-time to control the system memory map. Outputs of the page register feed the inputs to both PLDs within the PSD. Since eight memory pages (or banks) are needed as shown in the memory map diagram of the design (Figure 24), three paging bits (23 = 8) are specified in the Screen below (Figure 32) Figure 32. Page Register Definitions 44/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Click "Next" to move on to the "Chip Select Equations"Definition Screen. 7.3 Chip-Select Equations Now you will see the Chip-Select definition screen (Figure 33). Some of the signals will be shown in this application note for understanding the different types. You can go through each one to get the pin definitions. The key signals based upon the Block diagram (Figure 23) are shown in the following screens:. Figure 33. Design Assistant Chip select equations (rs0) 1. Click the chip-select signal rs0 for the 8 Kbyte xdata SRAM (see Figure 33) 2. Make sure that its definition matches the memory map in Figure 24. Note: No page number is specified for rs0 since the SRAM is common to all pages (page independent). Additional signal qualifiers (8032 control signals _rd, _wr, _psen, and ale) are NOT needed for internal uPSD chip-selects as this is taken care of in silicon. The SRAM always defaults to 8032 data space. At any time, you may click the "View" button to see how you are doing, and a summary will appear. 3. Click on the chip-select csiop (Chip Select I/O Port). This is a band of 256 xdata registers used to control Turbo uPSD Ports A, B, C, D, the Page Register, power management, and other functions. 40 of the 256 registers are used (see the complete Turbo uPSD datasheet for register definitions and their address offset from the csiop base address). There is no need to specify additional signal qualifiers for csiop, and it is not allowed to place csiop on a particular memory page. 45/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 34. Design Assistant Chip select equations (csiop) 4. Click on fs0, fs1.fs7, which are chip-selects for the eight 32 Kbyte segments of Turbo uPSD Main flash. Figure 35 below shows fs0. Note: the address range of fs0 matches with the memory match, and the address range is 0000 - 7FFF as shown in memory map of Figure 24. 46/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 35. Design Assistant Chip select equations (fs0) 5. Click on fs1. fs2 . fs7, which are chip-selects for the other 7 32 Kbyte segments of Turbo uPSD Main flash. Notes: The page number is 0 for fs1, and the address range is 8000 - FFFF as shown in the memory map (Figure 24) No additional qualifiers are needed for the page number assignments. In Figures 36,37 below, fs1 and fs7 are shown. 47/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 36. Design Assistant Chip select equations (fs1) 48/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 37. Design Assistant Chip select equations (fs7) 6. Click on csboot0, csboot1, csboot2, csboot3, which are chip-selects for the four 8 Kbyte segments of Turbo uPSD secondary flash memory (see Figure 38) - shown for csboot3. 7. Check the address assignments for each of these chip-selects. Note: There are no page numbers assigned; the secondary flash is common to all pages. 49/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 38. Design Assistant Chip select equations (csboot3) 8. Click on psel0. This address range specifies when Port A pins behaves like a data bus repeater in Peripheral I/O Mode to drive the ELCD module. Port A pins were earlier specified a "Peripheral I/O Mode" which acts like a 245 bus transceiver chip connecting the 8032 data bus to external peripherals over a given address range specified by the label psel0 or psel1. The direction of this transceiver function is controlled automatically in silicon by the 8032 _rd and _wr signals (see the full uPSD datasheet for details). All you have to do is click on psel0 and enter the address range 7E00-7EFF 7E00-7EFF to enable this feature for that address range as shown in Figure 24, with no Page Number assignment. psel1 is not needed because the Peripheral I/O feature is active for the logical OR of psel0 or psel1. 50/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 39. Design Assistant Chip select equations (psel0) 9. Click on LCD_E2. This is an external chip-select for the LCD module. Since this is an external chip select, you must include signal qualifiers _rd and _wr. In this design, LCD_E is true (active-high) only when the 8032 presents an address in the range of 7E04-7E07 7E04-7E07 AND when either 8032 control signal _rd is true, OR when 8032 control signal _wr is true, as shown in Figure 40 Note: Signal qualifiers may be added by setting the cursor where you want the signal name to go, then just double-clicking on the signal name in the list of eligible qualifiers. 51/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 40. Design Assistant Chip select equations (LCD_E2) Click on the remaining chip-selects for main flash 10. Click "Next" to move on to I/OLogic Definitions. 7.4 I/O Logic Equations Defined here are equations for PLD outputs for the LCD interface signals. The Design Assistant (DA) will create HDL logic statements using the ABEL language in the background after you enter logic in this point-and-click design entry environment. The DA will also create all the declaration statements in ABEL. This saves much typing and reduces the chance of error. For more complicated logic PSDsoft allows you to edit the ABEL statements directly. 1. Click on "LCD_rw" as shown in Figure 41 Note: The internal signal a0 is assigned to drive the output signal "LCD_rw". Although this was a very simple logic equation, AND, OR, XOR, NOT, and other logic operators are also available for general purpose logic. 2. Click through the remaining signal names and observe the logic assigned. Note: There is no logic equation assigned to term_count because that assignment will be made by editing the ABEL file directly. 52/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 41. Design Assistant I/O Logic equations (LCD_rw) 53/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 42. Design Assistant I/O Logic equations (LCD_A0) 3. Click "Next" to move on to User-Defined Node Equations. 7.5 User-Defined Node Equations Here you will see how internal logic nodes are created. In this example, there are four registers (or nodes) to hold the initial count of the 4-bit down-counter, and four additional registers to create the actual 4-bit down-counter (see Figure 43). These nodes were created by: 1. Clicking the "Def Node." button; 2. Naming the node; and 3. Delecting the type node (e.g., combinatorial, D-register, J-K register). 4. Clicking "Done." Now you will see the main PSDsoft flow diagram that will guide you through the remaining steps. Note: You may view a summary report at this time by pulling down the "Report" selection in the main menu bar at the top of the screen, then selecting "Design Assistant Summary." Your report should match the one in APPENDIX D. 54/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 43. User Node Equations 7.6 Additional uPSD Configuration Click the box "Additional PSD Configuration." This is where you can choose to set the security bit to prevent a device programmer from examining or copying the contents of the Turbo uPSD. The only way to override the security bit is to erase the entire Turbo uPSD, then it can be used again as a blank part. Note: You may also click through the other sheets on this screen to set the JTAG USERCODE value and set the sector protection on the individual uPSD Non-Volatile memory segments. (Just click "OK" for now.) 55/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 44. Additional PSD Configuration 7.7 Fitting Design Click the next highlighted box in the design flow, "Fit Design to Silicon." PSDsoft will compile all the configuration selections and present a report (also available in APPENDIX D.). The fitter report documents how pins are configured and how the programmable logic is allocated. It also shows how many programmable logic product terms are used, which is needed to estimate power consumption. 56/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 7.8 Merging 8032 Firmware with uPSD Configuration Now that all Turbo uPSD pins and configuration settings have been defined, PSDsoft Express will create a single object file (*.obj) that is a composite of the 8032 firmware (*.hex) and the Turbo uPSD configuration. FlashLINK/R-LINK-ST or third-party programmer tools can use this object file to program a Turbo uPSD device. PSDsoft Express will create project1.obj for this design example. During this merging process, PSDsoft Express will input firmware files from the 8032 compiler/linker in Intel HEX format. It will map the content of these files into the physical memory segments of the Turbo uPSD according to the choices that were made in the 'Chip Select Equations' screen. This mapping process translates the absolute system addresses inside 8032 firmware files into physical internal Turbo uPSD addresses that are used by a programmer device to program the Turbo uPSD. This address translation process is transparent. All you need to do is type (or browse) the file name that was generated from the 8032 linker into the appropriate boxes and PSDsoft Express does the rest. You can specify a single file name for more than one Turbo uPSD chip-select, or a different file name for each Turbo uPSD chipselect. It depends on how the 8032 linker has created the firmware file(s). For each Turbo uPSD chip-select in which you have specified a firmware file name, PSDsoft Express will extract firmware from that file only between the specified start and stop addresses, and ignore firmware outside of the start and stop addresses. Click on "Merge MCU Firmware" in the main flow diagram. You will see an information window pop up to remind you to be sure you have configured the firmware compiler and linker to support a paged memory mapping scheme. Select "OK" and you will see the screen shown in Figure 44. In the left column of the "Step 1" area are Turbo uPSD memory segment chip-selects (e.g., FS0, FS1). The next column shows the logic equations for selection of each Turbo uPSD memory segment. These equations reflect the choices that were made while defining Turbo uPSD internal chip-select equations in an earlier step. In the middle of the screen are hexadecimal start and stop addresses that PSDsoft Express has filled in, based on the chip-select equations. On the right are fields to enter (browse) the 8032 firmware files. To select a firmware file: 1. Select "Intel Hex Record" for 'Record Type' as shown in Figure 45. 2. Slide the bar on the right side all the way down to the bottom until you see FS0 3. See that the firmware files are in FS0. This is a small example program that exercises the PWM and ADC channels of the Turbo uPSD on the DK3300-ELCD DK3300-ELCD board, and this code fits completely within the 32Kbyte flash segment fs0. 4. Slide the bar on the right side all the way down to the bottom until you see CSBOOT3 5. You will see the font .hex file in that segment. This specification places firmware in primary Turbo uPSD flash memory segment ds0 and the Fonts in the CSBOOT3. The composite object file used for the demonstration was generated as "project.obj". You can regenerate it as long as all parameters are same. 57/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 45. Merge Firmware (Fs0) 58/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 46. Merge Firmware (csboot3) 59/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 7.9 JTAG Programming Selection of The Programming Tool (either FlashLINK OR R-LINK) is done in the HW setup window. 1. Click the "STMicroelectronics JTAG/ISP" box to program the Turbo uPSD. You will be asked how many JTAG devices are on the target circuit board. 2. Choose "Only One" to see the screen shown in Figure 47 This window enables you to perform JTAG-ISP operations and also offers a loop back test for your FlashLINK/R-LINK cable. If this is your first use, test your FlashLINK or R-LINK cable and PC parallel or USB port by clicking the "HW Setup" button, then click "LoopTest" button and follow the directions. To define your JTAG-ISP environment: 1. Connect the JTAG ribbon cable to the target system 2. Power-up the target system 3. Click 'Execute' on the JTAG screen. The Log window at the bottom of the JTAG screen shows the progress. Programming should just take a few seconds. Note: For this example project, PSDsoft Express should have filled in the folder and filename of the object file to program, the uPSD device, and the JTAG-ISP operation, as shown in Figure 48. There are optional choices available when the "Properties." button is clicked. One choice includes setting the state of all pins on port A, B, C, or D during JTAG-ISP operations (make them inputs or outputs). The default state of these pins is "input", which is fine for this design example. The other choice allows you to specify a USERCODE value to compare before any JTAG-ISP operation starts. This is typically used in a manufacturing environment (see on-screen description for details). 4. After JTAG-ISP operations are complete, click on the 'Save' button so that you can save the JTAG setup for this programming session to a file for later use. Note: You may restore the setup of a different previous session by clicking the 'Browse.' button. Figure 47. JTAG-ISP Operation Selection 60/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 48. JTAG-ISP Operations: Programming Figure 49. Hardware Setting Figure 50. RLINK Test Status 61/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 51. Target Connect test Figure 52. JTAG-ISP Message 7.10 Watch It Run On DK3300-ELCD DK3300-ELCD After JTAG programming completes in just a few seconds, you should see a message appear on the LCD: "PWM to ADC DEMO" You will see the HEX value of the ADC conversion sweep up and down between 0x000 and 0x3FF as the PWM pulse width changes. If you do not see the ADC value change, make sure there are two jumpers installed on the DK3300-ELCD DK3300-ELCD board. They are JP14. Remove the jumper and watch the ADC value on the LCD drop to 000 hex. 62/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE 8 CONCLUSION Congratulations! You have seen the majority of steps to implement a Turbo uPSD design on the DK3300-ELCD DK3300-ELCD board. This design guide showed the basic steps to pre-configure the memories with PSDsoft, compile, program in Flash and debug with RIDE Tools. The process flow diagram steps were described so that the method for creating a new project from scratch was shown and a detailed design and process based upon the PWM-ADC demo has also been described in detail with all the tools required. You still need to review the relevant documentation in the CD-ROM about the uPSD Turbo architecture and the additional documentation supplied on the CD with the DK3300-ELCD DK3300-ELCD kit as well as from the Website links provided earlier. The supplied tools from RIDE limit the Code size to 4KB and any application larger than 4KB would require purchase of the full tools from Raisonance. The example code and the steps clearly demonstrate the powerful firmware development and debugging capabilities of the RIDE environment with RLINK-ST for uPSD DK3300-ELCD-Development Board. For more information, please refer to: Datasheet of the uPSD33xx uPSD33xx MCU at: http://www.st.com/psm Application Note AN48-uPSD on the supplied RIDE CD. Schematic for the DK3300-ELCD DK3300-ELCD circuit board resides at: http://psmdev.st.com/DK3300ELCD _schematics.pdf Please see the ST web site for the latest information on uPSD products, tools, application notes, and other documentation: http://www.st.com/psm 63/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE APPENDIX A. DK3300-ELCD DK3300-ELCD JUMPERS SELECTION AND DEFAULTS The following Table describes the DK3300-ELCD DK3300-ELCD Jumpers. Verify that in Jumper set JP14 ADC7 is closed and JP3 is set to Fix. JP5, JP4 and JP6 Jumper sets are all closed for the PWMADC demo. See the Schematics for more information regarding the jumpers. Table 1. DK3300-ELCD DK3300-ELCD Jumpers Jumper # Description Default settings Comments/ JP1 JTAG Debug I/O Pin Closed JP2 Reset Input Select closed in position 1-2 for reset switch. Position 2-3 for RTC reset. JP3 LCD Contrast 2-3 closed (Fix) Normally closed in position 2-3 Position 1-2 used for PWM control JP4 Enhanced LCD Closed Determines if Enhanced -LCD is on Board JP5 Encoder Connection Normally all 3 closed to This connects Encoder to Port B. enable Encoder JP6 Key board & LED Closed JP7 Enable SPI Closed Normally closed to enable SPI EEPROM JP8 IrDA / Uart1 Select Normally 1-3 and 2-4 Closed to select the RS232 RS232 connector 1 Else can be set to position 3-5 and 4-6 to select the IrDA transceiver to be connected to Uart1. JP9 SRAM Battery Normally Open JP10 Enable I2C Closed Normally both positions closed to enable I2C access to RTC chip. JP11 Clock Select Closed X2 for Crystal Selects Crystal or Oscillator JP12 Interrupt Select for MCU) Normally open. (See DK3300-ELCD DK3300-ELCD schematics) (Used to map various RTC Interrupt sources to the MCU) 1-IRQ; 2-PFO2; 3-SQW; 4PFO1; 5-PBO JP14 ADC Channel Select ADC7 (Positions 15-16) Selects what ADC channel connects the RC is Closed circuit on the board. JP15 PWM RC Constant Normally (position 1-2) is closed. Selects PWM RC constant. position 1-2 is 1ms. JP16 For connecting Uart0 and Uart1 in loop back mode Normally open Can be connected positions 1-2 and 3-4 for loop back. Normally not used Headers can be used to connect to check signals: 1- ECON 2-TPCLR 3-F32K 3-F32K 4-GND JP18 64/83 1 Headers for M41ST87 M41ST87 Signals Should be closed uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE APPENDIX B. INTERFACE DISPLAY WINDOWS AND CODE VIEW Figure 53. Ride Interface Display Windows 65/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 54. Code View (Disassembly) 66/83 1 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 55. Trace Display 67/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE APPENDIX C. Importing an external application into RIDE The RIDE IDE allows you to combine the building of the project and the debugging of the built application. However, you could wish to simply debug an application that has been written and compiled out of RIDE. In such a situation, chose "Debug | Load" and you will be presented with the following window: Figure 56. Debug Application Window You can then select your application. You will have also to specify the format of this application. Take care that some of the listed formats does not contain any debug information (such as HEX or Binary): Figure 57. Format Drop-down List Debugging an external application and a built-in-RIDE application will be then exactly the same. If none of these formats matches with the format of your application, it is recommend that you check if the tools you are using allow conversion from the original format into one from this selection. Importing a Keil Project into RIDE for Debugging Here, the process is shown for importing the same application example as developed using Keil Compiler. This is available in the Keil folder of your installed Keil software tools. Browse through the application path and then select the correct file. (See note below). The Keil AOM5F51 AOM5F51 format required by RIDE has no extension and in this case it will be the following 68/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE path and file name: Right click on arrow on the Format display and ensure that you select Keil AOMF51 AOMF51. Note: for Keil projects the file name has no extension and is same as the project name used for developing the application. uPSD projects for Keil have the extension *.uv2. Below, the RIDE screens are shown for importing the same PWM_ADC project from Keil and then loading in DK330-ELCD DK330-ELCD and using RIDE tools to Debug. You may use this process to import large codes into the Eval and demonstration version of RIDE for Debugging only. Figure 58. Keil Application path and Format Click "OK". RIDE will generate the next screen shown below. Select the correct device. Figure 59. Core selection 69/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Running the application on the target hardware To load and to debug your application using the RLINK-ST dongle, you have first to configure the "Options | Debug" window as follows: Figure 60. Debug Options Select the Real Machine option, Select in the "Tools" list, RLINK-ST-uPSD. If you then click on "Advanced Options", the following window will be presented: 70/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 61. Debugger Options Screen This window allows you: To specify the PSDsoft Express project file (INI). To specify the JTAG chain description file (if any) when the uPSD part is included into a multiple-device JTAG chain. To execute simple commands such as Erase, Program and Blank-Check. To specify the CSIOP address This window allows you: To specify the PSDsoft Express project file (INI). To specify the JTAG chain description file (if any) when the uPSD part is included into a multiple-device JTAG chain. To execute simple commands such as Erase, Program and Blank-Check. 71/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE To specify the CSIOP address Specifying the PSDsoft Express INI file information In the above window, the file "project.ini" is a project you designed using PSDsoft Express, where all associated information pertaining to this project reside. Merging is the action of creating an OSF file, using an INI file generated by PSDsoft Express. An OSF file is a file containing the code to be loaded in all the sectors of the part. This is the only format supported by the loader. It is strongly recommended to always keep the "Merge" option checked, unless you plan to use the debugger as a simple downloader for programming a large number of boards, with a program that you have already tested and validated. Note that for merging, you MUST have PSDsoft Express properly installed on your computer. Indeed, RIDE will call some ST utilities (present in the PSDsoft Express directory) to merge the PLD and the flash. These utilities are the following: UTLADRM.EXE OBJOSF.EXE If you have issues, please check that these files exist into your PSDsoft Express. Make sure that you give the correct Keil folder path and get the PSDsoft files from the folder to ensure correct code loading. Executing simple commands such as Erase, Program and Blank-Check. It is recommended first to check that both the RLINK-ST dongle and the target board are properly connected and powered. The communication can be checked by clicking onto: 1. "Connect to Rlink" to check that the USB dongle answers, 2. "Connect to target" to check that the uPSD answers to the dongle. Then, the first command available is Erase. 1. "Erase Full Chip" allows to erase both the PLD and the FLASH. 2. "Erase Flash Sectors" allows to erase only the FLASH, keeping intact the contents of the PLD. 3. "Do not Erase" makes sense only when the debug session is started and that the only selected options will be executed at the loading time. Once Erased (which is done by clicking on "Erase Now!"), a blank check can be performed by clicking on the "Blank-Check" button. Then, programming can be done with the exact same options as "Erasing". 72/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Caution: Note that the settings of "Erase" and "Program" will be used when launching a debug session. You need, before clicking on "OK" to keep the settings required for debugging. In most of cases, it is recommend to set: 1. either "Erase Flash Sectors" and "Program Flash Sectors" if you don't need to update the PLD (but keep the "Merge" option checked), 2. or "Erase Full Chip" and "Program Full Chip" when you are still working on the design of the PLD . Specifying the CSIOP address. This information is mandatory when the application is larger than 64KB and uses the bank-switching technique. In this case, the RIDE debugger needs to read the PAGE register to calculate the current PC. This PAGE register is found within the CSIOP segment (that can be relocated anywhere in the XDATA segment). Debugging the application on the hardware target from RIDE Refer to section 3, PROJECT CREATION AND SAMPLE DESIGN DEVELOPMENT PROCESS above and also to RIDE documentation. Main features. Hardware breakpoints: the embedded debug module provides four hardware breakpoints that can be used either as standard breakpoints in the program, or as data breakpoints (See RIDE documentation for how to set breakpoints). Note that the RIDE debugger needs also to set temporary breakpoints to perform most of the HLL commands (step over/into/ out.). Therefore, it is highly recommended to disable the breakpoints when they are not used. Note: when the four breakpoints are already set, the debugger displays a message to report this situation. Execution control (Step into/over/.), Data/SFR visualization, Trace mode (see next paragraph). The trace mode. The on-chip debug system of the uPSD turbo core features a powerful trace mode. To either enable or disable this mode, chose "Debug | Trace | Options" and the following window will be presented: 73/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE Figure 62. Trace Options Window Trace ON Trace OFF When enabled, the CPU transfers the destination address at every non-sequential instruction (e.g. JMP, CALL, RET.) into a JTAG buffer that will be read by the RLINK-ST dongle. In the case where two non-sequential instructions are executed almost consecutively, the bit-rate on the JTAG communication will not be sufficient to read the previous destination address, and the execution will be paused automatically (and released as soon as the JTAG buffer is empty). Therefore, setting the TRACE mode could slow down the overall execution. Moreover, the standard breakpoint mechanism is no longer available when the trace mode is enabled. The breakpoints can be set, but they will only trigger an interrupt instead of freezing the execution. The following table summarizes the restrictions that are present when the trace is enabled: Table 2. Execution performance with Trace ON/OFF Trace OFF Transparency Real-Time Notes: 74/83 Trace ON HW breakpoints stop the execution (the CPU clock is disabled). -HW Breakpoints trigger an interrupt -EA must be kept set to allow breakpoints -Breakpoint Interrupt vector () must be reserved Full-Speed Wait states are added (depending on the program) when non sequential instructions are too frequent. uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE When the trace mode is set, the breakpoints behave differently. Executing an instruction with a breakpoint sets the breakpoint interrupt flag. Therefore, the execution will be stopped only one or two instructions later. The execution will be stopped ONLY if the interrupt is currently enabled. When the execution is launched, RIDE enables the breakpoint interrupt. However, your program must avoid disabling the global interrupts or the debug breakpoint interrupt. Reliability of the trace/code coverage information. Due to the dynamic mechanism used for tracing, Trace and Code Coverage has some limitations which needs to be noted. Some known issues are listed below: 1. when several conditional jumps branch to the same address, it's not possible to detect the effective branch. 2. when an interrupt occurs, the current instruction (when non-sequential) is unknown. The following instructions will be listed in the trace buffer until encountering the next-nonsequential instruction. But a correction is done in the code coverage to avoid counting twice these instructions. Performances in Trace mode. When the trace mode is switched ON, the execution speed is reduced since Rlink has to read the destination address after any branch instruction. The following table gives some typical values: Table 3. Execution performance in Trace mode Without Code Coverage With Code Coverage Branch instructions (non sequential instructions) 125 K/ s 65 K/s Instructions 600 K/s 350 K/s Notes: The ratio (non-sequential instruction / total) depends on the application, but the typical value is around 1/5. The number of instructions processed for the code coverage depends a lot on the performances of the computer. 75/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE APPENDIX D. PSDSOFT REPORTS Project.frp This report is generated by PSDsoft after the Fit design to silicon step and the report for this example is listed here. Some Key points are highlighted for reviewing in relationship to the example design. * PSDsoft Express Version 8.30 Output of PSD Fitter * PROJECT : project DATE : 01/18/2005 DEVICE : uPSD3334D uPSD3334D TIME : 17:56:54 FIT OPTION : Keep Current DESCRIPTION: Combo Demo code to demonstrate Turbo uPSD's IPs: PCA-PWM, I2C, SPI, and JTAG, it runs on a DK3300 DK3300 ELCD board. * = Pin Layout for U (80-Pin TQFP) Package Type = -| | pd2 |1 ] pd2 adio4 [41| Address Bus a4/Data Port |2 ] p3_3 p3_5 [42| pd1 |3 ] pd1 adio5 [43| Address Bus a5/Data Port ale |4 ] pd0 p3_6 [44| |5 ] pc7 adio6 [45| Address Bus a6/Data Port tdo, TDO |6 ] pc6/TDO p3_7 [46| tdi, TDI |7 ] pc5/TDI adio7 [47| Address Bus a7/Data Port JTAG_debug_pin |8 ] debug Xtal1 [48| Xtal1 _terr, TERR |9 ] pc4/TERR Xtal2 [49| Xtal2 |10] 3.3V VCC 5.0V VCC [50| |11] N/C adio8 [51| Address Bus a8, a8 |12] 5.0V VCC p1_0 [52| |13] GND adio9 [53| Address Bus a9, a9 tstat, TSTAT |14] pc3/TSTAT p1_1 [54| |15] pc2 adio10 [55| Address Bus a10, a10 tck, TCK |16] pc1/TCK p1_2 [56| |17] N/C adio11 [57| Address Bus a11, a11 |18] p4_7 p1_3 [58| |19] p4_6 p1_4 [59| tms, TMS |20] pc0/TMS p1_5 [60| pa7 ,Peripheral I/O Mode |21] pa7 p1_6 [61| pa6 ,Peripheral I/O Mode |22] pa6 cntl0 [62| _wr |23] p4_5 cntl2 [63| _psen pa5 ,Peripheral I/O Mode |24] pa5 p1_7 [64| |25] p4_4 cntl1 [65| _rd pa4 ,Peripheral I/O Mode |26] pa4 pb7 [66| pb7 |27] p4_3 pb6 [67| En_EA pa3 ,Peripheral I/O Mode |28] pa3 Reset_In [68| _Reset_In |29] GND GND [69| |30] p4_2 Vref [70| VREF |31] p4_1 pb5 [71| En_EB pa2 ,Peripheral I/O Mode |32] pa2 AVcc [72| |33] p4_0 pb4 [73| LCD_E2 pa1 ,Peripheral I/O Mode |34] pa1 pb3 [74| LCD_E1 pa0 ,Peripheral I/O Mode |35] pa0 p3_0 [75| ad0, Address Bus a0/Data Port d0 |36] adio0 pb2 [76| LCD_RW ad1, Address Bus a1/Data Port d1 |37] adio1 p3_1 [77| ad2, Address Bus a2/Data Port d2 |38] adio2 pb1 [78| LCD_A0 ad3, Address Bus a3/Data Port d3 |39] adio3 p3_2 [79| |40] p3_4 pb0 [80| | | -= Global Configuration = Data Bus : 8-Bit Address/Data Mode : Multiplexed ALE/AS Signal : Active High Control Signals : /WR, /RD, /PSEN Main PSD flash memory will reside in this space at power-up : Program space Secondary PSD flash memory will reside in this space at power-up : Data space Enable Chip-Select Input(/CSI) : OFF Standby Voltage Input (PC2) : OFF Standby-on Indicator (PC4) : OFF RDY/Busy function (PC3) : OFF Load Micro-Cell on : edge Security Protection : OFF = DataBus_IMC access information = 76/83 d4, ad4 d5, ad5 d6, ad6 d7, ad7 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE CSIOP Location Address Offset Register Name Signals -= Resource Usage Summary = Total Product Terms Used: 45 Device Resources used / total -Port A: (pins 35 34 32 28 26 24 22 21) I/O Pins : 8 / 8 GP I/O or Address Out : 0 Peripheral I/O : 8 Logic Inputs : 0 Address Latch Inputs : 0 PT Dependent Latch Inputs : 0 PT Dependent Register Inputs : 0 Combinatorial Outputs : 0 Registered Outputs : 0 Other Information Microcells : 6 / 8 Micro-Cells AB : Buried Microcells : 6 Output Microcells : 0 Product Terms : 7 / 24 Control Product Terms : 12 / 34 Port B: (pins 80 78 76 74 73 71 I/O Pins : GP I/O or Address Out Logic Inputs Address Latch Inputs PT Dependent Latch Inputs PT Dependent Register Inputs Combinatorial Outputs Registered Outputs Other Information Microcells Micro-Cells AB : Buried Microcells Output Microcells Micro-Cells BC : Buried Microcells Output Microcells Product Terms Control Product Terms 67 66) 7 : 1 : 2 : 0 : 0 : 0 : 4 : 0 Port C: (pins 20 16 15 14 9 7 6 I/O Pins : GP I/O or Address Out Logic Inputs Address Latch Inputs PT Dependent Latch Inputs PT Dependent Register Inputs JTAG signals Standby Voltage Input Rdy/Bsy signal Standby On Indicator Combinatorial Outputs Registered Outputs Other Information Microcells Micro-Cells BC : Buried Microcells Output Microcells Product Terms Control Product Terms 5) Port D: (pins 4 3 1) I/O Pins : GP I/O or Address Out Logic Inputs Chip-Select Input Clock Input Control Signal Input Fast Decoding Outputs Other Information Product Terms Control Product Terms : 6 : : 2 0 : : : : 0 4 9 7 / 8 / 8 / 28 / 34 6 0 0 0 0 0 6 0 0 0 0 0 / 8 : : : : : : : : : : : : 4 / 8 : : : : 4 0 6 0 / 32 / 34 3 2 0 0 0 1 0 / 3 : : : : : : : : 0 0 / 3 / 3 77/83 uPSD3300 uPSD3300 Series Design Guide for DK3300-ELCD DK3300-ELCD Using RIDE = OMC Resource Assignment = Resources PT User Used Allocation Name -Micro-Cell AB : Micro-Cells 0 En_counter0 => Register Micro-Cells 1 En_PA => Register Micro-Cells 2 En_PB => Register Micro-Cells 3 En_Dir => Register Micro-Cells 4 En_counter0_C_0 => Combinatorial Micro-Cells 5 En_Dir_C_0 => Combinatorial Micro-Cell BC Micro-Cells Micro-C