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Part Manufacturer Description Datasheet BUY
DF1760P Texas Instruments 4-BIT, DSP-DIGITAL FILTER, PDIP28, PLASTIC, DIP-28 visit Texas Instruments
DF1760U Texas Instruments Multi-Bit Enhanced Noise Shaping 20-Bit A/D Conversion System 20-SO visit Texas Instruments
DF1760U/1KE6 Texas Instruments 4-BIT, DSP-DIGITAL FILTER, PDSO28, SOP-28 visit Texas Instruments

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Part : DF1760P Supplier : Texas Instruments Manufacturer : Avnet Stock : - Best Price : $33.0615 Price Each : $38.2438
Part : DF1760P Supplier : Texas Instruments Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Part : DF1760U Supplier : Texas Instruments Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Part : DF1760P Supplier : Texas Instruments Manufacturer : Rochester Electronics Stock : 26 Best Price : $38.75 Price Each : $47.69
Part : DF1760U Supplier : Texas Instruments Manufacturer : Rochester Electronics Stock : 90 Best Price : $34.52 Price Each : $42.48
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DF1760 Datasheet

Part Manufacturer Description PDF Type
DF1760 Burr-Brown Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM Original
DF1760 Texas Instruments Multi-Bit Enhanced Noise Shaping 20-Bit A-D Conversion System Original
DF17-60DP-0.5V Hirose Electric 0.5mm Pitch Board to Board Connector Original
DF17-60DS-0.5V Hirose Electric 0.5mm Pitch Board to Board Connector Original
DF1760P Burr-Brown Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM Original
DF1760P Texas Instruments DF1760 Multi-bit Enhanced Noise Shaping 20-Bit A/D Conversion System Original
DF1760P Texas Instruments Multi-Bit Enhanced Noise Shaping 20 Bit Analog-to-Digital Conversion System Original
DF1760P/U Burr-Brown Multi-Bit Enhanced Noise Shaping 20-Bit Analog-to-Digital Conversion System Original
DF1760U Burr-Brown Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM Original
DF1760U Texas Instruments Multi-Bit Enhanced Noise Shaping 20-Bit A/D Conversion System 20-SO Original
DF1760U_1K Burr-Brown Multi-Bit Enhanced Noise Shaping 20-Bit A/D Conversion System Original
DF1760U/1K Texas Instruments Multi-Bit Enhanced Noise Shaping 20-Bit A/D Conversion System Original
DF1760U/1KE6 Texas Instruments DF1760 - IC 4-BIT, DSP-DIGITAL FILTER, PDSO28, SOP-28, DSP Peripheral Original

DF1760

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Burr-Brown
Original
20-BIT PCM1760 28-PIN PCM1760/DF1760 SBAA032 SBAA055
Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Texas Instruments
Original
Abstract: NA NA PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE MODEL PACKAGE , -Pin SOIC 804 DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 800 804 800 NOTE: (1 , 6 ns Fall Time - - 6 ns FIGURE 3e. Timing o f Slave Mode, DF1760. SYSTEM , DF1760. . I 1 dsv, ' T «â' ü « â *'' X ! FSYNC I , , DF1760. BURR-BROWN » 9 17313b5 D0257fl 4 325 â  P C M 1 7 6 0 P /U D F 1 7 6 0 P /U I -
OCR Scan
17313LS

vas05

Abstract: fsync in PCM soie -90dB 108dB PCM1760P-L PDIP -88dB 106dB PCM1760U-L soie -88dB 106dB DF1760P PDIP NA NA DF1760U , 28-Pin SOIC 804 PCM1760P-L 28-Pin PDIP 800 PCM1760U-L 28-Pin SOIC 804 DF1760P 28-Pin PDIP 801 DF1760U , FIGURE 3c. System Clock Timing Requirements of DF1760. tdsv SCLK _/ \_/ \_ Tikv 1 dss , Timing of Master Mode, DF1760. hhbr tslkh tsikl SC KL _J \_f X / Y "^dss ^ ^dsv mmrnm , Mode, DF1760.
-
OCR Scan
vas05 fsync in PCM G03E141

marking C4L

Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760.
Texas Instruments
Original
marking C4L DEM-PCM1760
Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Texas Instruments
Original

DF1760

Abstract: PCM1760 Master Mode, DF1760. ® 9 PCM1760P/U DF1760P/U THEORY OF OPERATION The DF1760 accepts the , -Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 800 804 800 804 DF1760P DF1760U PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE , devices and/or systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View PIN , DIAGRAM OF PCM1760 AND DF1760 ® PCM1760P/U DF1760P/U FUNCTIONS OF THE DIGITAL FILTER OFFSET
Burr-Brown
Original
Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Texas Instruments
Original

RT1L

Abstract: DF1760 Master Mode, DF1760. ® 9 PCM1760P/U DF1760P/U THEORY OF OPERATION The DF1760 accepts the , -Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 800 804 800 804 DF1760P DF1760U PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE , devices and/or systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View PIN , DIAGRAM OF PCM1760 AND DF1760 ® PCM1760P/U DF1760P/U FUNCTIONS OF THE DIGITAL FILTER OFFSET
Texas Instruments
Original
RT1L
Abstract: PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE , FIGURE 3e. Timing of Slave Mode, DF1760. , DESCRIPTION r v r v r i â'"r u ~ L T FIGURE 3c. System Clock Timing Requirements of DF1760. TO , and Mode Reset Timing. FIGURE 3d. Output Timing of Master Mode. DF1760. B U R R -B R O W N Â , input stage of the system can be compensated by using the calibration mode of the DF1760. Offset -
OCR Scan
DF176 PPMCBA17- BA87- TTTTTI11111ITTT GD215

RT1L

Abstract: DF1760 Master Mode, DF1760. ® 9 PCM1760P/U DF1760P/U THEORY OF OPERATION The DF1760 accepts the , -Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 800 804 800 804 DF1760P DF1760U PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE , devices and/or systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View PIN , DIAGRAM OF PCM1760 AND DF1760 ® PCM1760P/U DF1760P/U FUNCTIONS OF THE DIGITAL FILTER OFFSET
Burr-Brown
Original
1 bit delta-sigma servo dc TTL 74hc74 74HC74

72000H

Abstract: DF1760 Master Mode, DF1760. ® 9 PCM1760P/U DF1760P/U THEORY OF OPERATION The DF1760 accepts the , -Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 800 804 800 804 DF1760P DF1760U PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE , devices and/or systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View PIN , DIAGRAM OF PCM1760 AND DF1760 ® PCM1760P/U DF1760P/U FUNCTIONS OF THE DIGITAL FILTER OFFSET
Burr-Brown
Original
72000H
Abstract: datasheet in Acrobat PDF: df1760.pdf (128 KB) (Updated: 09/27/2000) Product Folder: DF1760, Multi-Bit , +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Burr-Brown
Original
SGZN001A SBAU022
Abstract: 18 -8 -1 2 40 4 370 PCM 1760 PCM1760 PCM 1760 PCM1760 DF1760, Normal Mode DF1760. , 217-2J DF1760P DF1760U PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP , FIGURE 3d. Output Timing of Master Mode, DF1760. T hl NAME MM TYP MAX UM TS Low , - 6 ns FIGURE 3c. System Clock Timing Requirements of DF1760. FIGURE 3e. Timing of Slave Mode, DF1760. E â  17313bS GG224flb 7Ã3 â  WR-BROWM« E 3 E 3 J A block diagram of a -
OCR Scan
256FS 384FS 64-FS
Abstract: Edge FIGURE 3e. Timing of Slave Mode, DF1760. BURR-BROWN 9 PCM1760P/U DF1760P/U â â , PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U MODEL PACKAGE PACKAGE DRAWING NUMBER , 173-1J 217-2 J 173-1J 217-2J DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 173-2J 217-3J NOTE , DF1760P/U 6 64 BASIC CONNECTION DIAGRAM OF PCM1760 AND DF1760 BURR-BROWN S 1 PCM1760P/U , , DF1760. V NAME MIN TYP MAX UNITS Low Level Duration "^CLKi. 31 - - ns -
OCR Scan
Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Burr-Brown
Original
SBAA033 SGLB002 SGYC003B
Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Texas Instruments
Original

RT1L

Abstract: DF1760 Master Mode, DF1760. ® 9 PCM1760P/U DF1760P/U THEORY OF OPERATION The DF1760 accepts the , -Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 800 804 800 804 DF1760P DF1760U PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE , devices and/or systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View PIN , DIAGRAM OF PCM1760 AND DF1760 ® PCM1760P/U DF1760P/U FUNCTIONS OF THE DIGITAL FILTER OFFSET
Texas Instruments
Original
datasheet of 74HC74 ic

DF1760

Abstract: PCM1760 Master Mode, DF1760. ® 9 PCM1760P/U DF1760P/U THEORY OF OPERATION The DF1760 accepts the , -Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 800 804 800 804 DF1760P DF1760U PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE , devices and/or systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View PIN , DIAGRAM OF PCM1760 AND DF1760 ® PCM1760P/U DF1760P/U FUNCTIONS OF THE DIGITAL FILTER OFFSET
Texas Instruments
Original
Abstract: +125°C ORDERING INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE , NA PACKAGE INFORMATION MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28 , systems. ® 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View OVL OVR D3 D2 D1 D0 TP1 , ns ns ns ns THL FIGURE 3e. Timing of Slave Mode, DF1760. Texas Instruments
Original
Abstract: (DF1760) q HIGH PERFORMANCE: THD+N: ­92dB typ, ­90dB max Dynamic Range: 108dB typ SNR: 108dB min, 110dB , OPTIONAL FUNCTIONS: Offset Error Calibration Overflow Detection Power Down Mode (DF1760) q RUNS ON ±5V SUPPLIES (PCM1760) AND 5V SUPPLY (DF1760) q COMPACT 28-PIN PACKAGES: 28-Pin DIP and SOIC PCM1760 DESCRIPTION The PCM1760 and DF1760 combine for a low-cost, high-performance dual 20-bit, 48kHz sampling analog-to-digital conversion system which is specifically designed for dynamic applications. The PCM1760/DF1760 pair Texas Instruments
Original
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