CY28352-400 DDR400 CY28352OC CY28352OI

Differential Clock Buffer/Driver DDR400 and DDR333-Compliant Features Description · Supports 333-MHz and 400-MHz DDR SDRAM

CY28352-400 CY28352-400 Differential Clock Buffer/Driver DDR400 DDR400 and DDR333-Compliant Features Description · Supports 333-MHz and 400-MHz DDR SDRAM · 60273-MHz operating frequency This PLL clock buffer is designed for 2.6VDD and 2.6AVDD operation and differential output levels. · Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN. · Distributes one clock input to six differential outputs · External feedback pin FBIN is used to synchronize output to clock input · Conforms to DDRI specification · Spread AwareTM for electromagnetic interference (EMI) reduction The two-line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, low-jitter output differential clocks. · 28-pin SSOP package Block Diagram Pin Configuration 10 CLKC0 CLKT0 VDD CLKT1 SDATA CLKIN PLL FBIN AVDD CLKIN NC CLKT4 CLKC4 Serial Interface Logic CLKT2 CLKC2 CLKT3 CLKC3 SCLK CLKC1 GND SCLK AVDD CLKT5 CLKC5 AGND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY28352-400 CY28352-400 CLKT0 CLKC0 CLKT1 CLKC1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA NC FBIN FBOUT NC CLKT3 CLKC3 GND FBOUT 28 pin SSOP Rev 1.0, November 28, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Page 1 of 7 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY28352-400 CY28352-400 Pin Description[1] Pin Number Pin Name 8 CLKIN 20 FBIN 2,4,13,17,24, CLKT(0:5) 26 1,5,14,16,25, CLKC(0:5) 27 I/O I I O O 19 FBOUT O 7 SCLK I 22 SDATA I/O 3,12,23 VDD 10 6,15,28 11 9, 18, 21 AVDD GND AGND NC Electrical Pin Description Characteristics Complementary Clock Input. Input Feedback Clock Input. Connect to FBOUT for accessing the PLL. Input Clock Outputs Differential Outputs Clock Outputs Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 2.6V Power Supply for Logic 2.6V Power Supply for PLL Ground Analog Ground for PLL Not Connected Output Data Input for the two line serial bus Data Input and Output for the two line serial bus 2.6V Nominal 2.6V Nominal Zero Delay Buffer Power Management When used as a zero delay buffer the CY28352-400 CY28352-400 will likely be in a nested clock tree application. For these applications the CY28352-400 CY28352-400 offers a clock input as a PLL reference. The CY28352-400 CY28352-400 can then lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. The individual output enable/disable control of the CY28352-400 CY28352-400 allows the user to implement unique power management schemes into the design. Outputs are three-stated when disabled through the two-line interface as individual bits are set low in Byte0 and Byte1 registers. The feedback output FBOUT cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks. When AVDD is strapped LOW, the PLL is turned off and bypassed for test purposes. Function Table Inputs AVDD Outputs CLKIN CLKT(0:5)[2] CLKC(0:5)[2] PLL FBOUT GND L L H L BYPASSED/OFF GND H H L H BYPASSED/OFF 2.5V L L H L On 2.5V H H L H On 2.5V