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TS2DDR2811ZXYR Texas Instruments 1GHz Bandwidth, 8-bit SPST switch with Low and Flat On-State Resistance 20-BGA MICROSTAR JUNIOR -40 to 85 visit Texas Instruments Buy
CDCU2A877ZQLR Texas Instruments 1.8V Phase-Lock Loop Clock Driver with high output drive for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR 0 to 70 visit Texas Instruments
CDCU2A877ZQLT Texas Instruments 1.8V Phase-Lock Loop Clock Driver with high output drive for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR 0 to 70 visit Texas Instruments Buy
TIC10024QDCPTQ1 Texas Instruments Automotive 24-Input Multiple-Switch Detection With SPI Interface 38-HTSSOP -40 to 125 visit Texas Instruments
TIC12400DCPR Texas Instruments 24-Input Sensor Monitor With SPI Interface 38-HTSSOP -40 to 105 visit Texas Instruments
TIC12400QDCPRQ1 Texas Instruments Automotive 24-Input Multiple-Switch Detection With SPI Interface 38-HTSSOP -40 to 125 visit Texas Instruments

DDR2 SDRAM with SSTL_18 interface

Catalog Datasheet MFG & Type PDF Document Tags

AN328

Abstract: AP1910 design examples interface with five DDR2 SDRAM components (amounting to a 72-bit interface) available in , with DDR2 SDRAM modules and discrete devices. (4) DDR2 SDRAM memory interface support in Arria GX , -bit interface uses AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices , AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices © October , for implementing a DDR2 SDRAM memory interface on a Stratix II, Stratix II GX, or Arria GX FPGA
Altera
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ELPIDA DDR3

Abstract: Elpida GDDR5 Family J: DDR3 E: DDR2 D: DDR SDRAM, DDR Mobile RAM Power Supply, Interface Organization Density / Bank S: SDRAM, (SDR) Mobile RAM W: GDDR5 X: XDR B: DDR2 Mobile RAM R: RDRAM ©Elpida Memory, Inc , information) Module Outline J: DDR3 Module Die Rev. (Mono) Power Supply, Interface E: DDR2 Module Mono Organization Product Family D: DDR SDRAM Module S: SDRAM Module R: RIMM ©Elpida Memory , : x8 16: x16 Package SE: FBGA BG: FBGA Power Supply, Interface B, D: 1.5V, SSTL_15 ©Elpida
Elpida Memory
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MT36HVS25672PY-667D1

Abstract: BC 667 during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM , voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) SDRAM access from clock, tAC , 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Features DDR2 SDRAM VLP RDIMM MT36HVS25672 , notice. 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM Features Table 2: Parameter Refresh , : MT47H256M4THK,1 1Gb TwinDieTM DDR2 SDRAM Module Density 2GB 2GB Module Bandwidth 5.3 GB/s 4.3 GB/s Memory Clock
Micron Technology
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MT36HVS25672PY-667D1 BC 667 240-P MT36HVS51272 PC2-4200 PC2-5300 PC2-6400 DDR2-800
Abstract: is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules , interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) SDRAM access from clock, tAC (CL = MAX , supported Module thickness (with/without heat spreader) DDR2 DIMM type SDRAM module attributes SDRAM device , 8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM Features DDR2 SDRAM RDIMM MT72HT(Z)S1G72P ­ 8GB , herein are subject to change by Micron without notice. 8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM Micron Technology
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PC2-3200 MO-237 DDR2-667 DDR2-533 DDR2-400 HTS72C1G

ddr2 module ecc

Abstract: , along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM , and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and , Modules Base device: MT47H128M4,1 2Gb DDR2 SDRAM Module Density 1GB 1GB Configuration 128 Meg x 72 128 , : Part Numbers and Timing Parameters ­ 2GB Modules Base device: MT47H256M4,1 1Gb DDR2 SDRAM Module , On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
Micron Technology
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ddr2 module ecc MT18HVF12872 MT18HVF25672 HVF18C128

MT72HVQ1G72

Abstract: U21R0 8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM VLP RDIMM Features DDR2 SDRAM VLP RDIMM MT72HVQ1G72P ­ , . 8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM VLP RDIMM Features Table 2: Addressing Parameter 8GB , : MT47H1G4THT,1 4Gb QuadDie DDR2 SDRAM Part Number2 Module Density Configuration Module Bandwidth , , ECC, QR) 240-Pin DDR2 SDRAM VLP RDIMM Pin Assignments and Descriptions Pin Assignments and , reserved. 8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM VLP RDIMM Pin Assignments and Descriptions Table 5
Micron Technology
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MT72HVQ1G72 U21R0 MT72HVQ1G72PY-667 MT47H1G4 U21R1 SSTL-18 HVQ72C1G

k4B2G1646

Abstract: K4S561632N : SDRAM : DDR SDRAM : DDR2 SDRAM : DDR3 SDRAM : GDDR : GDDR3 : SSTL_2 (2.5V, 2.5V) Q : SSTL_18 , Lead-free & Halogen-free package with Lead-free package code(-U) 2.2 DDR SDRAM Density Bank Part , Apr. 2010 Product Guide Consumer Memory 2.3 DDR2 SDRAM Density Banks Part Number , with Lead-free package code(-U) 2.7 GDDR3 SDRAM Density Banks Part Number 1Gb E-die , 84ball FBGA Now SSTL_18 8K/64m 1.8V ± 0.1V Interface Refresh Power (V) 60ball
Samsung Electronics
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k4B2G1646 K4S561632N K4B2G1646C k4t1g164qf K4T51163QI K4H641638Q 10MAX

DDR2 SSTL class

Abstract: SSTL_18 registered buffer with parity for DDR2 RDIMM applications SSTU32866 1.8-V 25-bit 1:1 or 14-bit 1:2 , SSTUH32864 1.8-V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with high output drive for DDR2 , PCKU878 1.8-V 1:10 differential zero-delay PLL clock buffer with fast lock time for DDR2 400-533 RDIMM , SSTUA32S865 1.8-V 28-bit 1:2 registered buffer with parity for DDR2 667 RDIMM applications SSTUA32866 1.8-V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 667 RDIMM
NXP Semiconductors
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DDR266 DDR333 DDR400 SSTUA32S868 DDR2 SSTL class SSTL_18 DDR2 SDRAM with SSTL_18 interface DDR1-400 TVSOP-48 PCK2059 PC100 PC133 PCK2509 PCK2510 DDR200

ky 202

Abstract: DDR2-533 with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a , 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Features DDR2 SDRAM VLP Mini-RDIMM , DDR2 SDRAM Module Density Part Number2 MT9HVF6472(P)KY-80E_ MT9HVF6472(P)KY-800_ MT9HVF6472(P , ,1 1Gb DDR2 SDRAM Module Density Part Number2 MT9HVF12872(P)KY-80E_ MT9HVF12872(P)KY , termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following
Micron Technology
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ky 202 244-P HVF9C64

DDR2-400

Abstract: DDR2-533 internal to the (SSTL_18) DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ , , along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM , and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and , 256MB: (x72, SR) 244-Pin DDR2 Mini-RDIMM Features DDR2 SDRAM Mini-RDIMM MT5HTF3272(P)K ­ 256MB , Timing Parameters ­ 256MB Base device: MT47H32M161, 512Mb DDR2 SDRAM Module Density Part Number2
Micron Technology
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PC-3200 MT47H32M16 MO-244

MT47H512M8

Abstract: PLL 567 center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the , Module voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) SDRAM access from , 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Features DDR2 SDRAM Mini-RDIMM MT18HTS25672(P)K ­ , Parameters ­ 2GB Modules Base Device: MT47H256M8THN,1 2Gb TwinDie DDR2 SDRAM Module Density 2GB 2GB Module , : MT47H512M8THM,1 4Gb TwinDie DDR2 SDRAM Module Density 4GB 4GB Module Bandwidth 5.3 GB/s 4.3 GB/s Memory Clock
Micron Technology
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MT47H512M8 PLL 567 MT18HTS51272 HTS18C256

DDR2 x32

Abstract: ELPIDA DDR2 TSOP(II)/FBGA Support x32-bit I/O 512Mb DDR2 SDRAM Elpida Memory has delivered the 512Mb DDR2 SDRAM with x32-bit I/O configuration samples. In the past a DDR2 controller with x32-bit wide interface required two x16-bit I/O DRAMs. Now, Elpida offers a 512Mb DDR2 SDRAM with x32-bit I/O configuration as a , DDR2 SDRAM Feature Comparison of DDR2 SDRAM, DDR SDRAM and SDRAM Items Clock frequency Transfer , die termination (ODT) Component package Lead-free DDR2 SDRAM 200/266/333/400/533MHz 400/533/667
Elpida Memory
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DDR2 x32 ELPIDA DDR2 Datasheet Unbuffered DDR2 SDRAM DIMM DDR2 layout 84 FBGA outline DDR2 SDRAM 200/266/333/400/533MH 400/533/667/800/1066M 100/133/166/200/250MH 200/266/333/400/500M 100/133/166MH DDR2-1066

SSTL-135

Abstract: ELPIDA DDR3 Family J: DDR3 E: DDR2 D: DDR SDRAM, DDR Mobile RAM Power Supply, Interface Organization Density / Bank S: SDRAM, (SDR) Mobile RAM X: XDR B: DDR2 Mobile RAM R: RDRAM ©Elpida Memory, Inc , information) Module Outline J: DDR3 Module Die Rev. (Mono) Power Supply, Interface E: DDR2 Module , Organization 04: x4 08: x8 16: x16 32: x32 Power Supply, Interface A: 1.8V, SSTL_18 ©Elpida Memory , Information*) Module Outline Die Rev. (Mono) Power Supply, Interface A: 1.8V, SSTL_18 F,W: 240
Elpida Memory
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SSTL-135 ELPIDA DDR3 ELPIDA mobile DDR ddr2 ram ELPIDA ddr3 so dimm 204 pin ECT-TS-1984 DDR3-1600J DDR3-1600K PC1600 166MH 100MH

U29B

Abstract: MT47H1GM4THM , along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM , and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and , Reserved Module voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) 10 , 16GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM Features DDR2 SDRAM RDIMM MT72HTS2G72(P) ­ 16GB , Micron without notice. 16GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM Features Table 2: Addressing
Micron Technology
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U29B MT47H1GM4THM U15B HTS72C2G

DDR2-400

Abstract: DDR2-533 is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules , 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM VLP RDIMM Features DDR2 VLP Registered DIMM (RDIMM , notice. ©2003 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM VLP , Parameters 1GB Modules Base Device: MT47H128M41, 512Mb DDR2 SDRAM Module Density Part Number2 , , ECC, SR) 240-Pin DDR2 SDRAM VLP RDIMM Pin Assignments and Descriptions Pin Assignments and
Micron Technology
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DDR2 SDRAM Meg x 4 x 9 banks

Abstract: MT47H512M8 , along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM , and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and , voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) 10 SDRAM access from , 2GB, 4GB (x72, DR) 244-Pin DDR2 VLP Mini-RDIMM Features DDR2 SDRAM VLP Mini-RDIMM MT18HVS25672 , and Timing Parameters ­ 2GB Modules Base device: MT47H256M8THN,1 2Gb TwinDie DDR2 SDRAM Module
Micron Technology
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MT18HVS51272 DDR2 SDRAM Meg x 4 x 9 banks DDR2 pin out DDR2 SDRAM Meg x 5 x 8 banks diode marking code 4n lm 35 dm 91 HVS18C256

MT16HTF25664H

Abstract: Z 667 ) activates and CKE (registered LOW) deactivates clocking (SSTL_18) circuitry on the DDR2 SDRAM. Input Input , termination: ODT (registered HIGH) enables termination resistance internal to the (SSTL_18) DDR2 SDRAM. When , with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a , 1GB, 2GB (x64, DR) 200-Pin Halogen-Free DDR2 SDRAM SODIMM Features DDR2 SDRAM SODIMM , (x64, DR) 200-Pin Halogen-Free DDR2 SDRAM SODIMM Features Table 2: Parameter Refresh count Row
Micron Technology
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MT16HTF25664H Z 667 ddr2 micron 200-P MT16HTF12864H MO-224 HTF16C128

JESD79-2

Abstract: JESD-79 DDR2 SDRAM memory interface that uses the data path provided with the Altera® ALTMEMPHY megafunction , interface with a DDR2 SDRAM memory interface. Figure 4 shows the configuration of the DDR2 SDRAM High , Corporation February 2007 400MHz DDR2 SDRAM Example DDR2 SDRAM memory interface with the ALTMEMPHY , devices have dedicated circuitry to interface with DDR and DDR2 SDRAM at speeds up to 200MHz/400Mbps and , , communications, and networking. Stratix® III devices support DDR and DDR2 SDRAM interfacing with dedicated DQS
Altera
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JESD79-2 JESD-79 Micron TN-47-01 DDR2 DIMM VHDL MT9HTF3272AY-80E JESD8-15A 800-EPLD

HYS72T512020HR-5-A

Abstract: DDR2 pcb layout Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply , Modules RDIMM DDR2 SDRAM RoHS Compliant Memory Products N e v e r s t o p t h i n k i n g , : mp_a4_s_rev312 / 3 / 2005-03-18 HYS72T512020HR­[3.7/5]­A Registered DDR2 SDRAM Modules Table of Contents , -pin Registered DDR2 SDRAM Modules product family and describes its main characteristics. 1.1 · · · · Features · 240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for PC, Workstation and Server
Infineon Technologies
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HYS72T512020HR-5-A DDR2 pcb layout DDR2-667C DDR2-667D DDR2-533C DDR2-400B 02012005-N6JU-ZWV6
Abstract: , along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM , and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and , 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM Features DDR2 SDRAM Registered DIMM (RDIMM , : www.micron.com/products/ddr2 Features · · · · · · · · · · · · · · · · · · · · · Supports 95°C with double , notice. 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM Features Figure 2: Module Part Numbers Example Micron Technology
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MT36HTF25672 82255977/S 3-HTF36C256
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