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DATA47

Catalog Datasheet MFG & Type PDF Document Tags

ADSP-21161 reference manual

Abstract: SIGNAL PATH designer Pull-Up 50K Pull-Up Notes: 1) When configured as DATA15-0, LKDATxy are I/O/T just like DATA47-16 2 , Buffer Threestatable Bus (ADDR23-0, DATA47-16) Enable Figure 2. ADSP-21161 I/O drivers containing , . External Port Interface ADDR23-0 , DATA47-16 : The address, data and select lines can be left floating if
Analog Devices
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EE-138 ADSP-21161 reference manual SIGNAL PATH designer

ADSST-Mel-100

Abstract: ADSST-SHARC-MEL-100 ­0 ADDR23­0 TIMEXP RPBA DATA47­16 ID2-0 RD WR LXCLK ACK LXACK MS3­0 LXDAT7­0 SERIAL DEVICE , . Figure 7. Analog Power (AVDD) Filter Circuit Program Booting ADDR23­0 DATA47­16 CLKIN RESET 3 ID2­0 CONTROL ADSP-21161 #2 ADDR23­0 DATA47­16 CLKIN Phased-Locked Loop and Crystal , ­0 ADDR DATA47­16 DATA CLKIN RESET 1 RD OE WR ID2­0 BOOT EPROM (OPTIONAL , following: · ADDR23­0, DATA47­0, BRST, CLKOUT. (Note that these pins have a logic level hold circuit
Analog Devices
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ADSST-Mel-100 ADSST-SHARC-MEL-100 K610 lcd sharc architecture block diagram EE-68 avr adc 48-BIT 225-B CA-225 ADSST-MEL-100 C03681

ADSP 21 XXX Sharc processor

Abstract: -21061 1 CLOCK TO GND CLKIN EBOOT 3 4 LBOOT IRQ2­0 FLAG3­0 TIMEXP ADDR31­0 DATA47­0 RD TCLK0 RCLK0 TFS0 , ADSP-21061 #5 ADSP-21061 #4 ADSP-21061 #3 CLKIN RESET RPBA 3 ID2­0 011 CONTROL ADDR31­0 DATA47­0 BR1­2, BR4­6 BR3 5 ADSP-21061 #2 CLKIN RESET RPBA 3 ID2­0 CONTROL 010 ADDR31­0 DATA47­0 CPA BR1, BR3­6 BR2 5 CONTROL ADSP-21061 #1 CLKIN RESET RPBA 3 ID2­0 ADDR31­0 DATA47­0 RDx , multiprocessing bus master is reading or writing its internal memory or IOP registers. DATA47­0 I/O/T External Bus
Analog Devices
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ADSP 21 XXX Sharc processor ADSP-21061/ADSP-21061L IPC-7351 SP-240-2 B-225-2 S-240 ADSP-21061KS-133

RPBA 01

Abstract: ADSP-21061LKSZ TIMEXP DATA47­0 DATA MEMORYMAPPED OE DEVICES WE (OPTIONAL) ACK RD SERIAL DEVICE , -21061 #6 ADSP-21061 #5 ADSP-21061 #4 ADDRESS ADSP-21061/ADSP-21061L ADDR31­0 DATA47­0 RPBA , DATA47­0 RPBA 3 ID2­0 CONTROL 010 CPA BR1, BR3­6 BR2 5 ADSP-21061 #1 CLKIN RESET ADDR31­0 ADDR DATA47­0 DATA RDx ID2­0 WRx ACK MS3­0 3 001 CONTROL RPBA , GND, except for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that have internal pull-up or pull-down
Analog Devices
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RPBA 01 ADSP-21061LKSZ sad diode marking b12 ADSP-21000 ADSP-21060 ADSP-21061L 61LKSZ-1601 ADSP-21061LAS-176 ADSP-21061LASZ-1761 ADSP-21061LKS-176 ADSP-21061LKSZ-1761 240-L

ADSST-21161N

Abstract: ADSST-SHARC-MELODY-ULTRA -0 BMS CS ADDR BRST DATA FLAG11­0 ADDR23­0 TIMEXP RPBA DATA47­16 ID2-0 RD WR LXCLK , 28 ADSST-SHARC-Melody-Ultra ADDR23­0 DATA47­16 CLKIN RESET 3 ID2­0 CONTROL ADSP-21161 #2 ADDR23­0 DATA47­16 CLKIN Host Processor Interface RESET General-Purpose I/O Ports , (OPTIONAL) ADDR DATA47­16 CLKIN CONTROL The SHARC Melody Ultra host interface enables easy , following: 2 4 5 6 7 8 KEY (NO PIN) BTMS BTCK · ADDR23­0, DATA47­0, BRST, CLKOUT
Analog Devices
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ADSST-21161N ADSST-SHARC-MELODY-ULTRA circle surround IC circle surround IC "analog devices" home theater printed circuit board ID200 40-BIT ADSST-21161NKCA100 ADSST-21161NCCA100 C03373

ADSP-21161N

Abstract: ADSP-21060 ) MEMORY DATA AND OE PERIPHERALS WE (OPTIONAL) ACK CS DATA47-16 RD WR LXCLK ACK LXACK MS3 , -21161N DATA47­16 47 40 39 32 31 DATA15­0 24 23 PROM BOOT 16 15 8 7 0 L1DATA7 , -21161N #3 CONTROL ADSP-21161N #4 CLOCK RESET ADDR23-0 DATA47-16 CLKIN RESET 3 ID2-0 CONTROL ADSP-21161N #2 CLKIN ADDR23-0 DATA47-16 RESET 2 ID2-0 CONTROL ADDR DATA ADSP-21161N #1 CS BMS ADDR23-0 ADDR DATA47-16 CLKIN DATA RESET 1 BOOT
Analog Devices
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ADSP-21062 ADSP-21160 ADSP21161N hbr audio MO-192-AAF-2 BC-225-1 ADSP-21161NKCA-100 ADSP-21161NCCA-100 ADSP-21161NKCAZ1002 ADSP-21161NCCAZ1002

0x00043fff

Abstract: BR ST DATA ADDR BOOT EPROM (OPTIONAL) ADDR23-0 DATA47-16 RD WR LXCLK ACK LXACK MS3 , -21161N DATA47­16 47 40 39 32 3 1 24 2 3 16 15 DATA15­0 8 7 L0DATA7­0 DA TA7­0 0 its own double-buffered input , ADDR23-0 DATA47-16 ADSP-21161N #2 CLKIN RESET 2 ID2-0 ADDR23-0 DATA47-16 CONTROL ADDR DATA CS BOOT EPROM (OPTIONAL) ADSP-21161N #1 BMS CLKIN RESET 1 ID2-0 ADDR23-0 DATA47-16 RD WR ACK MS3-0 SBT , or pull unused inputs to VDDEXT or GND, except for the following: · ADDR23­0, DATA47­0, BRST, CLKOUT
Analog Devices
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0x00043fff ADSP-21161NKCAZ100 ADSP-21161NCCAZ100 ADSP-21161NYCAZ110 D02935-0-1/13

ADSP-2106x

Abstract: and or host accesses the ADSP-2106x through its external port, via the external bus (DATA47-0 and ADDR31-0). , ADDR 31-0 48 Buffer I/O Address Bus (IOA) 32 DATA47-0 Ext. Port Address Bus (EPA , reference: external bus DATA47-0, ADDR31-0, RD, WR, MS3-0, BMS, ADRCLK, PAGE, SW, ACK, and SBTS signals , is in memory onto the external bus (DATA47-0). 16-to-32 01 Data In: ADSP-2106x ignores
Analog Devices
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ADSP-2106x and or monitor btc EPD controller ADSP-2106

sharc ADSP-21xxx general block diagram

Abstract: sharc ADSP-21xxx architecture diagram CONTROL For current information contact Analog Devices at (800) 262-5643 ADDR23-0 DATA47-16 CLKIN RESET 3 ID2-0 CONTROL ADSP-21161 #2 CLKIN ADDR23-0 DATA47-16 RESET 2 ID2-0 CONTROL ADDR DATA ADSP-21161 #1 CS BMS ADDR23-0 CLOCK ADDR DATA47-16 DATA , Scan · ADDR23­0, DATA47­16, BRST, CLKOUT (NOTE: These pins have a logic-level hold circuit enabled , level it was last driven. This latch is only enabled on the ADSP-21161N with ID2-0=00x. DATA47-16
Analog Devices
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sharc ADSP-21xxx general block diagram sharc ADSP-21xxx architecture diagram AG110 ADSP-21065L interrupt Assembly sharc

ad14060lbf

Abstract: AD14060 BUS (ADDR31­0, DATA47­0, MS3-0, RD, WR, PAGE, ADRCLK, , SW, ACK, SBTS, HBR, HBG, REDY, BR , RPBA , A mA pF Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, STBS , bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy , three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG , for ADDR31-0, RD, WR, MS3-0, SW, PAGE, DATA47-0, and ACK also apply. Table 15. Specifications 5V
Analog Devices
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ad14060lbf AD14060 AD14060L lA1d ADSP-20160 22760a AD14060/AD14060L 308-L QS-308 AD14060BF-4 AD14060LBF-4 C00667

adsp 210xx architecture diagram

Abstract: ADDS-2106x-EZ-Lite 1x CLOCK DATA BOOT EPROM (OPTIONAL) Flexible Instruction Set ADDR31-0 ADDR DATA47-0 , -21061L ADDR31-0 CLKIN DATA47-0 RESET RPBA 011 3 ID 2-0 CONTROL CPA BR1-2, BR4-6 BR3 5 ADSP-2106x #2 CLKIN RESET ADDR31-0 DATA47-0 RPBA 3 010 ID 2-0 CONTROL CPA BR1, BR3 , CONTROL ADDR DATA47-0 DATA OE WE ACK CS RD WR ACK MS3-0 CS BMS PAGE SBTS SW , for ADDR31-0 , DATA47-0 , FLAG3-0, SW and inputs that have internal pull-up or pull-down resistors
Analog Devices
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adsp 210xx architecture diagram ADDS-2106x-EZ-Lite 1024-P ADSP-21061KS-160 ADSP-21061KS-200 ADSP-21061LKS-160 ADSP-21061LAS-160 ADSP-21061LKB-160

ADSP 21 XXX Sharc processor

Abstract: ADSP-21060 reference manual ) (OPTIONAL) FLAG3­0 ADDR31­0 ADDR TIMEXP DATA47­0 DATA MEMORYMAPPED OE DEVICES WE , -21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADDR31­0 DATA47­0 RPBA 3 ID2­0 CONTROL 011 BR1­2, BR4­6 5 BR3 ADSP-2106x #2 CLKIN ADDR31­0 RESET DATA47­0 RPBA 3 ID2­0 CONTROL 010 CPA BR1, BR3­6 BR2 5 ADSP-2106x #1 CLKIN RESET ADDR31­0 ADDR DATA47­0 , or pulled to VDD or GND, except for ADDR31-0, DATA47-0, FLAG3-0, and inputs that have internal
Analog Devices
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ADSP-21060 reference manual tms 1601 ADSP-21060 REV E code marking h06 sharc iir filter M1543 QS-240-1 QS-240-2 D00167-0-11/07

csc 9803

Abstract: QML-38534 Dins: DATA47-0, ADDR31 -0, RD, WR, SW, ACK, SBTS, IRQv2-0, FLAGvO, FLAG1, FLAGv2, HBG, CSv , . Electrical performance characteristics - Continued. 4/ Applies to output and bidirectional pins: DATA47-0 , / Applies to CPAy pin. _ _ 15/ Applies to bussed three statable pins and bidirectional pins: DATA47-0 , 1, TFS enable and TFS valid follow, tpDTLFSE and tppjEMFS- _ â'" _ _ _ 54/ System inputs = DATA47-0 , , RESET. _ _ _ _ _ 55/ System outputs = DATA47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG
-
OCR Scan
QML-38534 csc 9803 CE7Y BMS SYSTEM qualification LA4-DA 32-BIT 5962-E063-99 AD14060LBF/QML-4 5962-9750702HXC AD14060LTF/QML-4

ADSP 21 XXX Sharc processor

Abstract: ADSP-21060 reference manual benchmarks for the ADSP-2106x. 3 4 ADDR LBOOT DATA IRQ2­0 ADDR31­0 ADDR DATA47­0 , - ADDR31­0 DATA47­0 RPBA 3 ID2­0 CONTROL 011 BR1­2, BR4­6 5 BR3 ADSP-2106x #2 CLKIN ADDR31­0 RESET DATA47­0 RPBA 3 , DATA47­0 DATA RDx ID2­0 WRx ACK MS3­0 3 001 CONTROL RPBA OE WE ACK CS , TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR31­0, DATA47­0
Analog Devices
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Analog devices marking Information 74 HTC 00 ADSP filter algorithm implementation ADSP-21062KSZ-133 outline of the heat slug for JEDEC SHARC 21060 QS-240-2A QS-240-1A QS-240-1B QS-240-2B D00167-0-8/10

LSK 331

Abstract: QML-38534 pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQy2-0, FLAGyO, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2 , . _ _ _ Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK , : DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG1, HBG, REDY, DMAG1, DMAG2, BMSBCD, TFSO , and_tQQjENps- _ _ _ _ _ 57/ System inputs = DATA47-0, ADDR31-0, RD,"WR, ACK, SBTS, SW,"FTBR, HBG, CS, DMAR1 , , LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. _ _ 58/ System outputs = DATA47-0, ADDR31
-
OCR Scan
LSK 331 5962-E083-99 MIL-HDBK-103 AD14060BF/QML-4 5962-9750602HXC AD14060TF/QML-4

ADSP-21060 simulator program download

Abstract: ADSP-21060 reference manual -0 FLAG3-0 TIMEXP BMS ADDR31-0 DATA47-0 The ADSP-2106x SHARC represents a new standard of , ADDRESS ADSP-21060/ADSP-21060L ADDR31-0 CLKIN DATA47-0 RESET RPBA 011 3 ID 2-0 CONTROL CPA BR1-2, BR4-6 BR3 5 ADSP-2106x #2 CLKIN ADDR31-0 RESET DATA47-0 RPBA , RESET RPBA 3 001 ID 2-0 ADDR31-0 ADDR DATA47-0 DATA RD WR ACK MS3-0 OE WE , for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that have internal pull-up or pull-down resistors
Analog Devices
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ADSP-21060 simulator program download SIMULATOR 4...20 mA ADSP21060 DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER ADSP21000 ADSP-21060L ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060KB-160 ADSP-21060LKS-133 ADSP-21060LKS-160 ADSP-21060LKB-160

ADSP-21060 reference manual

Abstract: ADSP-21060 -0 FLAG3-0 TIMEXP BMS ADDR31-0 DATA47-0 The ADSP-2106x SHARC represents a new standard of , ADDRESS ADSP-21060/ADSP-21060L ADDR31-0 CLKIN DATA47-0 RESET RPBA 011 3 ID 2-0 CONTROL CPA BR1-2, BR4-6 BR3 5 ADSP-2106x #2 CLKIN ADDR31-0 RESET DATA47-0 RPBA , RESET RPBA 3 001 ID 2-0 ADDR31-0 ADDR DATA47-0 DATA RD WR ACK MS3-0 OE WE , for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that have internal pull-up or pull-down resistors
Analog Devices
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Tck12 C3165 225-P ADSP-21060LAB-160

sharc ADSP-21xxx general block diagram

Abstract: ADSP-21xxx PERIPHERALS WE (OPTIONAL) ACK CS DATA47-16 RD WR LXCLK ACK LXACK MS3-0 LXDAT7-0 SERIAL , external memory banks, with up to all four banks mapped to SDRAM. DATA47­16 47 40 39 32 31 24 , ADDRESS ADSP-21161N #3 CONTROL ADSP-21161N #4 CLOCK RESET ADDR23-0 DATA47-16 CLKIN RESET 3 ID2-0 CONTROL ADSP-21161N #2 CLKIN ADDR23-0 DATA47-16 RESET 2 ID2-0 CONTROL ADDR DATA ADSP-21161N #1 CS BMS ADDR23-0 ADDR DATA47-16 CLKIN DATA
Analog Devices
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ADSP-21xxx most sharc ADSP-21xxx sharc ADSP-21xxx architecture, INSTRUCTION SET, A C02935
Abstract: RCLK0 TF S0 RSF0 DT0 DR0 TCLK1 RCLK1 TF S1 RSF1 DT1 DR1 RPBA ID2­0 RESET ADDR31­0 DATA47­0 RD WR ACK MS3 , ADSP-2106x #3 CLKIN RESET RPBA 3 ID2­0 011 CONTROL ADDR31­0 DATA47­0 BR1­2, BR4­6 BR3 5 ADSP-2106x #2 CLKIN RESET RPBA 3 ID2­0 CONTROL 010 ADDR31­0 DATA47­0 CPA BR1, BR3­6 BR2 5 CONTROL AD SP-2106x #1 CLKIN RESET RPBA 3 ID2­0 ADDR31­0 DATA47­0 RDx CONTROL DATA DATA ADDR DATA OE , to VDD or GND, except for ADDR31­0, DATA47­0, FLAG3­0, and inputs that have internal pull-up or Analog Devices
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CSZ-160 ADSP-21062LKSZ-133 ADSP-21062LKS-160 ADSP-21062LKSZ-160 ADSP-21062LKB-160 ADSP-21062LKBZ-160
Abstract: SERIAL DEVICE (OPTIONAL) TCLK1 RCLK1 TFS1 RFS1 DT1 DR1 RPBA ID2-0 RESET ADDR DATA47-0 , -21060C/ADSP-21060LC ADDR31-0 CLKIN DATA47-0 RESET RPBA 011 3 ID 2-0 CONTROL CPA BR1-2, BR4-6 5 BR3 ADSP-2106x #2 CLKIN RESET ADDR31-0 DATA47-0 RPBA 3 010 ID 2-0 , -0 RPBA 001 3 ID 2-0 CONTROL ADDR DATA47-0 DATA OE WE ACK CS RD WR ACK MS3 , for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that have internal pull-up or pull-down resistors Analog Devices
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ADSP-21060C/ADSP-21060LC QS-240A C3350 ADSP-21060CZ-133 ADSP-21060CZ-160 ADSP-21060CW-133

627M

Abstract: sharc ADSP-21xxx general block diagram (OPTIONAL) DATA47-16 RD WR LXCLK ACK LXACK MS3-0 LXDAT7-0 SCLK0 FS0 D0A D0B SCLK1 FS1 D1A D1B SCLK2 FS2 , -0 DATA47-16 ADSP-21161 #2 CLKIN RESET 2 ID2-0 ADDR23-0 DATA47-16 CONTROL ADDR DATA CS BOOT EPROM (OPTIONAL) ADSP-21161 #1 BMS CLKIN RESET 1 ID2-0 ADDR23-0 DATA47-16 RD WR ACK MS3-0 SBTS ADDR , : · ADDR23­0, DATA47­0, BRST, CLKOUT (NOTE: These pins have a logic-level hold circuit enabled on the , -0 I/O/T DATA47-16 I/O/T MS3-0 I/O/T RD I/O/T WR I/O/T External Bus Address
Analog Devices
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627M schottky k04 21161n PIN HEADER 4X1, 2.54 pitch Pin Header 225-L MO-151 C02935-0-7/02

TCA 875

Abstract: TCA600 ADSP-2106x. 3 4 ADDR LBOOT DATA IRQ2­0 ADDR31­0 ADDR DATA47­0 DATA , -21060C/ADSP-21060LC ADDR31­0 DATA47­0 RPBA 3 ID2­0 CONTROL 011 BR1­2, BR4­6 5 BR3 ADSP-2106x #2 CLKIN ADDR31­0 RESET DATA47­0 RPBA 3 ID2­0 CONTROL 010 CPA BR1, BR3­6 BR2 5 ADSP-2106x #1 CLKIN RESET ADDR31­0 ADDR DATA47­0 DATA RPBA ID2 , TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR31­0, DATA47
Analog Devices
Original
TCA 875 TCA600 VIH22 ADSP-21060C ADSP-21060LC ADSP-21062L D00167-0-3/08

LVC1284

Abstract: hct1284 input and bi-directional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQy2-0, FLAGy0, FLAG1 , to input pins: CLKIN, RESET,TRST. 4/ Applies to output and bi-directional pins: DATA47-0, ADDR31 , CPAy pin. 15/ Applies to bussed three statable pins and bi-directional pins: DATA47-0, ADDR31-0, MS3
Philips Semiconductors
Original
LVC1284 hct1284 nack logic control ic 74HCT1284 74LVC1284 act 1284

PCA82C250T

Abstract: EPROM (OPTIONAL) ADDR DATA47-0 RD WR ACK MS3-0 PAGE SBTS SW ADRCLK OE WE ACK CS , -0, DATA47-0, FLAG3-0, SW, and inputs that have internal pullup or pulldown resistors (CPA, ACK, DTx, DRx , . DATA47-0 I/O/T External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these , word sizes are transferred over the external port. DATA47-0 47 40 32 24 16 8 0 , : DATA47-0 I/O/T SBTS I/S IRQ2-0 I/A FLAG3-0 I/O/A TIMEXP O HBR I/A CS I Tristate Input
Inicore
Original
PCA82C250T
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