DAC707 DAC708 DAC709 16-BIT DAC707JP/KP DAC708/709 DAC707/708/709 PDS-557H - Datasheet Archive

 

DAC708 DAC709 ® Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS q HIGH ACCURACY: Linearity Error ±0.003%

 

DAC707 DAC707 DAC708 DAC708 DAC709 DAC709 ® Microprocessor-Compatible 16-BIT 16-BIT DIGITAL-TO-ANALOG CONVERTERS q HIGH ACCURACY: Linearity Error ±0.003% of FSR max Differential Linearity Error ±0.006% of FSR max q MONOTONIC (TO 14 BITS) OVER SPECIFIED TEMPERATURE RANGE q HERMETICALLY SEALED FEATURES q TWO-CHIP CONSTRUCTION q HIGH-SPEED 16-BIT 16-BIT PARALLEL, 8-BIT (BYTE) PARALLEL, AND SERIAL INPUT MODES q DOUBLE-BUFFERED INPUT REGISTER CONFIGURATION q VOUT AND IOUT MODELS q LOW COST PLASTIC VERSIONS AVAILABLE (DAC707JP/KP DAC707JP/KP) DESCRIPTION The DAC708 DAC708 and DAC709 DAC709 are 16-bit converters designed to interface to an 8-bit microprocessor bus. 16bit data is loaded in two successive 8-bit bytes into parallel 8-bit latches before being transferred into the D/A latch. The DAC708 DAC708 and DAC709 DAC709 are current and voltage output models respectively and are in 24-pin hermetic DIPs. Input coding is Binary Two's Complement (bipolar) or Unipolar Straight Binary (unipolar, when an external logic inverter is used to invert the MSB). In addition, the DAC708/709 DAC708/709 can be loaded serially (MSB first). Data is written into a 16-bit latch and subsequently the D/A latch. The DAC707 DAC707 has bipolar voltage output and input coding is Binary Two's Complement (BTC). All models have Write and Clear control lines as well as input latch enable lines. In addition, DAC708 DAC708 and DAC709 DAC709 have Chip Select control lines. In the bipolar mode, the Clear input sets the D/A latch to give zero voltage or current output. They are all 14-bit accurate and are complete with reference, and for the DAC707 DAC707, and DAC709 DAC709, a voltage output amplifier. All models are available with an optional burn-in screening. The DAC707 DAC707 is designed to interface to a 16-bit bus. 8-Bit (DAC708 DAC708, 709) or 16-Bit (DAC707 DAC707) Serial (DAC708 DAC708, 709) Latch Enables/ Mode Select CLEAR WRITE CHIP SELECT Reference Circuit High Byte Latch D/A Latch Serial Data Low Byte Latch 16-Bit D/A Converter Bipolar Offset Summing Junction (708, 709) 10V Range (708, 709) VOUT DAC707 DAC707 or DAC709 DAC709 Only Control Logic DAC707/708/709 DAC707/708/709 Block Diagram International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111 · Twx: 910-952-1111 Internet: http://www.burr-brown.com/ · FAXLine: (800) 548-6133 (US/Canada Only) · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132 PDS-557H PDS-557H SBAS145 SBAS145 SPECIFICATIONS ELECTRICAL At TA = +25°C, VCC = ±15V, VDD = +5V, and after a 10-minute warm-up, unless otherwise noted. DAC707/708/709KH DAC707/708/709KH, DAC707KP DAC707KP DAC707JP DAC707JP PRODUCT MIN TYP MAX MIN TYP MAX DAC707/708/ DAC707/708/ 709BH 709BH, SH MIN TYP MAX UNITS * Bits * * * * V V µA µA * * ±0.0015 ±0.05 * * * ±0.003 ±0.10 * % of FSR(4) % of FSR % of FSR % % of FSR Bits % of FSR/%VCC % of FSR/%VDD INPUT DIGITAL INPUT Resolution Bipolar Input Code (all models) Unipolar Input Code(1) (DAC708/709 DAC708/709 only) Logic Levels(2): VIH VIL IIH (VI = +2.7V) IIL (VI = +0.4V) 16 Binary Two's Complement +2.0 ­1.0 * * Unipolar Straight Binary * * * * * * +5.5 +0.8 1 1 * * * * TRANSFER CHARACTERISTICS ACCURACY(3) Linearity Error Differential Linearity Error(5) at Bipolar Zero(5, 6) Gain Error(7) Zero Error(7) Monotonicity Over Spec Temp Range Power Supply Sensitivity: +VCC, ­VCC VDD ±0.003 ±0.0045 ±0.006 ±0.012 ±0.0015 ±0.003 ±0.003 * * ±0.003 ±0.006 ±0.006 ±0.15 * ±0.07 ±0.05 ±0.30 ±0.1 ±0.0015 ±0.0001 ±0.006 ±0.001 * * * * * * ±0.003 * ±30 * * * ±2.5 * ±0.15 ±25 ±25 ±5 ±12 +0.009, ­0.006 ±0.006 * * ±7 ±1.5 ±4 ±0.10 ±15 ±15 ±3 ±10 * 8 4 * * * 13 DRIFT (Over Spec Temp Range(3) Total Error Over Temp Range(8) Total Full Scale Drift Gain Drift Zero Drift: Unipolar (DAC708/709 DAC708/709 only) Bipolar (all models) Differential Linearity Over Temp(5) 14 ±0.08 ±10 ±10 ±5 ±15 ±0.012 14 ±0.012 Linearity Error Over Temp(5) SETTLING TIME (to ±0.003% of FSR)(9) Voltage Output Models Full Scale Step (2k load) 1LSB Step at Worst Case Code(10) Slew Rate Current Output Models Full Scale Step (2mA): 10 to 100 Load 1k Load 4 2.5 10 * * * * 8 4 % of FSR ppm of FSR/°C ppm/°C ppm of FSR/°C ppm of FSR/°C % of FSR % of FSR µs µs V/µs 350 1 * * ns µs 0 to +10 ±5, ±10 * * * * V V V mA OUTPUT VOLTAGE OUTPUT MODELS Output Voltage Range DAC709 DAC709: Unipolar (USB Code) Bipolar (BTC Code) DAC707 DAC707 Bipolar (BTC Code) Output Current Output Impedance Short Circuit to Common Duration ±5 ±10 * 0.15 Indefinite * * * 0 to ­2 ±1 4.0 2.45 ±2.5 CURRENT OUTPUT MODELS Output Current Range (±30% typ) DAC708 DAC708: Unipolar (USB Code) Bipolar (BTC Code) Unipolar Output Impedance (±30% typ) Bipolar Output Impedance (±30% typ) Compliance Voltage * * * * * * * mA mA k k V The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC707/708/709 DAC707/708/709 2 ELECTRICAL (CONT) At TA = +25°C, VCC = ±15V, VDD = +5V, and after a 10-minute warm-up, unless otherwise noted. DAC707/708/709KH DAC707/708/709KH, DAC707KP DAC707KP DAC707JP DAC707JP PRODUCT DAC707/708/ DAC707/708/ 709BH 709BH, SH MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS +13.5 ­13.5 +4.5 +15 ­15 +5 +16.5 ­16.5 +5.5 * * * * * * * * * * * * * * * * * * V V V +10 ­13 +5 * * * +25 ­25 +10 * * * * * * * * * * * * * * * mA mA mA mA mA mA 370 * 800 950 * * * * mW mW ­25 +85 ­55 ­65 +125 +150 °C °C °C °C °C POWER SUPPLY REQUIREMENTS Voltage (all models): +VCC ­VCC VDD Current (No Load, +15V Supplies) Current Output Models: +VCC ­VCC VDD Voltage Output Models: +VCC ­VCC VDD +16 ­18 +5 Power Dissipation (±15V supplies) Current Output Models Voltage Output Models +30 ­30 +10 535 TEMPERATURE RANGE Specification: BH Grades JP, KP, KH Grades SH Grades Storage: Ceramic Plastic 0 +70 * +100 ­60 * ­65 * +150 * *Specification same as for models in column to the left. NOTES: (1) MSB must be inverted externally prior to DAC708/709 DAC708/709 input. (2) Digital inputs are TTL, LSTTL, 54/74C 54/74C, 54/74HC 54/74HC and 54/74HTC 54/74HTC compatible over the specified temperature range. (3) DAC708 DAC708 (current-output models) are specified and tested with an external output operational amplifier connected using the internal feedback resistor in all tests. (4) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (5) ±0.0015% of Full Scale Range is equal to 1 LSB in 16-bit resolution, ±0.003% of Full Scale Range is equal to 1 LSB in 15-bit resolution. ±0.006% of Full Scale Range is equal to 1 LSB in 14-bit resolution. (6) Error at input code 0000H 0000H. (For unipolar connection on DAC708/709 DAC708/709, the MSB must be inverted externally prior to D/A input.) (7) Adjustable to zero with external trim potentiometer. Adjusting the gain potentiometer rotates the transfer function around the bipolar zero point. (8) With gain and zero errors adjusted to zero at +25°C. (9) Maximum represents the 3 limit. Not 100% tested for this parameter. (10) The bipolar worst-case code change is FFFFH to 0000H 0000H and 0000H 0000H to FFFFH. For unipolar (DAC708/709 DAC708/709 only) it is 7FFFH to 8000H 8000H and 8000H 8000H to 7FFFH. PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) DAC707JP DAC707JP DAC707KP DAC707KP 28-Pin Plastic DBL Wide DIP 28-Pin Plastic DBL Wide DIP 215 215 DAC707BH DAC707BH 28LD Side Brazed Hermetic Dip 28LD Side Brazed Hermetic DIP 28LD Side Brazed Hermetic DIP 149 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 165 DAC707KH DAC707KH DAC707SH DAC707SH DAC708BH DAC708BH DAC708KH DAC708KH DAC708SH DAC708SH DAC709BH DAC709BH DAC709KH DAC709KH DAC709SH DAC709SH 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP VDD to COMMON . 0V, +15V +VCC to COMMON . 0V, +18V ­VCC to COMMON . 0V, ­18V Digital Data Inputs to COMMON . ­0.5V, VDD +0.5 DC Current any input . ±10mA Reference Out to COMMON . Indefinite Short to COMMON VOUT (DAC707 DAC707, DAC709 DAC709) . Indefinite Short to COMMON External Voltage Applied to RF (pin 13 or 14, DAC708 DAC708) . ±18V External Voltage Applied to D/A Output (pin 1, DAC707 DAC707; pin 14, DAC709 DAC709) . ±5V Power Dissipation . 1000mW Storage Temperature . ­60°C to +150°C Lead Temperature (soldering, 10s) . 300°C 149 149 165 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 165 165 ELECTROSTATIC DISCHARGE SENSITIVITY 165 165 This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® 3 DAC707/708/709 DAC707/708/709 ORDERING INFORMATION PRODUCT TEMPERATURE RANGE INPUT CONFIGURATION OUTPUT CONFIGURATION DAC707JP DAC707JP DAC707JP-BI DAC707JP-BI(1) DAC707KP DAC707KP DAC707KP-BI DAC707KP-BI(1) DAC707KH DAC707KH DAC707KH-BI DAC707KH-BI(1) DAC707BH DAC707BH DAC707BH-BI DAC707BH-BI(1) DAC707SH DAC707SH DAC707SH-BI DAC707SH-BI(1) 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C ­25°C to +85°C ­25°C to +85°C ­55°C to +125°C ­55°C to +125°C 16-bit port 16-bit port 16-bit port 16-bit port 16-bit port 16-bit port 16-bit port 16-bit port 16-bit port 16-bit port ±10V output ±10V output ±10V output ±10V output ±10V output ±10V output ±10V output ±10V output ±10V output ±10V output DAC708KH DAC708KH DAC708BH DAC708BH DAC708SH DAC708SH 0°C to +70°C ­25°C to +85°C ­55°C to +125°C 8-bit port 8-bit port 8-bit port ±1mA output ±1mA output ±1mA output DAC709KH DAC709KH DAC709BH DAC709BH DAC709SH DAC709SH 0°C to +70°C ­25°C to +85°C ­55°C to +125°C 8-bit port 8-bit port 8-bit port ±10V output ±10V output ±10V output NOTE: (1) 25 piece minimum order. CONNECTION DIAGRAMS DAC708/709 DAC708/709 A2 Register Enable Lines A0 A1 D7 (D15) 24 2 23 3 22 4 D6 (D14) High Byte Latch 5 D5 (D13) 21 7 D3 (D11) Low Byte Latch 8 D2 (D10) 16-Bit Reference Circuit Ladder Resistor Network and Current Switches D/A Latch 6 D4 (D12) Data Inputs 1 18 17 16 15 DAC709 DAC709 Only 11 DCOM 14 10k 12 V OUT DAC707 DAC707 (2) 2 DCOM 3.9M 270k BPO SJ ACOM (1) +VCC + Gain Adjust 3.9M + (1) (2) (2) + Offset Adjust VOUT Connect for bipolar operation. R F2 Connect for 10V range. Leave pin 13 open for 20V range. 28 D0 (LSB) 27 D1 RF 25 D3 24 D4 23 D5 22 D6 8 CC 26 D2 7 CC ­V (2) +V 270k GA 6 GA Gain Adjust +VCC 5 (1) +VCC ­VCC ­VCC 4 SJ (3) CLR 3 ACOM Analog Common NOTES: (1) Potentiometer is 10k to 100k . (2) Decoupling capcitors are 0.1µF to 1.0µF. Control Lines 1 V DD VDD Offset Adjust 13 10k WR VDD + (2) CS (3) 10 D0 (D8)/S1 ­VCC 19 9 D1 (D9) Digital Common 20 VDD 21 D7 (2) 16-Bit Ladder Resistor Network and Current Switches WR 10 A1 11 A0 12 (MSB) D15 13 16 D12 D14 14 15 D13 Latch Enable Lines Input Latch 9 D/A Latch CLR Control Lines 20 D8 19 D9 18 D10 17 D11 Digital Inputs NOTES: (1) Potentiometers are 10k to 100k . (2) Decoupling capcitors are 0.1µF to 1.0µF. (3) Bypass, 0.0022µF to 0.01µF. ® DAC707/708/709 DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN FUNCTIONS DAC707 DAC707 Pin DESCRIPTION DESIGNATOR # DAC708/709 DAC708/709 DESIGNATOR DESCRIPTION VOUT Voltage output for DAC707 DAC707 (±10V) 1 A2 Latch enable for D/A latch (Active low) VDD Logic supply (+5V) 2 A0 Latch enable for "low byte" input (Active low). When both A0 and A1 are logic "0", the serial input mode is selected and the serial input is enabled. DCOM Digital common 3 A1 Latch enable for "high byte" input (Active low). When both A0 and A1 are logic "0", the serial input mode is selected and the serial input is enabled. ACOM Analog common 4 D7 (D15) Input for data bit 7 if enabling low byte (LB) latch or data bit 15 if enabling the high byte (HB) latch. SJ Summing junction of the internal output op amp for the DAC707 DAC707. Offset adjust circuit is connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14) Input for data bit 6 if enabling LB latch or data bit 14 if enabling the HB latch. GA Gain adjust pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data bit 13 (HB) +VCC Positive supply voltage (+15V) 7 D4 (D12) Data bit 4 (LB) or data bit 12 (HB) ­VCC Negative supply voltage (­15V) 8 D3 (D11) Data bit 3 (LB) or data bit 11 (HB) CLR Clear line. Sets the input latch to zero and sets the D/A latch to the input code that gives bipolar zero on the D/A output (Active low) 9 D2 (D10) Data bit 2 (LB) or data bit 10 (HB) WR Write control line (Active low) 10 D1 (D9) Data bit 1 (LB) or data bit 9 (HB) A1 Enable for D/A converter latch (Active low) 11 D0 (D8)/SI Data bit 0 (LB) or data bit 8 (HB). Serial input when serial mode is selected. A0 Enable for input latch (Active low) 12 DCOM Digital common D15 (MSB) Data bit 15 (Most Significant Bit) 13 RF2 Feedback resistor for internal or external operational amplifier. Connect to pin 14 when a 10V output range is desired. Leave open for a 20V output range. D14 Data bit 14 14 VOUT RF1 (DAC708 DAC708) Voltage output for DAC709 DAC709 or feedback resistor for use with an external output op amp for the DAC708 DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 DAC708. D13 Data bit 13 15 ACOM Analog common D12 Data bit 12 16 SJ (DAC709 DAC709) IOUT (DAC708 DAC708) Summing junction of the internal output op amp for the DAC709 DAC709, or the current output for the DAC708 DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 DAC708. D11 Data bit 11 17 BPO Bipolar offset. Connect to pin 16 when operating in the bipolar mode. Leave open for unipolar mode. D10 Data bit 10 18 GA Gain adjust pin D9 Data bit 9 19 +VCC Positive supply voltage (+15V) D8 Data bit 8 20 ­VCC Negative supply voltage (­15V) D7 Data bit 7 21 CLR Clear line. Sets the high and low byte input registers to zero and, for bipolar operation, sets the D/A register to the input code that gives bipolar zero on the D/A output. (In the unipolar mode, invert the MSB prior to the D/A.) D6 Data bit 6 22 WR Write control line D5 Data bit 5 23 CS Chip select control line D4 Data bit 4 24 VDD Logic supply (+5V) D3 Data bit 3 25 No pin D2 Data bit 2 26 No pin D1 Data bit 1 27 No pin D0 (LSB) Data bit 0 (Least Significant Bit) 28 No pin (The DAC708 DAC708 and DAC709 DAC709 are in 24-pin packages) ® 5 DAC707/708/709 DAC707/708/709 DISCUSSION OF SPECIFICATIONS the MSB must be inverted). This code corresponds to zero volts (DAC707 DAC707 and DAC709 DAC709) or zero milliamps (DAC708 DAC708) at the analog output. The maximum change in offset at tMIN or tMAX is referenced to the zero error at +25°C and is divided by the temperature change. This drift is expressed in FSR/ °C. DIGITAL INPUT CODES For bipolar operation, the DAC707/708/709 DAC707/708/709 accept positivetrue binary two's complement input code. For unipolar operation (DAC708/709 DAC708/709 only) the input code is positive-true straight-binary provided that the MSB input is inverted with an external inverter. See Table I. SETTLING TIME Settling time of the D/A is the total time required for the analog output to settle within an error band around its final value after a change in digital input. Refer to Figure 1 for typical values for this family of products. ANALOG OUTPUT Unipolar Straight Binary(1) (DAC708/709 DAC708/709 only; connected for Unipolar operation) Binary Two's Complement (Bipolar operation; all models) 7FFFH 0000H 0000H FFFFH 8000H 8000H +1/2 Full Scale ­1LSB(2) Zero +Full Scale +1/2 Full Scale +Full Scale Zero ­1LSB ­Full Scale Final-Value Error Band Percent of Full-Scale Range (±% of FSR) Digital Input Codes NOTES: (1) MSB must be inverted externally. (2) Assumes MSB is inverted externally. TABLE I. Digital Input Codes. ACCURACY Linearity This specification describes one of the most important measures of performance of a D/A converter. Linearity error is the deviation of the analog output from a straight line drawn through the end points (­Full Scale point and +Full Scale point). DAC707 DAC707 DAC709 DAC709 DAC708 DAC708 0.1 R L = 100 0.01 R L = 1k 0.001 0.01 0.1 1 10 Settling Time (µs) FIGURE 1. Final-Value Error Band Versus Full-Scale Range Settling Time. Differential Linearity Error Differential Linearity Error (DLE) of a D/A converter is the deviation from an ideal 1LSB change in the output when the input changes from one adjacent code to the next. A differential linearity error specification of ±1/2LSB means that the output step size can be between 1/2LSB and 3/2LSB when the input changes between adjacent codes. A negative DLE specification of ­1LSB maximum (­0.006% for 14-bit resolution) insures monotonicity. Voltage Output Settling times are specified to ±0.003% of FSR (±1/2LSB for 14 bits) for two input conditions: a full-scale range change of 20V (±10V) or 10V (±5V or 0 to 10V) and a 1LSB change at the "major carry", the point at which the worstcase settling time occurs. (This is the worst-case point since all of the input bits change when going from one code to the next.) Monotonicity Monotonicity assures that the analog output will increase or remain the same for increasing input digital codes. The DAC707/708/709 DAC707/708/709 are specified to be monotonic to 14 bits over the entire specification temperature range. Current Output Settling times are specified to ±0.003% of FSR for a fullscale range change for two output load conditions: one for 10 to 100 and one for 1000. It is specified this way because the output RC time constant becomes the dominant factor in determining settling time for large resistive loads. DRIFT Gain Drift Gain Drift is a measure of the change in the full-scale range output over temperature expressed in parts per million per degree centigrade (ppm/°C). Gain drift is established by: (1) testing the end point differences at tMIN, +25°C and tMAX; (2) calculating the gain error with respect to the +25°C value; and (3) dividing by the temperature change. COMPLIANCE VOLTAGE Compliance voltage applies only to current output models. It is the maximum voltage swing allowed on the output current pin while still being able to maintain specified accuracy. POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a change in a power supply voltage on the D/A converter Zero Drift Zero Drift is a measure of the change in the output with 0000H 0000H applied to the D/A converter inputs over the specified temperature range. (For the DAC708/709 DAC708/709 in unipolar mode, ® DAC707/708/709 DAC707/708/709 1 6 Zero Adjustment % of FSR Error Per % of Change in VSUPPLY output. It is defined as a percent of FSR change in the output per percent of change in either the positive supply (+VCC), negative supply (­VCC) or logic supply (VDD) about the nominal power supply voltages (see Figure 2). It is specified for DC or low frequency changes. The typical performance curve in Figure 2 shows the effect of high frequency changes in power supply voltages. For unipolar (USB) configurations, apply the digital input code that produces zero voltage or zero current output and adjust the zero potentiometer for zero output. For bipolar (BTC) configurations, apply the digital input code that produces zero output voltage or current. See Table II for corresponding codes and connection diagrams for zero adjustments circuit connections. Zero calibration should be made before gain calibration. 0.030 Gain Adjustment 0.025 Apply the digital input that gives the maximum positive output voltage. Adjust the gain potentiometer for this positive full-scale voltage. See Table II for positive full-scale voltages and the Connection Diagrams for gain adjustment circuit connections. ­15V Supply 0.020 0.015 +5V Supply 0.010 +15V Supply 0.005 Range of Gain Adjust 0 1 10 100 1k 10k + Full Scale 100k Power Supply Ripple Frequency (Hz) OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS For optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the Connection Diagram. 1µF tantalum capacitors should be located close to the D/A converter. Full Scale Range Analog Output 1LSB FIGURE 2. Power Supply Rejection Versus Power Supply Ripple Frequency. Range of Zero Adjust Gain Adjust Rotates the Line Input = 0000 H Input = FFFFH Digital Input Zero Adjust Translates the Line EXTERNAL ZERO AND GAIN ADJUSTMENT FIGURE 4. Relationship of Zero and Gain Adjustments for Unipolar D/A Converters, DAC708 DAC708 and DAC709 DAC709. Zero and gain may be trimmed by installing external zero and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram and adjust as described below. TCR of the potentiometers should be 100ppm/°C or less. The 3.9M and 270k resistors (±20% carbon or better) should be located close to the D/A converter to prevent noise pickup. If it is not convenient to use these high-value resistors, an equivalent "T" network, as shown in Figure 3, may be substituted in place of the 3.9M resistor. A 0.001µF to 0.01µF ceramic capacitor should be connected from GAIN ADJUST to ANALOG COMMON to prevent noise pickup. Refer to Figures 4 and 5 for the relationship of zero and gain adjustments to unipolar D/A converters. 3.9M 180k + Full Scale 1LSB Analog Output Input = 8000H 8000H Gain Adjust Rotates the Line Full Scale Range Range of Gain Adjust Offset Adjust Translates the Line Range and Offset Adjust Input = 7FFFH Input = 0000H 0000H 180k ­ Full Scale 10k Digital Input FIGURE 5. Relationship of Zero and Gain Adjustments for Bipolar D/A Converters, DAC707 DAC707 and DAC708/ DAC708/ 709 FIGURE 3. Equivalent Resistances. ® 7 DAC707/708/709 DAC707/708/709 VOLTAGE OUTPUT MODELS Digital Input Code One LSB FFFFH 0000H 0000H Analog Output Unipolar, 0 to +10V(1) 16-Bit 15-Bit 14-Bit Units 153 +9.99985 0 305 +9.99969 0 610 +9.99939 0 µV V V Analog Output Digital Input Code One LSB 7FFFH 8000H 8000H Bipolar, ±10V Bipolar, ±5V 16-Bit 15-Bit 14-Bit 16-Bit 15-Bit 14-Bit Units 305 +9.99960 ­10.0000 610 +9.99939 ­10.0000 1224 +9.99878 ­10.0000 153 +4.99980 ­5.0000 305 +4.99970 ­5.0000 610 +4.99939 ­5.0000 µV V V CURRENT OUTPUT MODELS Analog Output Digital Input Code 16-Bit 15-Bit 14-Bit Units 0.031 ­1.99997 0 One LSB FFFFH 0000H 0000H Analog Output Digital Input Code Unipolar, 0 to ­2mA (1) 0.061 ­1.99994 0 0.122 ­1.99988 0 µA mA mA Bipolar, ±1mA 16-Bit One LSB 7FFFH 8000H 8000H 15-Bit 14-Bit Units 0.031 ­0.99997 +1.00000 0.061 ­0.99994 +1.00000 0.122 ­0.99988 +1.00000 µA mA mA NOTE: (1) MSB assumed to be inverted externally. TABLE II. Digital Input and Analog Output Voltage/Current Relationships. INTERFACE LOGIC AND TIMING DAC708/709 DAC708/709 LOGIC TIMING - Parallel or Serial Data Input Over Temperature ns, min ns, max TDW Data valid to end of WR 80 TCW CS valid to end of WR 80 TAW A0, A1, A2 valid to end of WR 80 TWP Write pulse width 80 TDH Data hold after end of WR 0 The signals CHIP SELECT (CS), WRITE (WR), register enables (A0, A1, and A2) and CLEAR (CLR), provide the control functions for the microprocessor interface. They are all active in the "low" or logic "0" state. CS must be low to access any of the registers. A0 and A1 steer the input 8-bit data byte to the low- or high-byte input latch respectively. A2 gates the contents of the two input latches through to the D/A latch in parallel. The contents are then applied to the input of the D/A converter. When WR goes low, data is strobed into the latch or latches which have been enabled. TIMING DIAGRAM tCW CS tAW A0, A1, A2 The serial input mode is activated when both A0 and A1 are logic "0" simultaneously. The D0 (D8)/SI input data line accepts the serial data MSB first. Each bit is clocked in by a WR pulse. Data is strobed through to the D/A latch by A2 going to logic "0" the same as in the parallel input mode. tDW D0-D15 D0-D15, SI tDH WR Each of the latches can be made "transparent" by maintaining its enable signal at logic "0". However, as stated above, when both A0 and A1 are logic "0" at the same time, the serial mode is selected. tWP FIGURE 6. Logic Timing Diagram. D/A latch is enabled by A1. Also, there is no serial-input mode and no CHIP SELECT (CS) line. The CLR line resets both input latches to all zeros and sets the D/A latch to 0000H 0000H. This is the binary code that gives a null, or zero, at the output of the D/A in the bipolar mode. In the unipolar mode, activating CLR will cause the output to go to one-half of full scale. INSTALLATION CONSIDERATIONS The maximum clock rate of the latches is 10MHz. The minimum time between write (WR) pulses for successive enables is 20ns. In the serial input mode (DAC708 DAC708 and DAC709 DAC709), the maximum rate at which data can be clocked into the input shift register is 10MHz. Due to the extremely-high accuracy of the D/A converter, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a +10V full-scale range, 1LSB is 153µV. With a load current of 5mA, series wiring and connector resistance of only 30m will cause the output to be in error by 1LSB. To understand what this means in terms of a system layout, the resistance of typical 1 ounce copper-clad printed circuit board material is approximately 1/2m per square. In the example above, a 10 milliinch-wide conductor 60 milliinches long would cause a 1LSB error. The timing of the control signals is given in Figure 6. DAC707 DAC707 The DAC707 DAC707 interface timing is the same as that described above except instead of two 8-bit separately-enabled input latches, it has a single 16-bit input latch enabled by A0. The ® DAC707/708/709 DAC707/708/709 8 In Figures 7 and 8, lead and contact resistances are represented by R1 through R5. As long as the load resistance RL is constant, R2 simply introduces a gain error and can be removed with gain calibration. R3 is part of RL if the output voltage is sensed at ANALOG COMMON. DAC707/709 DAC707/709 RF 10k MicroProcessor Interface 4k Figures 8 and 9 show two methods of connecting the current output model with an external precision output op amp. By sensing the output voltage at the load resistor (connecting RF to the output of the amplifier at RL) the effect of R1 and R2 is greatly reduced. R1 will cause a gain error but is independent of the value of RL and can be eliminated by initial calibration adjustments. The effect of R2 is negligible because it is inside the feedback loop of the output op amp and is therefore greatly reduced by the loop gain. R2 2k 0 to 2mA RL 2mA +1% Analog Common Digital Common Sense Output R3 Alternate Ground Sense Connection In many applications it is impractical to sense the output voltage at ANALOG COMMON. Sensing the output voltage at the system ground point is permissible because these converters have separate analog and digital common lines and the analog return current is a near-constant 2mA and varies by only 10µA to 20µA over the entire input code range. R4 can be as large as 3 without adversely affecting the linearity of the D/A converter. The voltage drop across R4 is constant and appears as a zero error that can be nulled with the zero calibration adjustment. R4 1µF 1µF + + System Ground +VCC Analog Common ­VCC ±VCC Supply Digital Common 1µF VDD Supply + VDD Another approach senses the output at the load as shown in Figure 9. In this circuit the output voltage is sensed at the load common and not at the D/A converter common as in the previous circuits. The value of R6 and R7 must be adjusted for maximum common-mode rejection across RL. The effect of R4 is negligible as explained previously. FIGURE 7. DAC707/709 DAC707/709 Bipolar Output Circuit (Voltage Out). DAC708 DAC708 R1 The D/A converter and the wiring to its connectors should be located to provide optimum isolation from sources of RFI and EMI. The key to elimination of RF radiation or pickup is small loop area. Signal leads and their return conductors should be kept close together such that they present a small flux-capture cross section for any external field. RF1 RF 10k MicroProcessor Interface IOUT 2.45k R2 RB RL DAC708 DAC708 Analog Common Digital Common Sense Output R1 RF R3 R2 Alternate Ground Sense Connection RDAC R4 1µF 1µF + + System Ground +VCC Analog Common ­VCC R7 To System Ground R3 FIGURE 9. Alternate Connection for Ground Sensing at the Load (Current Output Models). VDD Supply + Sense Output R5 ±VCC Supply Digital Common 1µF RL R6 VDD FIGURE 8. DAC708 DAC708 Bipolar Output Circuit (with External Op Amp). ® 9 DAC707/708/709 DAC707/708/709 BURN-IN SCREENING Burn-in screening is an option available for the DAC707 DAC707. Burn-in duration is 160 hours at the temperature shown below (or equivalent combination of time and temperature). Product Temp. Range signal lines need to be isolated. The data is applied to pin 11 in a serial bit stream, MSB first. The WR input is used as a data strobe, clocking in each data bit. A RESET signal is provided for system startup and reset. These three signals are each optically isolated. Once the 16 bits of serial data have been strobed into the input register pair, the data is strobed through to the D/A register by the "carry" signal out of a 4-bit binary synchronous counter that has counted the 16 WR pulses used to clock in the data. The circuit diagram is given in Figure 10. Burn-In Screening DAC707JP-BI DAC707JP-BI 0°C to 70°C 100°C DAC707KP-BI DAC707KP-BI 0°C to 70°C 100°C DAC707KH-BI DAC707KH-BI ­25°C to +85°C 125°C DAC707BH-BI DAC707BH-BI ­25°C to +85°C 125°C DAC707SH-BI DAC707SH-BI ­55°C to +125°C 125°C All units are tested after burn-in to ensure that grade specifications are met. CONNECTING MULTIPLE DAC707s TO A 16-BIT 16-BIT MICROPROCESSOR BUS Figure 11 illustrates the method of connecting multiple DAC707s to a 16-bit microprocessor bus. The circuit shown has two DAC707s and uses only one address line to select either the input register or the D/A register. An external address decoder selects the desired converter. APPLICATIONS LOADING THE DAC709 DAC709 SERIALLY ACROSS AN ISOLATION BARRIER A very useful application of the DAC709 DAC709 is in achieving low-cost isolation that preserves high accuracy. Using the serial input feature of the input register pair, only three ® DAC707/708/709 DAC707/708/709 10 74LS161A 74LS161A VDD Synchronous Binary Counter Carry Out QA ENT QB ENP QC Load QD A B In C CLR CK D 2.2k 0.001µF No Connection +5V 1/4 74LS00 74LS00 VDD VDD A 2 A1 A0 CS 2.2k 330 Analog Output WR TIL117 TIL117 DATA STROBE 1/6 7407 VDD CLR DAC708 DAC708 or DAC709 DAC709 VDD 330 2.2k Serial Input (16-Bit Data Stream) 1/6 7407 VDD ACOM DCOM ­VCC +VCC DO 1/4 74LS00 74LS00 + + 1/4 74LS00 74LS00 VDD VDD 330 + 10k 2.2k RESET + 2.2µF VDD 1/6 7407 + Isolated Power Supply Power Supply Voltage ­ Isolation Barrier . DATA STROBE Serial Input 1 2 3 4 14 . 15 16 A2 Analog Output FIGURE 10. Serial Loading of Electrically Isolated DAC708/709 DAC708/709. WR D16 16-Bit Data Bus D0 A0 A1 µP A15 A1 16-Bit Address Bus Base Address Decoder WR VOUT 1 DAC707 DAC707 CS1 A0 CS2 A1 A0 WR VOUT 2 DAC707 DAC707 FIGURE 11. Connecting Multiple DAC707s to a 16-Bit Microprocessor. ® 11 DAC707/708/709 DAC707/708/709 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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