DAC5681Z SLLS865C 16-BIT DAC5682Z DAC5681 DAC5681ZIRGCT 64QFN DAC5681ZIRGCR - Datasheet Archive

 

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DAC5681Z DAC5681Z www.ti.com . SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 16-BIT 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) FEATURES 1 · · · · · · · · · 16-Bit Digital-to-Analog Converter (DAC) 1.0 GSPS Update Rate 16-Bit Wideband Input LVDS Data Bus ­ 8 Sample Input FIFO High Performance ­ 73 dBc ACLR WCDMA TM1 at 180 MHz 2x-32x Clock Multiplying PLL/VCO 2x or 4x Interpolation Filters ­ Stopband Transition 0.4­0.6 Fdata ­ Filters Configurable in Either Low-Pass or High-Pass Mode ­ Allows Selection of Higher Order Image On Chip 1.2 V Reference Differential Scalable Output: 2 to 20 mA Package: 64-Pin 9 × 9 mm QFN APPLICATIONS · · · · · Cellular Base Stations Broadband Wireless Access (BWA) WiMAX 802.16 Fixed Wireless Backhaul Cable Modem Termination System (CMTS) DESCRIPTION The DAC5681Z DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x interpolation filters, on-board clock multiplier and internal voltage reference. The DAC5681Z DAC5681Z offers superior linearity, noise, crosstalk and PLL phase noise performance. The DAC5681Z DAC5681Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either Low-Pass or High-Pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock. The DAC5681Z DAC5681Z is characterized for operation over the industrial temperature range of ­40°C to 85°C and is available in a 64-pin QFN package. Other members of the family include the dual-channel, interpolating DAC5682Z DAC5682Z and the single-channel, non-interpolating DAC5681 DAC5681. ORDERING INFORMATION TA ­40°C to 85°C (1) (2) (3) ORDER CODE PACKAGE DRAWING/TYPE (1) (2) (3) TRANSPORT MEDIA DAC5681ZIRGCT DAC5681ZIRGCT RGC / 64QFN 64QFN Quad Flatpack No-Lead Tape and Reel 250 Tape and Reel 2000 DAC5681ZIRGCR DAC5681ZIRGCR QUANTITY Thermal Pad Size: 7,4 mm × 7,4 mm MSL Peak Temperature: Level-3-260C-168 HR For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007­2009, Texas Instruments Incorporated DAC5681Z DAC5681Z SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 . www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. (3.3V) AVDD (1.8V) VFUSE (1.8V) DVDD LPF (1.8V) CLKVDD FUNCTIONAL BLOCK DIAGRAM PLL Bypass CLKIN Clock Multiplying PLL 2x-32x CLKINC DCLKP DCLKN 1.2V Reference FDAC/2 FDAC/4 EXTIO EXTLO BIASJ PLL Control Delay Lock Loop (DLL) FDAC Clock Distribution PLL Enable Sync Disable DLL Control Mode Control B A FIR1 13 16bit DAC IOUTA1 IOUTA2 4 2 DAC Gain 100 47t 76dB HBF FIR0 TXEnable='1' SYNCN x2 47t 76dB HBF SYNC='0->1' (transition) SYNCP DAC Delay (0-3) x2 Offset 16 (x1 Bypass) Fir0 Enable 16 8 Sample FIFO D0N DDR De-interleave 100 D0P (x2 Bypass) Delay Value 16 D15N Fir1 Enable 100 D15P Sync & Control SW_Sync 2 Submit Documentation Feedback GND (3.3V) IOVDD RESETB SCLK SDENB SDO SDIO FIFO Sync Disable Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z DAC5681Z DAC5681Z www.ti.com . SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 DVDD RESETB 50 49 AVDD 54 51 AVDD 55 IOUTA2 EXTIO 56 IOUTA1 AVDD BIASJ 57 53 AVDD EXTLO 52 AVDD 60 59 58 AVDD AVDD 62 DVDD 63 61 LPF 64 DAC5681Z DAC5681Z RGC PACKAGE (TOP VIEW) CLKVDD 1 48 SDENB CLKIN 2 47 SCLK CLKINC 3 46 SDIO GND 4 45 SDO SYNCP 5 44 VFUSE SYNCN D15P 6 43 D0N 7 42 D0P D15N 8 41 D1N DAC5681Z DAC5681Z IOVDD 9 40 D1P DVDD 10 39 DVDD 28 29 30 31 32 D7N D6P D6N D5P D5N 27 D7P 26 DCLKN D4P 25 33 DCLKP 16 23 D12N 24 D4N D8P 34 D8N 15 21 D12P 22 D3P D9P D13N D9N D3N 35 19 36 14 20 13 D10P D13P D10N D2P 18 D2N 37 D11N 38 12 17 11 D11P D14P D14N TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AVDD 51, 54, 55, 59­62 I BIASJ 57 O Full-scale output current bias. For 20mA full-scale output current, connect a 960 resistor to GND. CLKIN 2 I Positive external clock input with a self-bias of approximately CLKVDD/2. With the clock multiplier PLL enabled, CLKIN provides lower frequency reference clock. If the PLL is disabled, CLKIN directly provides clock for DAC up to 1GHz. CLKINC 3 I Complementary external clock input. (See the CLKIN description) CLKVDD 1 I Internal clock buffer supply voltage. (1.8 V) D[15.0]P 7, 11, 13, 15, 17, 19, 21, 23, 27, 29, 31, 33, 35, 37, 40, 42 I LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100 termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format relative to DCLKP/N clock is Double Data Rate (DDR) with two data samples input per DCLKP/N clock. In dual-channel mode, data for the A-channel is input while DCLKP is high. D[15.0]N 8, 12, 14, 16, 18, 20, 22, 24, 28, 30, 32, 34, 36, 38, 41, 43 Analog supply voltage. (3.3V) D15P is most significant data bit (MSB) ­ pin 7 D0P is least significant data bit (LSB) ­ pin 42 LVDS negative input data bits 0 through 15. (See D[15:0]P description above) I D15N is most significant data bit (MSB) ­ pin 8 D0N is least significant data bit (LSB) ­ pin 43 Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z 3 DAC5681Z DAC5681Z SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 . www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION 25 I LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit. See the "DLL Operation" section. For proper external termination, connect a 100 resistor across LVDS clock source lines followed by series 0.01 µF capacitors connected to each of DCLKP and DCLKN pins (see Figure 26). For best performance, the resistor and capacitors should be placed as close as possible to these pins. DCLKN 26 I LVDS negative input clock. (See the DCLKP description) DVDD 10, 39, 50, 63 I EXTIO 56 Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). I/O Used as 1.2V internal reference output when EXTLO = GND, requires a 0.1 µF decoupling capacitor to AGND when used as reference output. EXTLO 58 O Connect to GND for internal reference, or AVDD for external reference. 4, Thermal Pad I Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and IOVDD supplies. IOUTA1 52 O DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. IOUTA2 53 O DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described above. An input data value of 0x0000 results in a 0mA sink and the most positive voltage on the IOUTA2 pin. IOVDD 9 I Digital I/O supply voltage (3.3V) for pins RESETB, SCLK, SDENB, SDIO, SDO. LPF 64 I PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin may be left open. Set both PLL_bypass and PLL_sleep control bits for reduced power dissipation. RESETB 49 I Resets the chip when low. Internal pull-up. SCLK 47 I Serial interface clock. Internal pull-down. SDENB 48 I Active low serial data enable, always an input to the DAC5681Z DAC5681Z. Internal pull-up. SDIO 46 I/O Bi-directional serial interface data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO pin is an input only. Internal pull-down. SDO 45 O Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is in high-impedance state in 3-pin interface mode (default), but can optionally be used as a status output pin via CONFIG14 CONFIG14 SDO_func_sel(2:0). Internal pull-down. SYNCP 5 I LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100 termination resistor. By default, the SYNCP/N input must be logic `1' to enable a DAC analog output. See the LVDS SYNCP/N Operation paragraph for a detailed description. SYNCN 6 I LVDS SYNC negative input data. VFUSE 44 I Digital supply voltage. (1.8V) Connect to DVDD pins for normal operation. This supply pin is also used for factory fuse programming. NAME DCLKP GND 4 NO. Digital supply voltage. (1.8 V) Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z DAC5681Z DAC5681Z www.ti.com . SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE ­0.5 to 2.3 V VFUSE (2) Supply voltage range UNIT DVDD (2) ­0.5 to 2.3 V CLKVDD (2) ­0.5 to 2.3 V AVDD (2) ­0.5 to 4 V IOVDD (2) ­0.5 to 4 V AVDD to DVDD ­2 to 2.6 V CLKVDD to DVDD ­0.5 to 0.5 V IOVDD to AVDD ­0.5 to 0.5 V D[15.0]P ,D[15.0]N, SYNCP, SYNCN (2) ­0.5 to DVDD + 0.5 V DCLKP, DCLKN (2) ­0.3 to 2.1 V CLKIN, CLKINC (2) Terminal voltage range ­0.5 to CLKVDD + 0.5 V ­0.5 to IOVDD + 0.5 V ­0.5 to AVDD + 0.5 V SDO, SDIO, SCLK, SDENB, RESETB IOUTA1, IOUTA2 (2) (2) LPF, EXTIO, EXTLO, BIASJ (2) Peak total input current (all inputs) V 20 Peak input current (any input) ­0.5 to AVDD + 0.5 mA ­30 mA Operating free-air temperature range, TA: DAC5681Z DAC5681Z ­40 To 85 °C Storage temperature range ­65 To 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured with respect to GND. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) THERMAL CONDUCTIVITY TJ Maximum junction temperature 64ld QFN UNIT 125 (1) (2) °C Theta junction-to-ambient (still air) 22 Theta junction-to-ambient (200 lfm) 15 JT Psi junction-to-top of package 0.2 °C/W JB Theta junction-to-board 3.5 °C/W JA (1) (2) °C/W Air flow or heat sinking reduces JA and may be required for sustained operation at 85° under maximum operating conditions. It is strongly recommended to solder the device thermal pad to the board ground plane. Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z 5 DAC5681Z DAC5681Z SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 . www.ti.com ELECTRICAL CHARACTERISTICS - DC SPECIFICATION over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS RESOLUTION MIN TYP MAX 16 UNIT Bits DC ACCURACY (1) INL Integral nonlinearity DNL 1 LSB = IOUTFS/216 IOUTFS/216 ±4 Differential nonlinearity LSB ±2 ANALOG OUTPUT Coarse gain linearity ±0.04 LSB Offset error Mid code offset 0.01 %FSR Gain error With external reference 1 %FSR Gain error With internal reference 0.7 %FSR Minimum full scale output current (2) 2 Maximum full scale output current (2) 20 Output Compliance range (3) mA IOUTFS = 20 mA AVDD ­0.5V Output resistance AVDD + 0.5V V 300 5 Output capacitance k pF REFERENCE OUTPUT Vref Reference voltage 1.14 Reference output current (4) 1.2 1.26 100 V nA REFERENCE INPUT VEXTIO Input voltage range 0.1 Input resistance Small signal bandwidth 1.25 1 CONFIG6: BiasLPF_A = 0 95 CONFIG6: BiasLPF_A = 1 472 Input capacitance V M kHz 100 pF ±1 ppm of FSR/°C TEMPERATURE COEFFICIENTS Offset drift Gain drift With external reference ±15 With internal reference ±30 ppm of FSR/°C ±8 ppm/°C Reference voltage drift POWER SUPPLY Analog supply voltage, AVDD 3.0 3.3 3.6 V Digital supply voltage, DVDD 1.7 1.8 1.9 V Clock supply voltage, CLKVDD 1.7 1.8 1.9 V I/O supply voltage, IOVDD 3.0 3.3 3.6 V I(AVDD) Analog supply current 68 mA I(DVDD) Digital supply current 271 mA I(CLKVDD) Clock supply current 41 mA I(IOVDD) IO supply current 13 mA (1) (2) (3) (4) 6 Mode 4 (below) Measured differential across IOUTA1 and IOUTA2 with 25 each to AVDD. Nominal full-scale current, IoutFS, equals 16 × IBIAS current. The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5681Z DAC5681Z device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity. Use an external buffer amplifier with high impedance input to drive any external load. Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z DAC5681Z DAC5681Z www.ti.com . SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS - DC SPECIFICATION (continued) over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(AVDD) Sleep mode, AVDD supply current 1 mA I(DVDD) Sleep mode, DVDD supply current 4 mA I(CLKVDD) Sleep mode, CLKVDD supply current 2 mA I(IOVDD) Sleep mode, IOVDD supply current 2 mA 71 mA AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.8V Mode 6 (below) Mode 1: 1X2, PLL = OFF, CLKIN = 983.04 MHz FDAC = 983.04MHz, IF = 184.32 MHz 4 carrier WCDMA 267 AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.8V DVDD + CLKVDD current, 1.8V P Power Dissipation AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.8V Power Dissipation AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.8V Power Dissipation AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.8V Power supply rejection ratio T mW 71 Mode 3: 1X4, HP/HP, PLL = OFF, CLKIN = 983.04 MHz, FDAC = 983.04MHz, IF = 215.04 MHz 4 carrier WCDMA mA 790 mA 278 mW 81 Mode 4: 1X4, HP/HP, PLL = ON (8X), CLKIN = 122.88 MHz FDAC = 983.04MHz, IF = 215.04 MHz DACA on, 4 carrier WCDMA mA 735 mA 312 830 Mode 5: PLL = OFF, CLKIN = 983.04 MHz, FDAC = 983.04MHz, Digital Logic Disabled, DAC on SLEEP, Static Data Pattern mA 910 mW 3 mA 117 mW 3 Mode 6: PLL = OFF, CLKIN = OFF FDAC = OFF, Digital Logic Disabled DAC on SLEEP, Static Data Pattern mA 220 mA 6 Power Dissipation PSRR mA 292 Power Dissipation AVDD + IOVDD current, 3.3V mW 81 Mode 2: 1X2, PLL = ON (8X), CLKIN = 122.88 MHz FDAC = 983.04MHz, IF = 184.32 MHz 4 carrier WCDMA mA 715 Power Dissipation 20 mA 0.2 %FSR/V ­40 Operating range mW ­0.2 DC tested 30 85 °C ANALOG OUTPUT fCLK Maximum output update rate 1000 ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF tpd Output propagation delay DAC output is updated on falling edge of DAC clock. Does not include Digital Latency (see below). tr(IOUT) Output rise time 10% to 90% tf(IOUT) Output fall time 90% to 10% MSPS 10.4 ns 2.5 ns 220 ps 220 ps No interpolation, PLL Off x2 interpolation, PLL Off 158 x4 interpolation, PLL Off Digital Latency 76 289 DAC clock cycles DAC Wake-up Time Power-up Time IOUT current settling to 1% of IOUTFS. Measured from SDENB; Register 0x06, toggle Bit 4 from 1 to 0. 80 µs DAC Sleep Time IOUT current settling to less than 1% of IOUTFS. Measured from SDENB; Register 0x06, toggle Bit 4 from 0 to 1. 80 µs Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z 7 DAC5681Z DAC5681Z SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 . www.ti.com ELECTRICAL CHARACTERISTICS - AC SPECIFICATION (1) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V, IOUTFS = 20 mA, 4:1 transformer output termination, 50 doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE 1X1, PLL off, CLKIN = 500 MHz, IF = 5.1 MHz, First Nyquist Zone < fDATA/2 60 60 73 88 1X2, PLL off, CLKIN = 1000 MHZ, IF = 70.1 and 71.1 MHz 75 1X2, PLL off, CLKIN = 1000 MHZ, IF = 150.1 and 151.1 MHz Four-tone intermodulation (each tone at ­12 dBFS) 1X4, PLL off, CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 180 MHz 1X2, PLL off, CLKIN = 1000 MHZ, IF = 20.1 and 21.1 MHz IMD 66 1X2, PLL off, CLKIN = 1000 MHZ, Four tone, each -12 dBFS, IF = 24.7, 24.9, 25.1 and 25.3 MHz IMD3 70 1X2 , PLL off, CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 300.2 MHz Third-order two-tone intermodulation (each tone at ­6 dBFS) 75 1X2, PLL off, CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 70.1 MHz Signal-to-noise ratio 77 1X2, PLL off, CLKIN = 1000 MHZ, Single tone, 0 dBFS, IF = 20.1 MHz SNR 80 1X2, PLL off, CLKIN = 500 MHZ, Single tone, 0 dBFS, IF = 20.1 MHz Spurious free dynamic range 1X2, PLL off, CLKIN = 1000 MHz, IF = 5.1 MHz, First Nyquist Zone < fDATA/2 1X2, PLL off, CLKIN = 1000 MHz, IF = 20.1 MHz, First Nyquist Zone < fDATA/2 SFDR 81 67 1X2, PLL off, CLKIN = 1000 MHz, IF = 298.4, 299.2, 300.8 and 301.6 MHz 64 Single carrier, baseband, 1X2, PLL off, CLKIN = 983.04 MHz 80 Adjacent channel leakage ratio Noise floor (3) (1) (2) (3) 8 dBc dBc dBc 83 Single carrier, IF = 180 MHz, 1X2, PLL off, CLKIN = 983.04 MHz 73 Four carrier, IF = 180 MHz, 1X2, PLL off, CLKIN = 983.04 MHz 68 Four carrier, IF = 275 MHz, 1X2, PLL off, CLKIN = 983.04 MHz ACLR (2) dBc 66 50-MHz offset, 1-MHz BW, Single Carrier, baseband, 1X2, PLL off, CLKIN = 983.04 93 50-MHz offset, 1-MHz BW, Four Carrier, baseband, 1X2, PLL off, CLKIN = 983.04 85 dBc dBc Measured single-ended into 50 load. W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms Carrier power measured in 3.84 MHz BW. Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z DAC5681Z DAC5681Z www.ti.com . SLLS865C SLLS865C ­ AUGUST 2007 ­ REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS LVDS INTERFACE: D[15:0]P/N, SYNCP/N, DCLKP/N MIN TYP MAX UNIT (1) VA,B+ Logic high differential input voltage threshold 175 mV VA,B­ Logic low differential input voltage threshold ­175 mV VCOM1 Input Common Mode VCOM2 Input Common Mode ZT Internal termination CL DCLK to Data 1.0 DCLKP/N only SYNCP/N, D[15:0]P/N only 85 DCLKP/N: 0 to 125MHz (see Figure 32) DLL Disabled, CONFIG5 DLL_bypass = 1, CONFIG10 CONFIG10 = '00000000' DCLKP/N = 200 MHz DCLKP/N = 250 MHz DCLK to Data Skew (2) DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format DCLKP/N = 300 MHz DCLKP/N = 350 MHz DCLKP/N = 400 MHz DCLKP/N = 450 MHz DCLKP/N = 500 MHz fDATA Input data rate supported 110 Setup_min Positive ­1800 Positive 800 Negative ­1300 Positive 600 Negative ­1000 Positive 450 Negative ­800 Positive 400 Negative ­700 Positive ps 300 Negative ­600 Positive 300 Negative ­500 Positive 350 Negative ­300 DLL Disabled, CONFIG5 DLL_bypass = 1, DDR format, DCLKP frequency: