DAC1401D125 AD9767 DAC2904 DAC5672 LQFP48 DAC1201D125 DAC1001D125 - Datasheet Archive
125 Msps DAC1401D125 Lowest power consumption for your cost-effective I/Q transmit application Operating with high update rates
NXP high-speed, highperformance dual 14-bit, 125 Msps DAC1401D125 DAC1401D125 Lowest power consumption for your cost-effective I/Q transmit application Operating with high update rates of up to 125 Msps, the DAC1401D125 DAC1401D125 from NXP Semiconductors offers exceptional dynamic performance whilst maintaining low power consumption. Key benefits Optimized for I/Q transmit applications -40 % power consumption versus competitor 1.8V / 3.3V / 5.0V input data path compliance Easy to implement (wide operating window in clock period) Pin-to-pin compatible AD9767 AD9767, DAC2904 DAC2904, DAC5672 DAC5672 Key features 14-bit resolution, up to 125 Msps update rate Dual port or interleaved data Excellent SFDR and IMD: 80 dBc Fully independent gain control Single +3.3V supply operation Power dissipation: < 185 mW @ 3.3 V Power down mode: 16.5 mW @ 3.3v 48 lead LQFP package Key applications Communications (basestation, WLAN, WLL) Quadrature modulator Direct Digital Synthesis (DDS) VDSL / AWG Medical / test instrumentation The DAC1401D125 DAC1401D125 is a high-speed, high-performance dual 14 bit digital-to-analog data converter designed for I/Q transmit applications and for applications where board space and power consumption are at a premium. The DAC1401D125 DAC1401D125 can operate with its own individual digital inputs, as well as interleaved DACs where data is alternately written from a single digital input path to either of the two DACs. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. The DAC1401D125 DAC1401D125 is available in a LQFP48 LQFP48 package, and is specified over the extended industrial temperature range of -40 deg C to +85 deg C. Pin-to-pin compatible with family members DAC1201D125 DAC1201D125 (12 bit) and DAC1001D125 DAC1001D125 (10 bit). Typical application RL RL AGND AGND AGND AGND 1.5 k 100 AGND 1.5 k 100 nF 100 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 PWD AGND IOUTBP IOUTBN BVIRES GAINCTRL REFIO AVIRES AGND IOUTAN IOUTAP MODE VDDA 3.3 V 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 DAC1401D125 DAC1401D125 7 30 8 29 9 28 10 27 11 26 12 25 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 100 nF DGND 3.3 V DB12 DB13 VDDD DGND IQSEL IQRESET IQCLK IQWRT VDDD DA0 DGND DA1 13 14 15 16 17 18 19 20 21 22 23 24 100 nF DGND 3.3 V 001aaj063 www.nxp.com © 2008 NXP B.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. Date of release: December 2008 The information presented in this document does not form part of any quotation or contract, is believed to be accurate and Document order number: 9397 750 16649 reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Printed in the Netherlands Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.