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D12-D0

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: the BW bit is set (BW = 1), D12­D0 are active. The clock input pin used to drive the ADC12041. The , and the CS will enable the input buffers of the data pins D12­D0. The signal at this pin is used by the ADC12041 to latch in data on D12­D0. The sense of the WMODE pin at power-up will determine which , Logic Low Output Voltage TRI-STATE Output Leakage Current D12­D0 Input Capacitance Conditions VA+ = VD , D12­D0 are all active. The BW bit is cleared at power-up. b4: The SYNC bit. When the SYNC bit is a '1' National Semiconductor
Original
SNAS106 TMS320C25 MC68HC11/16 ADSP21 LM4040 LM4041
Abstract: the BW bit is set (BW = 1), D12­D0 are active. The clock input pin used to drive the ADC12041. The , and the CS will enable the input buffers of the data pins D12­D0. The signal at this pin is used by the ADC12041 to latch in data on D12­D0. The sense of the WMODE pin at power-up will determine which , Logic Low Output Voltage TRI-STATE Output Leakage Current D12­D0 Input Capacitance Conditions VA+ = VD , D12­D0 are all active. The BW bit is cleared at power-up. b4: The SYNC bit. When the SYNC bit is a '1' National Semiconductor
Original
LM9140 ADC12041CIMSASSOP-EIAJ ADC12041CIV
Abstract: ± 2.0 |xA (max) C|N D12-D0 Input Capacitance 10 PF Converter AC Characteristics The , Conversion *CSWR "*CSRD ^rdcs ! Jâ'"L 1_r DATA D12-D0 LWRSET Falling , ^OROr *â { *CSWR *RDCS Ã"" Jâ'"L ' *RD ' T_r DATA D12-D0 'wrset Falling WRHOLD Falling 'RO , /H/123S7-46 FIGURE 7c. Sync-Out Write (WMODE = 0, BW = 1), Read and Convert Cycles _n DATA D12-D0 , _i 1_r W DATA 1_r ' 'RDHOLO DATA D12-D0 -^Valid Daïâ^- *RD DATA " *RDH0LD -^Valid -
OCR Scan
ADC12048 ADC12046 ci 4946 7466 ci me 4946 TTL 7466 AN64 B1-043-299-2408
Abstract: ® . When the BW bit is set (BW = 1), D12­D0 are active. 28 CLK The clock input pin used to , D12­D0. The signal at this pin is used by the ADC12041 to latch in data on D12­D0. The sense of the , = 5V CIN D12­D0 Input Capacitance 10 pF Converter AC Characteristics The following , configured to interface with a 16-bit data bus and data pins D12­D0 are all active. The BW bit is cleared at , -bit data input/output bus (D12­D0), digital control signals and two internal registers: a write only 8 National Semiconductor
Original
DS012441-1
Abstract: ® . When the BW bit is set (BW = 1), D12­D0 are active. 28 CLK The clock input pin used to , D12­D0. The signal at this pin is used by the ADC12041 to latch in data on D12­D0. The sense of the , VOUT = 0V VOUT =5V CIN D12­D0 Input Capacitance 10 pF Converter AC Characteristics The , configured to interface with a 16-bit data bus and data pins D12­D0 are all active. The BW bit is cleared at , /output bus (D12­D0), digital control signals and two internal registers: a write only 8 National Semiconductor
Original
4946 zener 3.3 b2 DS012441-
Abstract: = ov Vout = 5V ±2.0 jliA (max) C|N D12-D0 Input Capacitance 10 pF Converter AC , Acquisition Time Hold Analog Input and Begin Conversion Acq SyncOut ' *R0CS 1_r Falling DATA D12-D0 , DATA D12-D0 WRSET Falling ^RD DATA Valid DataX WMODE i y tl/h/12387â'"14 FIGURE 7b. Sync-In , Copyrighted By Its Respective Manufacturer Timing Diagrams (Continued) DATA D12-D0 - Start Acquisition , Acquisition *CSWR DATA D12-D0 Change Multiplexer Channel â'¢RD RDY J L " ^CSRD " «Re- 's Des !"" 1 -
OCR Scan
SMR 40000 smr 40000 c 2800N TL 4946 L20MA ADC12048CIV ADI21 D-B225 273S-9960
Abstract: =5V ±2.0 ¡xA (max) C|N D12-D0 Input Capacitance 10 pF Converter AC Characteristics The , SyncOut DATA D12-D0 'cSWR Ã- wfhold Falling Jâ'"L -â'¢CSRO ^RDCS Ã" i_r *rd data , Convert Cycles tl/h/12441â'"13 _n DATA D12-D0 Start Acquisition WRHOLD Falling â'¢rdrdï Jâ'"L , Respective Manufacturer Timing Diagrams (Continued) â  Start Acquisition âºj *cswr DATA D12-D0 *RD , â  Hold Analog Input and Begin Conversion TL/H/12441 -46 _n DATA D12-D0 - Start Acquisition -
OCR Scan
ADI21xx TL/H/12441-1 2T2-5066 S0112M
Abstract: ), followed by the 13 data bits D12.D0 (Figure 4). The 3-bit control code determines: · The register to be , 3 Control Bits 13 Data Bits , . Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION C0 MSB Maxim Integrated Products
Original
MAX535 MAX535BMJA schmitt trigger using ic 555 optocoupler with schmitt trigger input SCLK45 MAX535ACPA MAX535ACUA MAX535AEPA MAX535BEPA MAX535AEUA MAX535BEUA
Abstract: D12.D0 (Figure 4). The 3-bit control code determines: · The register to be updated · The configuration , C0 3 Control Bits 13 Data Bits , MSB LSB FUNCTION C2 X 0 0 13 bits of data Load input register; DAC register Maxim Integrated Products
Original
MAX5351 MAX535BCPA MAX535BCUA MAX535/MAX5351 21-0036D
Abstract: ), D7­D0 are active and D12­D8 are always in TRI-STATE. When the BW bit is set (BW = 1), D12­D0 are , the CS will enable the input buffers of the data pins D12­D0. The signal at this pin is used by the ADC12048 to latch in data on D12­D0. The sense of the WMODE pin at power-up will determine which edge of , mA IOFF TRI-STATE ® Output Leakage Current CIN D12­D0 Input Capacitance VOUT = 0V , . The digital interface consists of a 13-bit data input/output bus (D12­D0), digital control signals National Semiconductor
Original
ADC12048CIVF V44A
Abstract: 10010000 SI 0 0 A5 A0 0 0 0 D12D0 0 0 0 D12D0 0 0 0 D12D0 RDY SO OFRAM S_RESET RQ SCLK SI 1 0 0 1 0 0 0 0 0 0 A5A0 0 0 0 0 0 0 0 0 0 0 0 D12D0 1 0 0 1 0 0 0 0 0 0 A5A0 0 0 0 0 0 Asahi Kasei Microsystems
Original
AK7730A AK7730AVT 74h 132 CLKO22 48KHz PLL SWA marking AK7730A24ADCADC8 AK7730ADSP8192 AK7730ARAMDSP AK7730 PLL256
Abstract: D12.D0 (Figure 4). The 3-bit control code determines: · The register to be updated · The configuration , C0 3 Control Bits 13 Data Bits , MSB LSB FUNCTION C2 X 0 0 13 bits of data Load input register; DAC register Maxim Integrated Products
Original
Abstract: DAC LATCH D DAC D ­ + VOUTD INPUT LATCH E D12­D0 DAC LATCH A DAC LATCH E , selected by A0­A2. A2 Address bit 2. A1 Address bit 1. A0 Address bit 0. D12­D0 Data bits 12­0. (D0 Signal Processing Technologies
Original
SPT5400 SPT5400SCP 13-BIT
Abstract: + VOUTG INPUT LATCH H D12­D0 DAC LATCH A DAC LATCH H DAC H AGNDAB AGNDCD , Address bit 2. A1 Address bit 1. A0 Address bit 0. D12­D0 Data bits 12­0. (D0 = LSB) LDEF Load Fairchild Semiconductor
Original
Abstract: + VOUTG INPUT LATCH H D12­D0 DAC LATCH A DAC LATCH H DAC H AGNDAB AGNDCD , Address bit 2. A1 Address bit 1. A0 Address bit 0. D12­D0 Data bits 12­0. (D0 = LSB) LDEF Load CADEKA Microcircuits
Original
binary weight resistance dac VDR positive
Abstract: D12­D8 are always in TRI-STATE. When the BW bit is set (BW = 1), D12­D0 are active. ADC inputs. The , input buffers of the data pins D12­D0. The signal at this pin is used by the ADC12048 to latch in data on D12­D0. The sense of the WMODE pin at power-up will determine which edge of the WR signal the , 2.0 uA (max) -0.035 -2.0 uA (max) 2.4 V (min) 0.4 V (max) ± 2.0 D12­D0 , a 13-bit data input/output bus (D12­D0), digital control signals and two internal registers: a National Semiconductor
Original
Abstract: ), D7­D0 are active and D12­D8 are always in TRI-STATE. When the BW bit is set (BW = 1), D12­D0 are active , the data pins D12­D0. The signal at this pin is used by the ADC12048 to latch in data on D12­D0. The , Low Output Voltage TRI-STATE Output Leakage Current D12­D0 Input Capacitance Typicals are at TA = 25 , /output bus (D12­D0), digital control signals and two internal registers: a write only 13 , (D7­D0 are active and D12­D8 are in TRI-STATE) if the BW bit is cleared or 13 bits (D12­D0 are active) if Texas Instruments
Original
PGB0044A SNAS105B ISO/TS16949
Abstract: ), D7­D0 are active and D12­D8 are always in TRI-STATE. When the BW bit is set (BW = 1), D12­D0 are active , the data pins D12­D0. The signal at this pin is used by the ADC12048 to latch in data on D12­D0. The , Leakage Current D12­D0 Input Capacitance Conditions VA+ = VD+ = 5.5V VA+ = VD+ = 4.5V VIN = 5V VIN = 0V VA , /output bus (D12­D0), digital control signals and two internal registers: a write only 13 , (D7­D0 are active and D12­D8 are in TRI-STATE) if the BW bit is cleared or 13 bits (D12­D0 are active) if National Semiconductor
Original
SNAS105A
Abstract: and D12­D8 are always in TRI-STATE. When the BW bit is set (BW = 1), D12­D0 are active. The clock , pins D12­D0. The signal at this pin is used by the ADC12048 to latch in data on D12­D0. The sense of , Output Voltage TRI-STATE ® Output Leakage Current D12­D0 Input Capacitance Conditions VA+ = VD+ = 5.5V VA , an 8-bit or 16-bit data bus. The digital interface consists of a 13-bit data input/output bus (D12­D0 , TRI-STATE) if the BW bit is cleared or 13 bits (D12­D0 are active) if the BW bit is set. At power-up the bus National Semiconductor
Original
Abstract: TRI-STATE. When the BW bit is set (BW = 1), D12­D0 are active. ADC inputs. The inverting (negative) and , D12­D0. The signal at this pin is used by the ADC12048 to latch in data on D12­D0. The sense of the , VA+ = VD+ = 4.5V IOUT = 1.6 mA IOFF TRI-STATE ® Output Leakage Current CIN D12­D0 Input , . The digital interface consists of a 13-bit data input/output bus (D12­D0), digital control signals , bits (D12­D0 are active) if the BW bit is set. At power-up the bus width defaults to 8 bits and any National Semiconductor
Original
Abstract: ± 2.0 |xA (max) C|N D12-D0 Input Capacitance 10 PF Converter AC Characteristics The , Conversion *CSWR "*CSRD ^rdcs ! Jâ'"L 1_r DATA D12-D0 LWRSET Falling , ^OROr *â { *CSWR *RDCS Ã"" Jâ'"L ' *RD ' T_r DATA D12-D0 'wrset Falling WRHOLD Falling 'RO , /H/123S7-46 FIGURE 7c. Sync-Out Write (WMODE = 0, BW = 1), Read and Convert Cycles _n DATA D12-D0 , _i 1_r W DATA 1_r ' 'RDHOLO DATA D12-D0 -^Valid Daïâ^- *RD DATA " *RDH0LD -^Valid Texas Instruments
Original
LM95245 SNIS148F LM95235
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