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D12-D0

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Abstract: the BW bit is set (BW = 1), D12­D0 are active. The clock input pin used to drive the ADC12041 ADC12041. The , and the CS will enable the input buffers of the data pins D12­D0. The signal at this pin is used by the ADC12041 ADC12041 to latch in data on D12­D0. The sense of the WMODE pin at power-up will determine which , Logic Low Output Voltage TRI-STATE Output Leakage Current D12­D0 Input Capacitance Conditions VA+ = VD , D12­D0 are all active. The BW bit is cleared at power-up. b4: The SYNC bit. When the SYNC bit is a '1' ... National Semiconductor
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30 pages,
627.09 Kb

ADC12041 SNAS106 TEXT
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Abstract: the BW bit is set (BW = 1), D12­D0 are active. The clock input pin used to drive the ADC12041 ADC12041. The , and the CS will enable the input buffers of the data pins D12­D0. The signal at this pin is used by the ADC12041 ADC12041 to latch in data on D12­D0. The sense of the WMODE pin at power-up will determine which , Logic Low Output Voltage TRI-STATE Output Leakage Current D12­D0 Input Capacitance Conditions VA+ = VD , D12­D0 are all active. The BW bit is cleared at power-up. b4: The SYNC bit. When the SYNC bit is a '1' ... National Semiconductor
Original
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31 pages,
623.43 Kb

ADC12041 TEXT
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Abstract: ± 2.0 |xA (max) C|N D12-D0 Input Capacitance 10 PF Converter AC Characteristics The , Conversion *CSWR "*CSRD ^rdcs ! J—L 1_r DATA D12-D0 LWRSET Falling , ^OROr *■{ *CSWR *RDCS Î"" J—L ' *RD ' T_r DATA D12-D0 'wrset Falling WRHOLD Falling 'RO , /H/123S7-46 /H/123S7-46 FIGURE 7c. Sync-Out Write (WMODE = 0, BW = 1), Read and Convert Cycles _n DATA D12-D0 , _i 1_r W DATA 1_r ' 'RDHOLO DATA D12-D0 -^Valid Daïâ^- *RD DATA " *RDH0LD -^Valid ... OCR Scan
datasheet

29 pages,
1081.99 Kb

LM4040 ci 7805 lg led tv internal parts block diagram ADC1204B LM4041 LM9140 ADC12048 nl 836 TL 7805 TMS320C25 AN64 TTL 7466 me 4946 7466 ci ci 4946 ADC12046 TEXT
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Abstract: ® . When the BW bit is set (BW = 1), D12­D0 are active. 28 CLK The clock input pin used to , D12­D0. The signal at this pin is used by the ADC12041 ADC12041 to latch in data on D12­D0. The sense of the , = 5V CIN D12­D0 Input Capacitance 10 pF Converter AC Characteristics The following , configured to interface with a 16-bit data bus and data pins D12­D0 are all active. The BW bit is cleared at , -bit data input/output bus (D12­D0), digital control signals and two internal registers: a write only 8 ... National Semiconductor
Original
datasheet

28 pages,
596.69 Kb

TMS320C25 LM9140 LM4041 LM4040 ADC12041CIV ADC12041 TEXT
datasheet frame
Abstract: ® . When the BW bit is set (BW = 1), D12­D0 are active. 28 CLK The clock input pin used to , D12­D0. The signal at this pin is used by the ADC12041 ADC12041 to latch in data on D12­D0. The sense of the , VOUT = 0V VOUT =5V CIN D12­D0 Input Capacitance 10 pF Converter AC Characteristics The , configured to interface with a 16-bit data bus and data pins D12­D0 are all active. The BW bit is cleared at , /output bus (D12­D0), digital control signals and two internal registers: a write only 8 ... National Semiconductor
Original
datasheet

28 pages,
589.95 Kb

zener 3.3 b2 TMS320C25 me 4946 LM9140 LM4041 LM4040 ADC12041CIV ADC12041 4946 TEXT
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Abstract: = ov Vout = 5V ±2.0 jliA (max) C|N D12-D0 Input Capacitance 10 pF Converter AC , Acquisition Time Hold Analog Input and Begin Conversion Acq SyncOut ' *R0CS 1_r Falling DATA D12-D0 , DATA D12-D0 WRSET Falling ^RD DATA Valid DataX WMODE i y tl/h/12387—14 FIGURE 7b. Sync-In , Copyrighted By Its Respective Manufacturer Timing Diagrams (Continued) DATA D12-D0 - Start Acquisition , Acquisition *CSWR DATA D12-D0 Change Multiplexer Channel •RD RDY J L " ^CSRD " «Re- 's Des !"" 1 ... OCR Scan
datasheet

29 pages,
1100.38 Kb

V44A 7805 BT ADC12048 ADC12048CIV L20MA LM4040 LM4041 LM9140 me 4946 TL 4946 TMS320C25 2800N smr 40000 c SMR 40000 TEXT
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Abstract: =5V ±2.0 ¡xA (max) C|N D12-D0 Input Capacitance 10 pF Converter AC Characteristics The , SyncOut DATA D12-D0 'cSWR Ê- wfhold Falling J—L -•CSRO ^RDCS Í" i_r *rd data , Convert Cycles tl/h/12441—13 _n DATA D12-D0 Start Acquisition WRHOLD Falling •rdrdï J—L , Respective Manufacturer Timing Diagrams (Continued) ■ Start Acquisition ►j *cswr DATA D12-D0 *RD , ■ Hold Analog Input and Begin Conversion TL/H/12441 TL/H/12441 -46 _n DATA D12-D0 - Start Acquisition ... OCR Scan
datasheet

29 pages,
1018.02 Kb

TMS320C25 me 4946 LM9140 LM4041 LM4040 ADI21xx ADC12041 TEXT
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Abstract: SCLK45 ), followed by the 13 data bits D12.D0 (Figure 4). The 3-bit control code determines: · The register to be , 3 Control Bits 13 Data Bits , . Serial-Interface Programming Commands 16-BIT 16-BIT SERIAL WORD FUNCTION C0 MSB ... Maxim Integrated Products
Original
datasheet

12 pages,
134.13 Kb

MAX535BMJA MAX535BCUA MAX535BCPA MAX535ACUA MAX535ACPA MAX535 optocoupler with schmitt trigger input schmitt trigger using ic 555 TEXT
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Abstract: D12.D0 (Figure 4). The 3-bit control code determines: · The register to be updated · The configuration , C0 3 Control Bits 13 Data Bits , MSB LSB FUNCTION C2 X 0 0 13 bits of data Load input register; DAC register ... Maxim Integrated Products
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datasheet

16 pages,
141.55 Kb

MAX535BCUA MAX535BCPA MAX535ACUA MAX535ACPA MAX5351 MAX535 TEXT
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Abstract: ), D7­D0 are active and D12­D8 are always in TRI-STATE. When the BW bit is set (BW = 1), D12­D0 are , the CS will enable the input buffers of the data pins D12­D0. The signal at this pin is used by the ADC12048 ADC12048 to latch in data on D12­D0. The sense of the WMODE pin at power-up will determine which edge of , mA IOFF TRI-STATE ® Output Leakage Current CIN D12­D0 Input Capacitance VOUT = 0V , . The digital interface consists of a 13-bit data input/output bus (D12­D0), digital control signals ... National Semiconductor
Original
datasheet

32 pages,
700.97 Kb

V44A TMS320C25 LM9140 LM4041 LM4040 ADC12048CIVF ADC12048CIV ADC12048 TEXT
datasheet frame
Abstract: ± 2.0 |xA (max) C|N D12-D0 Input Capacitance 10 PF Converter AC Characteristics The , Conversion *CSWR "*CSRD ^rdcs ! J—L 1_r DATA D12-D0 LWRSET Falling , ^OROr *■{ *CSWR *RDCS Î"" J—L ' *RD ' T_r DATA D12-D0 'wrset Falling WRHOLD Falling 'RO , /H/123S7-46 /H/123S7-46 FIGURE 7c. Sync-Out Write (WMODE = 0, BW = 1), Read and Convert Cycles _n DATA D12-D0 , _i 1_r W DATA 1_r ' 'RDHOLO DATA D12-D0 -^Valid Daïâ^- *RD DATA " *RDH0LD -^Valid ... Texas Instruments
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datasheet

35 pages,
1075.4 Kb

LM95245 SNIS148F TEXT
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