917MIPS PC7410 PC7400 2141D IEEE-754 PC740 PC750 PCX7410 MIL-STD-883 - Datasheet Archive

 

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Features · · · · · · · · · · · · · · · · · 22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated) 917MIPS 917MIPS at 500 MHz Selectable Bus Clock (14 CPU Bus Dividers Up To 9x) Seven Selectable Core-to-L2 Frequency Divisors Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V) Selectable L2 interface of 1.8V or 2.5V PD Typical 5.3W at 500 MHz, Full Operating Conditions Nap, Doze and Sleep Modes for Power Saving Superscalar (Four Instructions fetched per Clock Cycle) 4 GB Direct Addressing Range Virtual Memory: 4 hexabytes (252) 64-bit Data and 32-bit Address Bus Interface 32 KB Instruction and Data Cache Eight Independent Execution Units and Three Register Files Write-back and Write-through Operations fINT Max = 450 MHz 500 MHz fBUS Max = 133 MHz Description The PC7410 PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the PowerPCTM Reduced Instruction Set Computer (RISC) architecture. It is fully JTAG-compliant. The PC7410 PC7410 maintains some of the characteristics of G3 microprocessors: · The microprocessor provides four software controllable power-saving modes and a thermal assist unit management · PC7410 PC7410 The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units · PowerPC 7410 RISC Microprocessor Product Specification The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache interface with on-chip L2 tags In addition, the PC7410 PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency protocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVecTM technology instruction set. New features have been developed to make latency equal for double-precision and single-precision floating-point operations involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7410 PC7410 offers an optional, high-bandwidth MPX bus interface. Unlike the PC7400 PC7400, the PC7410 PC7410 does not support the 3.3V I/O on the L2 cache interface. Rev. 2141D 2141D­HIREL­02/04 Screening · CBGA Upscreenings Based on Atmel Standards · Full Military Temperature Range (Tj = -55°C, +125°C), Industrial Temperature Range (Tj = -40°C, +110°C) · CI-CGA Package Version, HiTCE Package Version G suffix CBGA 360 Ceramic Ball Grid Array GS suffix CI±CGA 360 Ceramic Ball Grid Array with Solder Column Interposer (SCI) GH suffix HITCE 360 Ceramic Ball Grid Array 2 PC7410 PC7410 2141D 2141D­HIREL­02/04 Fetcher Additional features Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor SRs (Shadow) Branch Processing Unit 128-entry ITLB 64-entry BTIC/512-entry BHT LR/CTR Instruction Queue 6-word 32-Kbyte iCache Tags IBAT Array Data MMU Dispatch Unit EA SRs (Original) 2 Instructions PA 128-entry DTLB 32-Kbyte DCache Tags DBAT Array 64-bit (2 Instructions) Reservation Station Reservation Station Reservation Station VR File Reservation Station Reservation Station Reservation Station 2-entry GPR File 6 Rename Buffers 6 Rename Buffers Load/Store Unit 32-bit Integer Unit 1 Vector ALU Integer Unit 2 Add-Multiplydivide Vector Permute Unit - Add - Reservation Station 6 Rename Buffers - Add EA Calculation Finished Stores Completed Stores System Register Unit FPR File Block Diagram Instruction MMU Instruction Unit Figure 1. PC7410 PC7410 Microprocessor Block Diagram 2141D 2141D­HIREL­02/04 128 bits (4 instructions) 64-bit Floating 64-bit Point Unit Add-Multiplydivide VSIU VCIU VFPU FPSCR VSCR 32-bit 32-bit 128-bit 128-bit 128 bits Completion Unit L2 Controller L2 Data L2 Tags Transaction L2CR Queue 8-entry Reorder Buffer Bus Interface Unit L2 Miss Data Transaction Queue Memory Subsystem Data Reload Data Reload Buffer Table L2PMCR L2 Castout 19-bit L2 Address Bus 32-bit Address Bus 64-bit Data Bus 3 PC7410 PC7410 Instruction Instruction Reload Buffer Reload Table 64- or 32-bit L2 Data Bus General Parameters Table 1 provides a summary of the general parameters of the PC7410 PC7410. Table 1. Device Parameters Parameter Description Technology 0.18 µm CMOS, six-layer metal Die size 6.32 mm × 8.26 mm (52 mm2) Transistor count 10.5 million Logic design Fully-static Packages Surface-mount 360 ceramic ball grid array (CBGA) Surface mount 360 high coefficient of thermal expansion ceramic ball grid array (HiTCE) Surface mount 360-column Ci-CGA Package Core power supply 1.8V ± 100 mV dc or 1.5V ± 50 mV dc (nominal; see Table 4 for Recommended Operating Conditions) I/O power supply 1.8V ± 100 mV dc or 2.5V ± 100 mV 3.3V ± 165 mV (603 bus only) (1) (input thresholds are configuration pin selectable) or Note: Features 1. 3.3V I/O bus not supported for 1.5V core power supply processor version. This section summarizes features of the PC7410 PC7410's implementation of the PowerPC architecture. Major features of the PC7410 PC7410 are as follows: · Branch Processing Unit ­ ­ One branch processed per cycle (plus resolving two speculations) ­ Up to one speculative stream in execution, one additional speculative stream in fetch ­ 512-entry branch history table (BHT) for dynamic prediction ­ · Four instructions fetched per clock 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots Dispatch Unit ­ Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU) ­ · Full hardware detection of dependencies (resolved in the execution units) ­ Serialization control (predispatch, postdispatch, execution serialization) Decode ­ Forwarding control ­ · Register file access ­ Partial instruction decode Completion ­ 4 8-entry completion buffer ­ Instruction tracking and peak completion of two instructions per cycle PC7410 PC7410 2141D 2141D­HIREL­02/04 PC7410 PC7410 ­ · Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization and all instruction flow changes Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands ­ Fixed-point unit 2 (FXU2)-shift, rotate, arithmetic, logical ­ Single-cycle arithmetic, shifts, rotates, logical ­ Multiply and divide support (multi-cycle) ­ · Fixed-point unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical ­ Early out multiply Three-stage Floating-point Unit and a 32-entry FPR File ­ ­ Three-cycle latency, one-cycle throughput (single or double precision) ­ Hardware support for divide ­ Hardware support for denormalized numbers ­ · Support for IEEE-754 IEEE-754 standard single- and double-precision floating-point arithmetic Time deterministic non-IEEE mode System Unit ­ · Executes CR logical instructions and miscellaneous system instructions ­ Special register transfer instructions AltiVec Unit ­ Full 128-bit data paths ­ Contains its own 32-entry 128-bit vector register file (VRF) with six renames ­ The vector ALU unit is further sub-divided into the vector simple integer unit (VSIU), the vector complex integer unit (VCIU) and the vector floating-point unit (VFPU). ­ · Two dispatchable units: vector permute unit and vector ALU unit ­ Fully pipelined Load/Store Unit ­ ­ Two-cycle load latency with one-cycle throughput ­ Effective address generation ­ Hits under misses (multiple outstanding misses) ­ Single-cycle unaligned access within double-word boundary ­ Alignment, zero padding, sign extend for integer register file ­ Floating-point internal format conversion (alignment, normalization) ­ Sequencing for load/store multiples and string operations ­ Store gathering ­ Executes the cache and TLB instructions ­ Big- and little-endian byte addressing supported ­ Misaligned little-endian supported ­ Supports FXU, FPU, and AltiVec load/store traffic ­ · One-cycle load or store cache access (byte, half-word, word, double-word) Complete support for all four architecture AltiVec DST streams Level 1 (L1) Cache Structure ­ 32K 32-byte line, 8-way set associative instruction cache (iL1) 5 2141D 2141D­HIREL­02/04 ­ ­ Single-cycle cache access ­ Pseudo least-recently-used (LRU) replacement ­ Data cache supports AltiVec LRU and transient instructions algorithm ­ Copy-back or write-through data cache (on a page-per-page basis) ­ Supports all PowerPC memory coherency modes ­ Non-blocking instruction and data cache ­ Separate copy of data cache tags for efficient snooping ­ · 32K 32-byte line, 8-way set associative data cache (dL1) No snooping of instruction cache except for ICBI instruction Level 2 (L2) Cache Interface ­ 512K, 1M and 2-Mbyte 2-way set associative L2 cache support ­ Copyback or write-through data cache (on a page basis or for all L2) ­ 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size ­ Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register-register) late-write synchronous burst SRAMs ­ Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM (either all, half or none of L2 SRAM must be configured as direct mapped. ­ Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported ­ 64-bit data bus which also support 32-bits bus mode ­ · Internal L2 cache controller and tags; external data SRAMs ­ Selectable interface voltages of 1.8V and 2.5V Memory Management Unit ­ ­ 128 entry, 2-way set associative data TLB ­ Hardware reload for TLBs ­ Four instruction BATs and four data BATs ­ Virtual memory support for up to four petabytes (252) of virtual memory ­ Real memory support for up to four gigabytes (232) of physical memory ­ · 128 entry, 2-way set associative instruction TLB Snooped and invalidated for TLBI instructions Efficient Data Flow ­ ­ dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF ­ L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s ­ Up to eight outstanding out-of-order cache misses between dL1 and L2/bus ­ Up to seven outstanding out-of-order transactions on the bus ­ Load folding to fold new dL1 misses into older outstanding load and store misses to the same line ­ Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed). ­ 6 All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are 128 bits wide Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1 PC7410 PC7410 2141D 2141D­HIREL­02/04 PC7410 PC7410 ­ · Separate additional queues for efficient buffering of outbound data (castouts, write throughs, etc.) from dL1 and L2 Bus Interface ­ Mode-compatible with 60x processor interface ­ 32-bit address bus ­ 64-bit data bus ­ Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x supported ­ · MPX bus extension to 60X processor interface ­ Selectable interface voltages of 1.8V, 2.5V and 3.3V Power Management ­ ­ Low voltage 1.8V or 1.5V processor core ­ Selectable interface voltages of 1.8V can reduce power in output buffers ­ Three static power saving modes: doze, nap, and sleep ­ · Low-power design with thermal requirements very similar to PC740 PC740 and PC750 PC750 Dynamic power management Testability ­ ­ IEEE 1149.1 JTAG interface ­ Array built-in self test (ABIST) ­ factory test only ­ · LSSD scan design Redundancy on L1 data arrays and L2 tag arrays Reliability and Serviceability ­ Parity checking on 60x and L2 cache buses 7 2141D 2141D­HIREL­02/04 Signal Description Figure 2. PC7410 PC7410 Microprocessor Signal Groups L2OVDD GND L2AVDD BR Address Arbitration BG ABB/AMON[0] Address Start TS A[0:31] Address Bus AP[0:3] TT[0:4] TBST TSIZ[0:2] Transfer Attribute GBL WT CI 1 13 49 19 1 64 1 8 1 Address Termination AACK ARTRY DBG Data Arbitration DBWO, DTI(0) 1 1 32 2 4 1 5 1 1 1 1 3 1 1 1 1 1 1 PCX7410 PCX7410 1 D[0:63] Data Transfer DP[0:7] 1 1 1 2 1 1 1 1 1 1 1 1 L2DP[0:7] DTI1 TEA L2 Cache Address/Data 1 8 1 1 L2CE L2WE L2CLKOUTA, L2CLKOUTB L2SYNC_OUT L2ZZ INT SMI MCP SRESET HRESET CKSTP_IN HIT SHDO, SHD1 RSRV TBEN EMODE QREQ QACK SYSCLK PLL_CFG[0:3] CLK_OUT VDD 20 OVDD 1 Clock Control Factory Test 1 12 Processor Status Control DRDY JTAG:COP 1 1 Interrupts Reset CKSTP_OUT 5 1 L2 Cache Clock/Control L2SYNC_IN 3 TA 8 1 64 4 DTI(2) Data Termination 1 1 DBB, DMON(0) L2DATA[0:63] 1 1 1 CHK L2ADDR[0:18] 1 L1_TSTCLK, L2_TSTCLK BVSEL L2VSEL Test Interface LSSD_MODE I/O Voltage Selection AVDD PC7410 PC7410 2141D 2141D­HIREL­02/04 PC7410 PC7410 Detailed Specification Scope This drawing describes the specific requirements for the microprocessor PC7410 PC7410 in compliance with Atmel-Grenoble standard screening. Applicable Documents 1. MIL-STD-883 MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535 MIL-PRF-38535: Appendix A: General specifications for microcircuits Requirements General The microcircuits are in accordance with the applicable documents and as specified herein. Design and Construction Terminal Connections Depending on the package, the terminal connections are as shown in Table 16, Table 4 and Figure 2. Absolute Maximum Ratings Table 2. Absolute Maximum Ratings(1) Symbol Characteristic Value VDD Core supply voltage -0.3 to 2.1(4) V (4) V (4) AVDD PLL supply voltage -0.3 to 2.1 Unit L2AVDD L2 DLL supply voltage -0.3 to 2.1 V OVDD 60x bus supply voltage -0.3 to 3.465(3)(6) V L2OVDD L2 bus supply voltage -0.3 to 2.6(3) V (2)(5) VIN Processor bus input voltage VIN L2 bus input voltage -0.3 to L2OVDD + 0,2V V VIN JTAG signal input voltage -0.3 to OVDD + 0,2V V TSTG Storage temperature range -55 to 150 °C Rework temperature 260 °C Notes: -0.3 to OVDD + 0,2V (2)(5) V 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.2V at any time including during power-on reset. 3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3. 6. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a maximum value OVDD of -0.3 to 2.6V. 9 2141D 2141D­HIREL­02/04 Figure 3. Overshoot/Undershoot Voltage (L2)OVDD + 20% (L2)OVDD + 5% (L2)OVDD VIH VIL GND GND - 0.3V GND - 0.7V Not to exceed 10% of tSYSCLK The PC7410 PC7410 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The PC7410 PC7410 "core" voltage must always be provided at nominal voltage (see Table 4 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD power pins. Table 3. Input Threshold Voltage Setting BVSEL Signal Processor Bus Input Threshold is Relative to: L2VSEL Signal(3) L2 Bus Input Threshold is Relative to: 0(1) 1.8V 0 1.8 HRESET 2.5V HRESET 2.5 1(1)(4)(5) 3.3V(7) 1 2.5 HRESET(6) 3.3V(7) HRESET Not supported (1)(2) Notes: 10 1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied. 2. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so that the two signals change state together. This is the preferred method for selecting this mode operation. 3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 should be used. 4. Default voltage setting if left unconnected (internal pulled-up). Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, the default voltage setting if left unconnected is 2.5V. 5. Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, having BVSEL = 1 selects the 2.5V threshold. 6. Parts Rev 1.4 and later only. Previous revisions do not support BVSEL = HRESET. 7. NSpec does not support the default OVDD setting of 3.3V. The BVSEL input must be tie either low or HRESET. PC7410 PC7410 2141D 2141D­HIREL­02/04 PC7410 PC7410 Recommended Operating Conditions Table 4. Recommended Operating Conditions(1) Recommended Value Unit Symbol Characteristic VDD Core supply voltage 1.8 ± 100 mV or 1.5 ± 50 mV V AVDD PLL supply voltage 1.8 ± 100 mV or 1.5 ± 50 mV V L2AVDD L2 DLL supply voltage 1.8 ± 100 mV or 1.5 ± 50 mV V OVDD Processor bus supply voltage see note (3) BVSEL = 0 1.8 ± 100 mV V BVSEL = HRESET 2.5 ± 100 mV V BVSEL = 1 or = HRESET(4) 3.3 ± 165 mV V L2VSEL = 0 1.8 ± 100 mV V 2.5 ± 100 mV V GND to OVDD V GND to L2OVDD V GND to OVDD V -55 to 125 °C OVDD (2)(3) OVDD L2OVDD L2 bus supply voltage (2) L2VSEL = 1 L2OVDD VIN Input voltage Processor bus VIN L2 Bus VIN JTAG Signals Tj Notes: Die-junction temperature or L2VSEL = HRESET 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a recommended OVDD value of 2.5V ±100 mV for BVSEL = 1. 3. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET. 4. Not supported for N spec with VDD = 1.5V 11 2141D 2141D­HIREL­02/04 Thermal Characteristics Package Characteristics Table 5. Package Thermal Characteristics CBGA RJA Unit (1)(2) 24 °C/W (1)(3) Symbol Value PC7410 PC7410 CBGA Characteristic Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board RJMA Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board 17 °C/W RJMA Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board(1)(3) 18 °C/W RJMA Junction-to-ambient thermal resistance, 400 ft/min airflow, single-layer (1s) board 16 °C/W 14 °C/W (1)(3) RJMA Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board RJMA Junction-to-ambient thermal resistance, 400 ft/min airflow, four-layer (2s2p) board 13 °C/W RJB Junction-to-board thermal resistance(4) 8 °C/W RJC Junction-to-case thermal resistance(5) < 0.1 °C/W Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 G38-87 and JEDEC JESD51-2 JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8 JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RJC for the part is less than 0.1°C/W. See "Thermal Management Information" on page 13 for more details about thermal management. The board designer can choose between several commercially available heat sink types to place on the PC7410 PC7410. For exposed-die packaging technology as in Table 5, the intrinsic conduction thermal resistance paths are shown in Figure 4. Package Thermal Characteristics for HiTCE Table 6 provides the package thermal characteristics for the PC7410 PC7410, HiTCE. Table 6. Package Thermal Characteristics for HiTCE Package Value Characteristic Symbol PC7410 PC7410 HiTCE Unit RJ 6.8 °C/W Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board(1)(2) RJMA 20.7 °C/W Junction to board thermal resistance RJB 11.0 °C/W Junction-to-bottom of balls Notes: (1) 1. Simulation, no convection air flow. 2. Per JEDEC JESD51-6 JESD51-6 with the board horizontal. Package Thermal Characteristics for CI-CGA Table 7. Package Thermal Characteristics for CI-CGA Value Characteristic Junction to board thermal resistance 12 Symbol PC7410 PC7410 CI-CGA Unit RJB 8.42 °C/W PC7410 PC7410 2141D 2141D­HIREL­02/04 PC7410 PC7410 Internal Package Conduction Resistance Figure 4 depicts the primary heat transfer path for a package with an attached heat sink mounted on a printed circuit board. Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material) and finally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a first-order analysis the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. Figure 4. C4 Package with Heat Sink Mounted on a Printed Circuit Board Radiation External Resistance Convection Heat Sink Thermal Interface Material Die Junction Internal Resistance Die/Package Package/Leads Printed Circuit Board Radiation External Resistance Thermal Management Information Convection This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design ­ the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package and mounting clip and screw assembly; see Figure 5. This spring force should not exceed 5.5 pounds of force. Ultimately, the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly and cost. Figure 5. CBGA Package Cross-section with Heat Sink Options Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Option Printed-Circuit Board 13 2141D 2141D­HIREL­02/04 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 6 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printedcircuit board (see Figure 5). This spring force should not exceed 5.5 pounds of force. Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure. The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet must have adequate mechanical strength to meet equipment shock/vibration requirements. Figure 6. Thermal Performance of Different Thermal Interface Materials Silicone Sheet (0.006") Bare Joint Floroether Oil Sheet (0.007") Graphite/Oil Sheet (0.005") Synthetic Grease Specific Thermal Resistance (K-in.2/W) 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) 14 PC7410 PC7410 2141D 2141D­HIREL­02/04 PC7410 PC7410 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: T j = T a + T r + ( jc + int + sa ) × P d where: Tj = die-junction temperature Ta = inlet cabinet ambient temperature Tr = air temperature rise within the computer cabinet jc = junction-to-case thermal resistance int = adhesive or interface material thermal resistance sa = heat sink base-to-ambient thermal resistance Pd = power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 4. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30°C to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5°C to 10°C. The thermal resistance of the thermal interface material (int) is typically about 1°C/W. Assuming a Ta of 30°C, a Tr of 5°C, a CBGA package jc = 0.03, and a power consumption (Pd) of 5.0 watts, the following expression for Tj is obtained: T j = 30°C + 5°C + ( 0,03°C / W + 1,0°C / W + sa ) × 5W For a Thermally heat sink #2328B 2328B, the heat sink-to-ambient thermal resistance (sa) versus airflow velocity is shown in Figure 7. 15 2141D 2141D­HIREL­02/04 Figure 7. Thermalloy #2328B 2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow Velocity 8 Thermalloy #2328B 2328B Pin-Fin Heat Sink (25 x 28 x 15 mm) Heat Sink Thermal Resistance (°C/W) 7 6 5 4 3 2 1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s) Assuming an air velocity of 0.5 m/s, the effective Rsa is 7°C/W, thus T j = 30°C + 5°C + ( 0,03°C / W + 1,0°C / W + 7°C / W ) × 5W , resulting in a die-junction temperature of approximately 75°C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering and Aavid Engineering offer different heat sink-to-ambient thermal resistances and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure of merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but of the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature ­ airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. 16 PC7410 PC7410 2141D 2141D­HIREL­02/04 PC7410 PC7410 Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, it is recommended to use conjugate heat transfer models for the board, as well as systemlevel designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM®. These are available upon request. Power Consideration Power Management The PC7410 PC7410 provides four power modes, selectable by setting the appropriate control bits in the MSR and HIDO registers. The four power modes are: · Full-power: This is the default power state of the PC7410 PC7410. The PC7410 PC7410 is fully powered and the internal functional units are operating at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution or external hardware. · Doze: All the functional units of the PC7410 PC7410 are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or machine check brings the PC7410 PC7410 into the full-power state. The PC7410 PC7410 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-power state takes only a few processor clock cycles. · Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The PC7410 PC7410 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or a machine check input (MCP). A return to full-power state from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping. · Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the PLL and SYSCLK. Returning the PC7410 PC7410 to the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset or a machine check input (MCP) signal after the time required to relock the PLL. 17 2141D 2141D­HIREL­02/04 Power Dissipation Table 8. Power Consumption for PC7410 PC7410 (1.8V) Processor (CPU) Frequency Power Mode Core power supply 400 MHz 1.5V 450 MHz 1.8V 500 MHz 1.5V 1.8V Unit 1.8 V Full-On Mode Typical(1)(3) 2.92 4.2 3.29 4.7 5.3 W Maximum(1)(2)(4)(5) 6.6 9.5 7.43 10.7 11.9 W 3.6 4.3 4.1 4.8 5.3 W 1.35 1.35 1.5 1.5 1.65 W 1.3 1.3 1.45 1.45 1.6 W 600 600 600 600 600 mW 1.1 1.1 1.1 1.1 1.1 W Doze Mode Maximum(1)(2)(5) Nap Mode Maximum(1)(2)(5) Sleep Mode Maximum(1)(2)(5) Sleep Mode - PLL and DLL Disabled Typical(1)(3) Maximum Notes: 18 (1)(2)(5) 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically