CYIV-51001-1 CYIV-51002-1 CYIV-51003-1 CYIV-51004-1 CYIV-51005-2 CYIV-51006-2 - Datasheet Archive

 

101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.3 Copyright © 2010 Altera Corporation. All rights

 

Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.3 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. RSDS and PPDS are registered trademarks of National Semiconductor. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Contents Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xi How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xi Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xi Section I. Device Core Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Package Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Cyclone IV Device Family Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Cyclone IV Device Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 FPGA Core Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 High-Speed Transceivers (Cyclone IV GX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Hard IP for PCI Express (Cyclone IV GX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Reference and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Chapter 2. Logic Elements and Logic Array Blocks in Cyclone IV Devices Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-3 2-3 2-4 2-4 2-4 2-5 2-6 2-7 Chapter 3. Memory Blocks in Cyclone IV Devices Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed-Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . © July 2010 Altera Corporation 3-1 3-3 3-3 3-3 3-4 3-4 3-6 3-6 Cyclone IV Device Handbook, Volume 1 iv Contents Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Single-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Shift Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 FIFO Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Input or Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Read or Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Single-Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Read-During-Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Chapter 4. Embedded Multipliers in Cyclone IV Devices Embedded Multiplier Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplier Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-3 4-3 4-3 4-4 4-4 4-5 4-5 4-7 Chapter 5. Clock Networks and PLLs in Cyclone IV Devices Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 GCLK Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 GCLK Network Clock Source Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 GCLK Network Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 clkena Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 PLLs in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Cyclone IV PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 External Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Source-Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 No Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Deterministic Latency Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 Cyclone IV Device Handbook, Volume 1 © July 2010 Altera Corporation Contents v Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Shift Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Post-Scale Counters (C0 to C4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypassing a PLL Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spread-Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5-28 5-30 5-31 5-31 5-32 5-32 5-34 5-35 5-35 5-37 5-38 5-39 5-40 5-41 5-43 5-43 5-43 Section II. I/O Interfaces Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1 Chapter 6. I/O Features in Cyclone IV Devices Cyclone IV I/O Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 I/O Element Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 PCI-Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 OCT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 On-Chip Series Termination Without Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Termination Scheme for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Voltage-Referenced I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Differential I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 External Memory Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Pad Placement and DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Pad Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 High-Speed I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 High-Speed I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 High Speed Serial Interface (HSSI) Input Reference Clock Support . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 LVDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Designing with LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 BLVDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Designing with BLVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 1 vi Contents RSDS, Mini-LVDS, and PPDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . Designing with RSDS, Mini-LVDS, and PPDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVPECL I/O Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential SSTL I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential HSTL I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . True Output Buffer Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Pad Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6-31 6-33 6-34 6-34 6-35 6-35 6-36 6-37 6-37 6-37 6-38 6-39 Chapter 7. External Memory Interfaces in Cyclone IV Devices Cyclone IV Devices Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Data and Data Clock/Strobe Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Optional Parity, DM, and Error Correction Coding Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Address and Control/Command Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Memory Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Cyclone IV Devices Memory Interfaces Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 DDR Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 DDR Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 OCT with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 Section III. System Integration Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1 Chapter 8. Configuration and Remote System Upgrades in Cyclone IV Devices Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Configuration Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Power-On Reset (POR) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Configuration File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Configuration and JTAG Pin I/O Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Configuration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 AS Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Single-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Multi-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Configuring Multiple Cyclone IV Devices with the Same Design . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Guidelines for Connecting a Serial Configuration Device to Cyclone IV Devices for an AS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Cyclone IV Device Handbook, Volume 1 © July 2010 Altera Corporation Contents vii AP Configuration (Supported Flash Memories) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AP Configuration Supported Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Word-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for Connecting Parallel Flash to Cyclone IV E Devices for an AP Interface . . . . . . . Configuring With Multiple Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimating AP Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Parallel Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring Cyclone IV Devices with Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring Cyclone IV Devices with the JRunner Software Driver . . . . . . . . . . . . . . . . . . . . . . Combining JTAG and AS Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Serial Configuration Devices In-System with the JTAG Interface . . . . . . . . . . . . JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote System Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8-21 8-22 8-24 8-25 8-25 8-27 8-27 8-29 8-30 8-31 8-32 8-35 8-36 8-39 8-39 8-43 8-44 8-51 8-52 8-52 8-54 8-56 8-61 8-67 8-68 8-69 8-69 8-70 8-70 8-73 8-74 8-77 8-78 8-79 8-80 Chapter 9. SEU Mitigation in Cyclone IV Devices Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Automated SEU Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 CRC_ERROR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Accessing Error Detection Block Through User Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Recovering from CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 1 viii Contents Chapter 10. JTAG Boundary-Scan Testing for Cyclone IV Devices IEEE Std. 1149.6 Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXTEST_PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXTEST_TRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10-3 10-5 10-5 10-5 10-6 10-7 Chapter 11. Power Requirements for Cyclone IV Devices External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Devices Driven Before Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins Remain Tri-stated During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclone IV Device Handbook, Volume 1 11-1 11-2 11-2 11-2 11-3 11-3 11-4 © July 2010 Altera Corporation Chapter Revision Dates The chapters in this book, Cyclone IV Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 Cyclone IV FPGA Device Family Overview Revised: July 2010 Part Number: CYIV-51001-1 CYIV-51001-1.3 Chapter 2 Logic Elements and Logic Array Blocks in Cyclone IV Devices Revised: November 2009 Part Number: CYIV-51002-1 CYIV-51002-1.0 Chapter 3 Memory Blocks in Cyclone IV Devices Revised: November 2009 Part Number: CYIV-51003-1 CYIV-51003-1.0 Chapter 4 Embedded Multipliers in Cyclone IV Devices Revised: February 2010 Part Number: CYIV-51004-1 CYIV-51004-1.1 Chapter 5 Clock Networks and PLLs in Cyclone IV Devices Revised: July 2010 Part Number: CYIV-51005-2 CYIV-51005-2.1 Chapter 6 I/O Features in Cyclone IV Devices Revised: July 2010 Part Number: CYIV-51006-2 CYIV-51006-2.1 Chapter 7 External Memory Interfaces in Cyclone IV Devices Revised: February 2010 Part Number: CYIV-51007-1 CYIV-51007-1.0 Chapter 8 Configuration and Remote System Upgrades in Cyclone IV Devices Revised: July 2010 Part Number: CYIV-51008-1 CYIV-51008-1.2 Chapter 9 SEU Mitigation in Cyclone IV Devices Revised: February 2010 Part Number: CYIV-51009-1 CYIV-51009-1.1 Chapter 10 JTAG Boundary-Scan Testing for Cyclone IV Devices Revised: February 2010 Part Number: CYIV-51010-1 CYIV-51010-1.1 Chapter 11 Power Requirements for Cyclone IV Devices Revised: July 2010 Part Number: CYIV-51011-1 CYIV-51011-1.2 © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 1 x Cyclone IV Device Handbook, Volume 1 Chapter Revision Dates © July 2010 Altera Corporation Additional Information About this Handbook This handbook provides comprehensive information about the Altera® Cyclone® IV family of devices. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact (Note 1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI. bold type Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf. Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Cyclone IV Design Guidelines. Italic type Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, and .pof. Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu. "Subheading Title" Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, "Typographic Conventions." © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 2 Info­xii Additional Information Visual Cue Courier type Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). 1., 2., 3., and a., b., c., and so on. Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. 1 The hand points to information that requires special attention. c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w A warning calls attention to a condition or possible situation that can cause you injury. r The angled arrow instructs you to press Enter. f The feet direct you to more information about a particular topic. Cyclone IV Device Handbook, Volume 2 © July 2010 Altera Corporation Section I. Device Core This section provides a complete overview of all features relating to the Cyclone® IV device family, which is the most architecturally advanced, high-performance, low-power FPGA in the market place. This section includes the following chapters: Chapter 1, Cyclone IV FPGA Device Family Overview Chapter 2, Logic Elements and Logic Array Blocks in Cyclone IV Devices Chapter 3, Memory Blocks in Cyclone IV Devices Chapter 4, Embedded Multipliers in Cyclone IV Devices Chapter 5, Clock Networks and PLLs in Cyclone IV Devices Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 1 1. Cyclone IV FPGA Device Family Overview CYIV-51001-1 CYIV-51001-1.3 Altera's new Cyclone® IV FPGA device family extends the Cyclone FPGA series leadership in providing the market's lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs. Built on an optimized low-power process, the Cyclone IV device family offers the following two variants: Cyclone IV E-lowest power, high functionality with the lowest cost Cyclone IV GX-lowest power and lowest cost FPGAs with 3.125 Gbps transceivers 1 f Cyclone IV E devices are offered in core voltage of 1.0 V and 1.2 V. For more information, refer to the Power Requirements for Cyclone IV Devices chapter. Providing power and cost savings without sacrificing performance, along with a low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost, small-form-factor applications in the wireless, wireline, broadcast, industrial, consumer, and communications industries. Cyclone IV Device Family Features The Cyclone IV device family offers the following features: Low-cost, low-power FPGA fabric: Up to 360 18 × 18 multipliers for DSP processing intensive applications Altera Corporation Up to 6.3 Mb of embedded memory © July 2010 6K to 150K logic elements Protocol bridging applications for under 1.5 W total power Cyclone IV Device Handbook, Volume 1 1­2 Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Features Cyclone IV GX devices offer up to eight high-speed transceivers that provide: 8B/10B 8B/10B encoder/decoder 8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface Byte serializer/deserializer (SERDES) Word aligner Rate matching FIFO TX bit slipper for Common Public Radio Interface (CPRI) Electrical idle Dynamic channel reconfiguration allowing you to change data rates and protocols on-the-fly Static equalization and pre-emphasis for superior signal integrity 150 mW per channel power consumption Data rates up to 3.125 Gbps Flexible clocking structure to support multiple protocols in a single transceiver block Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe) Gen 1: End-point and root-port configurations Up to 256-byte payload One virtual channel 2 KB retry buffer ×1, ×2, and ×4 lane configurations 4 KB receiver (Rx) buffer Cyclone IV GX devices offer a wide range of protocol support: PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps) Gigabit Ethernet (1.25 Gbps) CPRI (up to 3.072 Gbps) XAUI (3.125 Gbps) Triple rate serial digital interface (SDI) (up to 2.97 Gbps) Serial RapidIO (3.125 Gbps) Basic mode (up to 3.125 Gbps) V-by-One (up to 3.0 Gbps) DisplayPort (2.7 Gbps) Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps) OBSAI (up to 3.072 Gbps) Cyclone IV Device Handbook, Volume 1 © July 2010 Altera Corporation Chapter 1: Cyclone IV FPGA Device Family Overview Device Resources 1­3 Up to 532 user I/Os LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx Support for DDR2 SDRAM interfaces up to 200 MHz Support for QDRII SRAM and DDR SDRAM up to 167 MHz Up to eight phase-locked loops (PLLs) per device Offered in commercial and industrial temperature grades Device Resources Table 1­1 lists Cyclone IV E device resources. Resources EP4CE6 EP4CE10 EP4CE10 EP4CE15 EP4CE15 EP4CE22 EP4CE22 EP4CE30 EP4CE30 EP4CE40 EP4CE40 EP4CE55 EP4CE55 EP4CE75 EP4CE75 EP4CE115 EP4CE115 Table 1­1. Resources for the Cyclone IV E Device Family Logic elements (LEs) 6,272 10,320 15,408 22,320 28,848 39,600 55,856 75,408 114,480 Embedded memory (Kbits) 270 414 504 594 594 1,134 2,340 2,745 3,888 Embedded 18 × 18 multipliers 15 23 56 66 66 116 154 200 266 General-purpose PLLs 2 2 4 4 4 4 4 4 4 Global Clock Networks 10 10 20 20 20 20 20 20 20 User I/O Banks 8 8 8 8 8 8 8 8 8 179 179 343 153 532 532 374 426 528 Maximum user I/O © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 1 1­4 Chapter 1: Cyclone IV FPGA Device Family Overview Device Resources Table 1­2 lists Cyclone IV GX device resources. EP4CGX15 EP4CGX15 EP4CGX22 EP4CGX22 EP4CGX30 EP4CGX30 (1) EP4CGX30 EP4CGX30 (2) EP4CGX50 EP4CGX50 (8) EP4CGX75 EP4CGX75 (8) EP4CGX110 EP4CGX110 (8) EP4CGX150 EP4CGX150 (8) Table 1­2. Resources for the Cyclone IV GX Device Family 14,400 21,280 29,440 29,440 49,888 73,920 109,424 149,760 540 756 1,080 1,080 2,502 4,158 5,490 6,480 Embedded 18 × 18 multipliers 0 40 80 80 140 198 280 360 General purpose PLLs 1 2 2 4 (4) 4 (4) 4 (4) 4 (4) 4 (4) 2 (3) 2 (3) 2 (3) 2 (3) 4 (3) 4 (3) 4 (3) 4 (3) Global clock networks 20 20 20 30 30 30 30 30 High-speed transceivers (7) 2 4 4 4 8 8 8 8 2.5 2.5 2.5 3.125 3.125 3.125 3.125 3.125 1 1 1 1 1 1 1 1 9 (5) 9 (5) 9 (5) 11 (6) 11 (6) 11 (6) 11 (6) 11 (6) 72 150 150 290 310 310 475 475 Resources Logic elements (LEs) Embedded memory (Kbits) Multipurpose PLLs Transceiver maximum data rate (Gbps) PCIe (PIPE) hard IP blocks User I/O banks Maximum user I/O Notes to Table 1­2: (1) Applicable for the F169 and F324 packages. (2) Applicable for the F484 package. (3) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer to the Clock Networks and PLLs in Cyclone IV Devices chapter. (4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the Clock Networks and PLLs in Cyclone IV Devices chapter. (5) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input. (6) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input. (7) If PCIe 1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates. (8) Only two multipurpose PLLs for F484 package. Cyclone IV Device Handbook, Volume 1 © July 2010 Altera Corporation Table 1­3 lists Cyclone IV E device package offerings. Table 1­3. Package Offerings for the Cyclone IV E Device Family (Note 1) Package E144 F256 F484 F780 Size (mm) 22 × 22 17 × 17 23 × 23 29 × 29 Pitch (mm) 0.5 1.0 1.0 1.0 Device User I/O LVDS (2) User I/O LVDS (2) User I/O LVDS (2) User I/O LVDS (2) EP4CE6 91 21 179 66 - - - - EP4CE10 EP4CE10 91 21 179 66 - - - - EP4CE15 EP4CE15 81 18 165 53 343 137 - - EP4CE22 EP4CE22 79 17 153 52 - - - - EP4CE30 EP4CE30 - - - - 328 124 532 224 EP4CE40 EP4CE40 - - - - 328 124 532 224 EP4CE55 EP4CE55 - - - - 324 132 374 160 EP4CE75 EP4CE75 - - - - 292 110 426 178 EP4CE115 EP4CE115 - - - - 280 103 528 Chapter 1: Cyclone IV FPGA Device Family Overview Package Matrix © July 2010 Altera Corporation Package Matrix 230 Notes to Table 1­3: (1) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane of your PCB. Use this exposed pad for electrical connectivity and not for thermal purposes. (2) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter. 1­5 Cyclone IV Device Handbook, Volume 1 1­6 Cyclone IV Device Handbook, Volume 1 Table 1­4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts. Table 1­4. Package Offerings for the Cyclone IV GX Device Family Package N148 F169 F324 F484 F672 F896 Size (mm) 11 × 11 14 × 14 19 × 19 23 × 23 27 × 27 31 × 31 Pitch (mm) 0.5 1.0 1.0 1.0 1.0 1.0 LVDS LVDS LVDS LVDS XCVRs User I/O XCVRs User I/O XCVRs User I/O XCVRs (1) (1) (1) (1) User I/O LVDS LVDS XCVRs User I/O XCVRs (1) (1) Device User I/O EP4CGX15 EP4CGX15 72 25 2 72 25 2 - - - - - - - - - - - - EP4CGX22 EP4CGX22 - - - 72 25 2 150 64 4 - - - - - - - - - EP4CGX30 EP4CGX30 - - - 72 25 2 150 64 4 290 130 4 - - - - - - EP4CGX50 EP4CGX50 - - - - - - - - - 290 130 4 310 140 8 - - - EP4CGX75 EP4CGX75 - - - - - - - - - 290 130 4 310 140 8 - - - EP4CGX110 EP4CGX110 - - - - - - - - - 270 120 4 393 181 8 475 220 8 EP4CGX150 EP4CGX150 - - - - - - - - - 270 120 4 393 181 8 475 220 8 Note to Table 1­4: (1) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter. Chapter 1: Cyclone IV FPGA Device Family Overview Package Matrix © July 2010 Altera Corporation Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Speed Grades 1­7 Cyclone IV Device Family Speed Grades Table 1­5 lists the Cyclone IV GX devices speed grades. Table 1­5. Speed Grades for the Cyclone IV GX Device Family Device N148 F324 F484 F672 F896 C8 EP4CGX15 EP4CGX15 F169 C6, C7, C8, I7 - - - - EP4CGX22 EP4CGX22 - C6, C7, C8, I7 C6, C7, C8, I7 - - - EP4CGX30 EP4CGX30 - C6, C7, C8, I7 C6, C7, C8, I7 C6, C7, C8, I7 - - EP4CGX50 EP4CGX50 - - - C6, C7, C8, I7 C6, C7, C8, I7 - EP4CGX75 EP4CGX75 - - - C6, C7, C8, I7 C6, C7, C8, I7 - EP4CGX110 EP4CGX110 - - - C7, C8, I7 C7, C8, I7 C7, C8, I7 EP4CGX150 EP4CGX150 - - - C7, C8, I7 C7, C8, I7 C7, C8, I7 Table 1­6 lists the Cyclone IV E devices speed grades. Table 1­6. Speed Grades for the Cyclone IV E Device Family (Note 1), (2) Device E144 F256 F484 F780 EP4CE6 C8L, C9L, I8L C8L, C9L, I8L C6, C7, C8, I7, A7 C6, C7, C8, I7, A7 - - EP4CE10 EP4CE10 C8L, C9L, I8L C8L, C9L, I8L C6, C7, C8, I7, A7 C6, C7, C8, I7, A7 - - EP4CE15 EP4CE15 EP4CE22 EP4CE22 C8L, C9L, I8L C6, C7, C8, I7 C8L, C9L, I8L C8L, C9L, I8L C6, C7, C8, I7, A7 C6, C7, C8, I7, A7 C8L, C9L, I8L C8L, C9L, I8L C6, C7, C8, I7, A7 C6, C7, C8, I7, A7 - - - EP4CE30 EP4CE30 - - C8L, C9L, I8L C6, C7, C8, I7, A7 C8L, C9L, I8L C6, C7, C8, I7 EP4CE40 EP4CE40 - - C8L, C9L, I8L C6, C7, C8, I7, A7 C8L, C9L, I8L C6, C7, C8, I7 EP4CE55 EP4CE55 - - C8L, C9L, I8L C6, C7, C8, I7 C8L, C9L, I8L C6, C7, C8, I7 EP4CE75 EP4CE75 - - C8L, C9L, I8L C6, C7, C8, I7 C8L, C9L, I8L C6, C7, C8, I7 EP4CE115 EP4CE115 - - C8L, C9L, I8L C7, C8, I7 C8L, C9L, I8L C7, C8, I7 Notes to Table 1­6: (1) C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage. (2) C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage. © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 1 1­8 Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Architecture Cyclone IV Device Family Architecture This section describes Cyclone IV device architecture and contains the following topics: "FPGA Core Fabric" "I/O Features" "Clock Management" "External Memory Interfaces" "Configuration" "High-Speed Transceivers (Cyclone IV GX Devices Only)" "Hard IP for PCI Express (Cyclone IV GX Devices Only)" FPGA Core Fabric Cyclone IV devices leverage the same core fabric as the very successful Cyclone series devices. The fabric consists of LEs, made of 4-input look up tables (LUTs), memory blocks, and multipliers. Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAM memory. You can configure the M9K blocks as single port, simple dual port, or true dual port RAM, as well as FIFO buffers or ROM. They can also be configured to implement any of the data widths in Table 1­7. Table 1­7. M9K Block Data Widths for Cyclone IV Device Family Mode Data Width Configurations Single port or simple dual port ×1, ×2, ×4, ×8/9, ×16/18, and ×32/36 True dual port ×1, ×2, ×4, ×8/9, and ×16/18 The multiplier architecture in Cyclone IV devices is the same as in the existing Cyclone series devices. The embedded multiplier blocks can implement an 18 × 18 or two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP including finite impulse response (FIR), fast Fourier transform (FFT), and numerically controlled oscillator (NCO) functions for use with the multiplier blocks. The Quartus® II design software's DSP Builder tool integrates MathWorks Simulink and MATLAB design environments for a streamlined DSP design flow. f For more information, refer to the Logic Elements and Logic Array Blocks in Cyclone IV Devices, Memory Blocks in Cyclone IV Devices, and Embedded Multipliers in Cyclone IV Devices chapters. Cyclone IV Device Handbook, Volume 1 © July 2010 Altera Corporation Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Architecture 1­9 I/O Features Cyclone IV device I/O supports programmable bus hold, programmable pull-up resistors, programmable delay, programmable drive strength, programmable slew-rate control to optimize signal integrity, and hot socketing. Cyclone IV devices support calibrated on-chip series termination (Rs OCT) or driver impedance matching (Rs) for single-ended I/O standards. In Cyclone IV GX devices, the high-speed transceiver I/Os are located on the left side of the device. The top, bottom, and right sides can implement general-purpose user I/Os. Table 1­8 lists the I/O standards that Cyclone IV devices support. Table 1­8. I/O Standards Support for the Cyclone IV Device Family Type I/O Standard Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X Differential I/O SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS The LVDS SERDES is implemented in the core of the device using logic elements. f For more information, refer to the I/O Features in Cyclone IV Devices chapter. Clock Management Cyclone IV devices include up to 30 global clock (GCLK) networks and up to eight PLLs with five outputs per PLL to provide robust clock management and synthesis. You can dynamically reconfigure Cyclone IV device PLLs in user mode to change the clock frequency or phase. Cyclone IV GX devices support two types of PLLs: multipurpose PLLs and generalpurpose PLLs: f Use multipurpose PLLs for clocking the transceiver blocks. You can also use them for general-purpose clocking when they are not used for transceiver clocking. Use general purpose PLLs for general-purpose applications in the fabric and periphery, such as external memory interfaces. Some of the general purpose PLLs can support transceiver clocking. For more information, refer to the Clock Networks and PLLs in Cyclone IV Devices chapter. External Memory Interfaces Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces on the top, bottom, and right sides of the device. Cyclone IV E devices also support these interfaces on the left side of the device. Interfaces may span two or more sides of the device to allow more flexible board design. The Altera® DDR SDRAM memory interface solution consists of a PHY interface and a memory controller. Altera supplies the PHY IP and you can use it in conjunction with your own custom memory controller or an Altera-provided memory controller. Cyclone IV devices support the use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces. © July 2010 Altera Corporation Cyclone IV Device Handbook, Volume 1 1­10 Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Architecture f For more information, refer to the External Memory Interfaces in Cyclone IV Devices chapter. Configuration Cyclone IV devices use SRAM cells to store configuration data. Configuration data is downloaded to the Cyclone IV device each time the device powers up. Low-cost configuration options include the Altera EPCS family serial flash devices and commodity parallel flash configuration options. These options provide the flexibility for general-purpose applications and the ability to meet specific configuration and wake-up time requirements of the applications. Table 1­9 lists which configuration schemes are supported by Cyclone IV devices. Table 1­9. Configuration Schemes for Cyclone IV Device Family Devices Supported Configuration Scheme Cyclone IV GX AS, PS, JTAG, and FPP (1) Cyclone IV E AS, AP, PS, FPP, and JTAG Note to Table 1­9: (1) The FPP configuration scheme is only supported by the EP4CGX30F484 EP4CGX30F484 and EP4CGX50/75/110/150 EP4CGX50/75/110/150 devices. IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pins support IEEE 1149.1 (JTAG) for boundary scan testing. f For more information, refer to the JTAG Boundary-Scan Testing for Cyclone IV Devices chapter. For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you must use passive serial (PS) configuration mode for the EP4CGX15/22/30 EP4CGX15/22/30 devices and use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 EP4CGX30F484 and EP4CGX50/75/110/150 EP4CGX50/75/110/150 devices. f For more information, refer to the Configuration and Remote System Upgrades in Cyclone IV Devices chapter. The cyclical redundancy check (CRC) error detection feature during user mode is supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only supported for the devices with the core voltage of 1.2 V. f For more information about CRC error detection, refer to the SEU Mitigation in Cyclone IV Devices chapter. Cyclone IV Device Handbook, Volume 1 © July 2010 Altera Corporation Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Architecture 1­11 High-Speed Transceivers (Cyclone IV GX Devices Only) Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that can operate independently. These blocks support multiple industry-standard communication protocols, as well as Basic mode, which you can use to implement your own proprietary protocols. Each transceiver channel has its own pre-emphasis and equalization circuitry, which you can set at compile time to optimize signal integrity and reduce bit error rates. Transceiver blocks also support dynamic reconfiguration, allowing you to change data rates and protocols on-the-fly. Figure 1­1 shows the structure of the Cyclone IV GX transceiver. Figure 1­1. Transceiver Channel for the Cyclone IV GX Device Transmitter Channel PCS tx_dataout Serializer rx_datain CDR Word Aligner Receiver Channel PMA Rate Match FIFO 8B10B 8B10B Decoder Byte Deserializer Byte Ordering Receiver Channel PCS RX Phase Compensation FIFO f 8B10B 8B10B Encoder Byte Serializer PIPE Interface PCI Express hard IP TX Phase Compensation FIFO Transceiver Channel PMA Deserializer FPGA Fabric For more information, refer to the Cyclone IV Transceivers Architecture chapter. Hard IP for PCI Express (Cyclone IV GX Devices Only) Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE) in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that implements the PHY-MAC layer, Data Link Layer, and Transaction Layer functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point configurations. This pre-verified hard IP block reduces risk, design time, timing closure, and verification. You can configure the block with the Quartus II software's PCI Express Compiler, which guides you through the process step by step. f © July 2010 For more information, refer to the PCI Express Compiler User Guide. Altera Corporation Cyclone IV Device Handbook, Volume 1 1­12 Chapter 1: Cyclone IV FPGA Device Family Overview Reference and Ordering Information Reference and Ordering Information Figure 1­2 shows the ordering codes for Cyclone IV GX devices. Figure 1­2. Packaging Ordering Information for the Cyclone IV GX Device EP4CGX 30 C F 19 C Family Signature 7 N Optional Suffix Indicates specific device shipment method ES: Engineering sample N: Lead-free devices EP4CGX Device Density 15, 22, 30, 50, 75 110, 150 Speed Grade 6, 7, or 8 with 6 being the fastest Transceiver Count B: 2 C: 4 D: 8 Operating Temperature C: Commercial temperature (tJ = 0° C to 85° C) Package Type N: Quad Flat Pack No Lead (QFN) F: FineLine BGA (FBGA) Cyclone IV Device Handbook, Volume 1 Package I: Industrial temperature (tJ = -40° C to 100° C) 11 = 148 pins 14 = 169 pins 19 = 324 pins 23 = 484 pins 27 = 672 pins 31 = 896 pins © July 2010 Altera Corporation Chapter 1: Cyclone IV FPGA Device Family Overview Document Revision History 1­13 Figure 1­3 shows the ordering codes for Cyclone IV E devices. Figure 1­3. Packaging Ordering Information for the Cyclone IV E Device EP4CE F 40 29 C 8 N Family Signature Optional Suffix EP4CE Indicates specific device shipment method N: Lead-free devices ES: Engineering sample L: Low-voltage devices Device Density 6, 10, 15, 22, 30, 40, 55, 75, 115 Speed Grade 6, 7, 8 or 9 with 6 being the fastest Package Type F: Fine Line BGA (FBGA) E: Enhanced Thin Quad Flat Pack Operating Temperature C: Commercial temperature (tJ = 0° C to 85° C) Package 17 = 256 pins 22 = 144 pins 23 = 484 pins 29 = 780 pins I: Industrial temperature (tJ = -40° C to 100° C) A: Automotive temperature (tJ = -40° C to 125° C) Document Revision History Table 1­10 lists the revision history for this chapter. Table 1­10. Document Revision History Date Version July 2010 1.3 March 2010 1.2 Changes Made Added the "Cyclone IV Device Family Speed Grades" and "Configuration" sections. Added Figure 1­3 to include Cyclone IV E Device Packaging Ordering Information. Updated Table 1­2, Table 1­4, and Table 1­5 for Cyclone IV GX devices. Altera Corporation Added Cyclone IV E devices in Table 1­1, Table 1­3, and Table 1­6 for the Quartus II software version 9.1 SP1 release. © July 2010 Minor text edits. 1.0 Updated Figure 1­3. November 2009 Updated Table 1­3 and Table 1­6. 1.1 Updated Table 1­2 to include F484 package information. February 2010 Minor text edits. Initial release. Cyclone IV Device Handbook, Volume 1 1­14 Cyclone IV Device Handbook, Volume 1 Chapter 1: Cyclone IV FPGA Device Family Overview Document Revision History © July 2010 Altera Corporation 2. Logic Elements and Logic Array Blocks in Cyclone IV Devices CYIV-51002-1 CYIV-51002-1.0 This chapter contains feature definitions for logic elements (LEs) and logic array blocks (LABs). Details are provided on how LEs work, how LABs contain groups of LEs, and how LABs interface with the other blocks in Cyclone® IV devices. Logic Elements Logic elements (LEs) are the smallest units of logic in the Cyclone IV device architecture. LEs are compact and provide advanced features with efficient logic usage. Each LE has the following features: A four-input look-up table (LUT), which can implement any function of four variables A programmable register A carry chain connection A register chain connection The ability to drive the following interconnects: Local Row Column Register chain Direct link © November 2009 Register packing support Register feedback support Altera Corporation Cyclone IV Device Handbook, Volume 1 2­2 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Logic Elements Figure 2­1 shows the LEs for Cyclone IV devices. Figure 2­1. Cyclone IV Device LEs Register Chain Routing from previous LE LE Carry-In data 1 data 2 data 3 Register Bypass LAB-Wide Synchronous LAB-Wide Programmable Synchronous Load Register Clear Synchronous Load and Clear Logic Look-Up Table Carry Chain (LUT) data 4 D Q ENA CLRN labclr1 labclr2 Chip-Wide Reset Register Feedback Asynchronous Clear Logic Row, Column, And Direct Link Routing Row, Column, And Direct Link Routing Local Routing (DEV_CLRn) Clock & Clock Enable Select LE Carry-Out Register Chain Output labclk1 labclk2 labclkena1 labclkena2 LE Features You can configure the programmable register of each LE for D, T, JK, or SR flipflop operation. Each register has data, clock, clock enable, and clear inputs. Signals that use the global clock network, general-purpose I/O pins, or any internal logic can drive the clock and clear control signals of the register. Either general-purpose I/O pins or the internal logic can drive the clock enable. For combinational functions, the LUT output bypasses the register and drives directly to the LE outputs. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output independently drives these three outputs. Two LE outputs drive the column or row and direct link routing connections, while one LE drives the local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated functions. The LAB-wide synchronous load control signal is not available when using register packing. For more information about the synchronous load control signal, refer to "LAB Control Signals" on page 2­6. The register feedback mode allows the register output to feed back into the LUT of the same LE to ensure that the register is packed with its own fan-out LUT, providing another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output. Cyclone IV Device Handbook, Volume 1 © November 2009 Altera Corporation Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices LE Operating Modes 2­3 In addition to the three general routing outputs, LEs in an LAB have register chain outputs, which allows registers in the same LAB to cascade together. The register chain output allows the LUTs to be used for combinational functions and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. LE Operating Modes Cyclone IV LEs operate in the following modes: Normal mode Arithmetic mode The Quartus® II software automatically chooses the appropriate mode for common functions, such as counters, adders, subtractors, and arithmetic functions, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions. You can also create special-purpose functions that specify which LE operating mode to use for optimal performance, if required. Normal Mode Normal mode is suitable for general logic applications and combinational functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (Figure 2­2). The Quartus II Compiler automatically selects the carry-in (cin) or the data3 signal as one of the inputs to the LUT. LEs in normal mode support packed registers and register feedback. Figure 2­2 shows LEs in normal mode. Figure 2­2. Cyclone IV Device LEs in Normal Mode Register Chain Connection sload sclear (LAB Wide) (LAB Wide) Packed Register Input D Row, Column, and Direct Link Routing ENA CLRN Row, Column, and Direct Link Routing Q data1 data2 data3 cin (from cout of previous LE) data4 Four-Input LUT clock (LAB Wide) ena (LAB Wide) Local Routing aclr (LAB Wide) Register Bypass © November 2009 Altera Corporation Register Feedback Register Chain Output Cyclone IV Device Handbook, Volume 1 2­4 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Logic Array Blocks Arithmetic Mode Arithmetic mode is ideal for implementing adders, counters, accumulators, and comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry chain (Figure 2­3). LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Register feedback and register packing are supported when LEs are used in arithmetic mode. Figure 2­3 shows LEs in arithmetic mode. Figure 2­3. Cyclone IV Device LEs in Arithmetic Mode Packed Register Input Register Chain Connection sload sclear (LAB Wide) (LAB Wide) data4 data1 data2 Three-Input LUT D ENA CLRN data3 Three-Input LUT cin (from cout of previous LE) Row, Column, and Direct link routing Row, Column, and Direct link routing Q clock (LAB Wide) ena (LAB Wide) Local Routing aclr (LAB Wide) cout Register Chain Output Register Bypass Register Feedback The Quartus II Compiler automatically creates carry chain logic during design processing. You can also manually create the carry chain logic during design entry. Parameterized functions, such as LPM functions, automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 16 LEs by automatically linking LABs in the same column. For enhanced fitting, a long carry chain runs vertically, which allows fast horizontal connections to M9K memory blocks or embedded multipliers through direct link interconnects. For example, if a design has a long carry chain in an LAB column next to a column of M9K memory blocks, any LE output can feed an adjacent M9K memory block through the direct link interconnect. If the carry chains run horizontally, any LAB which is not next to the column of M9K memory blocks uses other row or column interconnects to drive a M9K memory block. A carry chain continues as far as a full column. Logic Array Blocks Logic array blocks (LABs) contain groups of LEs. Topology Each LAB consists of the following features: 16 LEs Cyclone IV Device Handbook, Volume 1 © November 2009 Altera Corporation Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Logic Array Blocks LAB control signals LE carry chains Register chains 2­5 Local interconnect The local interconnect transfers signals between LEs in the same LAB. Register chain connections transfer the output of one LE register to the adjacent LE register in an LAB. The Quartus II Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local and register chain connections for performance and area efficiency. Figure 2­4 shows the LAB structure for Cyclone IV devices. Figure 2­4. Cyclone IV Device LAB Structure Row Interconnect Column Interconnect Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link interconnect to adjacent block Direct link interconnect to adjacent block LAB Local Interconnect LAB Interconnects The LAB local interconnect is driven by column and row interconnects and LE outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM blocks, and embedded multipliers from the left and right can also drive the local interconnect of a LAB through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive up to 48 LEs through fast local and direct link interconnects. © November 2009 Altera Corporation Cyclone IV Device Handbook, Volume 1 2­6 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices LAB Control Signals Figure 2­5 shows the direct link connection. Figure 2­5. Cyclone IV Device Direct Link Connection Direct link interconnect from right LAB, M9K memory block, embedded multiplier, PLL, or IOE output Direct link interconnect from left LAB, M9K memory block, embedded multiplier, PLL, or IOE output Direct link interconnect to right Direct link interconnect to left Local Interconnect LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include: Two clocks Two clock enables Two asynchronous clears One synchronous clear One synchronous load You can use up to eight control signals at a time. Register packing and synchronous load cannot be used simultaneously. Each LAB can have up to four non-global control signals. You can use additional LAB control signals as long as they are global signals. Synchronous clear and load signals are useful for implementing counters and other functions. The synchronous clear and synchronous load signals are LAB-wide signals that affect all registers in the LAB. Each LAB can use two clocks and two clock enable signals. The clock and clock enable signals of each LAB are linked. For example, any LE in a particular LAB using the labclk1 signal also uses the labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock enable signal turns off the LAB-wide clock. The LAB row clocks [5.0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrack interconnect inherent low skew allows clock and control signal distribution in addition to data distribution. Cyclone IV Device Handbook, Volume 1 © November 2009 Altera Corporation Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Document Revision History 2­7 Figure 2­6 shows the LAB control signal generation circuit. Figure 2­6. Cyclone IV Device LAB-Wide Control Signals Dedicated LAB Row Clocks 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclkena2 labclkena1 labclk1 labclk2 synclr labclr1 syncload labclr2 LAB-wide signals control the logic for the clear signal of the register. The LE directly supports an asynchronous clear function. Each LAB supports up to two asynchronous clear signals (labclr1 and labclr2). A LAB-wide asynchronous load signal to control the logic for the preset signal of the register is not available. The register preset is achieved with a NOT gate push-back technique. Cyclone IV devices only support either a preset or asynchronous clear signal. In addition to the clear port, Cyclone IV devices provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals. Document Revision History Table 2­1 shows the revision history for this chapter. Table 2­1. Document Revision History Date November 2009 © November 2009 Version 1.0 Altera Corporation Changes Made Initial release. Cyclone IV Device Handbook, Volume 1 2­8 Cyclone IV Device Handbook, Volume 1 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Document Revision History © November 2009 Altera Corporation 3. Memory Blocks in Cyclone IV Devices CYIV-51003-1 CYIV-51003-1.0 Cyclone® IV devices feature embedded memory structures to address the on-chip memory needs of Altera® Cyclone IV device designs. The embedded memory structure consists of columns of M9K memory blocks that you can configure to provide various memory functions, such as RAM, shift registers, ROM, and FIFO buffers. This chapter contains the following sections: "Memory Modes" on page 3­7 "Clocking Modes" on page 3­14 "Design Considerations" on page 3­15 Overview M9K blocks support the following features: Independent read-enable (rden) and write-enable (wren) signals for each port Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs Variable port configurations Single-port and simple dual-port modes support for all port widths True dual-port (one read and one write, two reads, or two writes) operation Byte enables for data input masking during writes Two clock-enable control signals for each port (port A and port B) © November 2009 8,192 memory bits per block (9,216 bits per block including parity) Initialization file to pre-load memory content in RAM and ROM modes Altera Corporation Cyclone IV Device Handbook, Volume 1 3­2 Chapter 3: Memory Blocks in Cyclone IV Devices Overview Table 3­1 lists the features supported by the M9K memory. Table 3­1. Summary of M9K Memory Features Feature M9K Blocks 8192 × 1 4096 × 2 2048 × 4 1024 × 8 Configurations (depth × width) 1024 × 9 512 × 16 512 × 18 256 × 32 256 × 36 Parity bits v Byte enable v Packed mode v Address clock enable v Single-port mode v Simple dual-port mode v True dual-port mode v Embedded shift register mode (1) v ROM mode v FIFO buffer (1) v Simple dual-port mixed width support v True dual-port mixed width support (2) v Memory initialization file (.mif) v Mixed-clock mode v Power-up condition Outputs cleared Register asynchronous clears Latch asynchronous clears Write or read operation triggering Read address registers and output registers only Output latches only Write and read: Rising clock edges Same-port read-during-write Outputs set to Old Data or New Data Mixed-port read-during-write Outputs set to Old Data or Don't Care Notes to Table 3­1: (1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control logic. (2) Width modes of ×32 and ×36 are not available. f For information about the number of M9K memory blocks for Cyclone IV devices, refer to the Cyclone IV Device Family Overview chapter in volume 1 of the Cyclone IV Device Handbook. Cyclone IV Device Handbook, Volume 1 © November 2009 Altera Corporation Chapter 3: Memory Blocks in Cyclone IV Devices Overview 3­3 Control Signals The clock-enable control signal controls the clock entering the input and output registers and the entire M9K memory block. This signal disables the clock so that the M9K memory block does not see any clock edges and does not perform any operations. The rden and wren control signals control the read and write operations for each port of M9K memory blocks. You can disable the rden or wren signals independently to save power whenever the operation is not required. Parity Bit Support Parity checking for error detection is possible with the parity bit along with internal logic resources. Cyclone IV devices M9K memory blocks support a parity bit for each storage byte. You can use this bit as either a parity bit or as an additional data bit. No parity function is actually performed on this bit. Byte Enable Support Cyclone IV devices M9K memory blocks support byte enables that mask the input data so that only specific bytes of data are written. The unwritten bytes retain the previous written value. The wren signals, along with the byte-enable (byteena) signals, control the write operations of the RAM block. The default value of the byteena signals is high (enabled), in which case writing is controlled only by the wren signals. There is no clear port to the byteena registers. M9K blocks support byte enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits. Byte enables operate in one-hot manner, with the LSB of the byteena signal corresponding to the least significant byte of the data bus. For example, if byteena = 01 and you are using a RAM block in ×18 mode, data[8.0] is enabled and data[17.9] is disabled. Similarly, if byteena = 11, both data[8.0] and data[17.9] are enabled. Byte enables are active high. Table 3­2 lists the byte selection. Table 3­2. byteena for Cyclone IV Devices M9K Blocks (Note 1) Affected Bytes byteena[3.0] datain ×16 datain ×18 datain ×32 datain ×36 [0] = 1 [7.0] [8.0] [7.0] [8.0] [1] = 1 [15.8] [17.9] [15.8] [17.9] [2] = 1 - - [23.16] [26.18] [3] = 1 - - [31.24] [35.27] Note to Table 3­2: (1) Any combination of byte enables is possible. © November 2009 Altera Corporation Cyclone IV Device Handbook, Volume 1 3­4 Chapter 3: Memory Blocks in Cyclone IV Devices Overview Figure 3­1 shows how the wren and byteena signals control the RAM operations. Figure 3­1. Cyclone IV Devices byteena Functional Waveform (Note 1) inclock wren rden an address data a0 a1 XXXX byteena contents at a1 10 a1 01 a2 XXXX 11 FFFF XX ABFF FFFF FFCD FFFF contents at a2 q (asynch) a0 ABCD XX contents at a0 a2 doutn ABFF ABCD FFCD ABCD ABFF FFCD ABCD Note to Figure 3­1: (1) For this functional waveform, New Data mode is selected. When a byteena bit is deasserted during a write cycle, the old data in the memory appears in the corresponding data-byte output. When a byteena bit is asserted during a write cycle, the corresponding data-byte output depends on the setting chosen in the Quartus® II software. The setting can either be the newly written data or the old data at that location. Packed Mode Support Cyclone IV devices M9K memory blocks support packed mode. You can implement two single-port memory blocks in a single block under the following conditions: Each of the two independent block sizes is less than or equal to half of the M9K block size. The maximum data width for each independent block is 18 bits wide. Each of the single-port memory blocks is configured in single-clock mode. For more information about packed mode support, refer to "Single-Port Mode" on page 3­7 and "Single-Clock Mode" on page 3­15. Address Clock Enable Support Cyclone IV devices M9K memory blocks support an active-low address clock enable, which holds the previous address value for as long as the addressstall signal is high (addressstall = '1'). When you configure M9K memory blocks in dual-port mode, each port has its own independent address clock enable. Figure 3­2 shows an address clock enable block diagram. The address register output feeds back to its input using a multiplexer. The multiplexer output is selected by the address clock enable (addressstall) signal. Cyclone IV Device Handbook, Volume 1 © November 2009 Altera Corporation Chapter 3: Memory Blocks in Cyclone IV Devices Overview 3­5 Figure 3­2. Cyclone IV Devices Address Clock Enable Block Diagram address[0] address[0] register address[0] address[N] address[N] register address[N] addressstall clock The address clock enable is typically used to improve the effectiveness of cache memory applications during a cache-miss. The default value for the address clock enable signals is low. Figure 3­3 and Figure 3­4 show the address clock enable waveform during read and write cycles, respectively. Figure 3­3. Cyclone IV Devices Address Clock Enable During Read Cycle Waveform inclock rdaddress a0 a1 a2 a3 a4 a5 a6 rden addressstall latched address (inside memory) an q (synch) doutn-1 q (asynch) © November 2009 Altera Corporation doutn doutn dout0 a4 a1 a0 dout0 dout1 dout1 dout1 dout1 dout1 a5 dout1 dout4 dout4 dout5 Cyclone IV Device Handbook, Volume 1 3­6 Chapter 3: Memory Blocks in Cyclone IV Devices Overview Figure 3­4. Cyclone IV Devices Address Clock Enable During Write Cycle Waveform inclock a0 a1 a2 a3 a4 a5 a6 00 wraddress 01 02 03 04 05 06 data wren addressstall latched address (inside memory) contents at a0 contents at a1 an a1 a0 a4 a5 00 XX 01 XX 03 02 contents at a2 XX contents at a3 XX contents at a4 04 XX XX contents at a5 05 Mixed-Width Support M9K memory blocks support mixed data widths. When using simple dual-port, true dual-port, or FIFO modes, mixed width support allows you to read and write different data widths to an M9K memory block. For more information about the different widths supported per memory mode, refer to "Memory Modes" on page 3­7. Asynchronous Clear Cyclone IV devices support asynchronous clears for read address registers, output registers, and output latches only. Input registers other than read address registers are not supported. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are immediately seen. If your RAM does not use output registers, you can still clear the RAM outputs using the output latch asynchronous clear feature. 1 Asserting asynchronous clear to the read address register during a read operation may corrupt the memory content. Figure 3­5 shows the functional waveform for the asynchronous clear feature. Figure 3­5. Output Latch Asynchronous Clear Waveform clk aclr aclr at latch q Cyclone IV Device Handbook, Volume 1 a1 a2 a0 a1 © November 2009 Altera Corporation Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes 1 f 3­7 You can selectively enable asynchronous clears per logical memory using the Quartus II RAM MegaWizardTM Plug-In Manager. For more information, refer to the RAM Megafunction User Guide. There are three ways to reset registers in the M9K blocks: Power up the device Use the aclr signal for output register only Assert the device-wide reset signal using the DEV_CLRn option Memory Modes Cyclone IV devices M9K memory blocks allow you to implement fully-synchronous SRAM memory in multiple modes of operation. Cyclone IV devices M9K memory blocks do not support asynchronous (unregistered) memory inputs. M9K memory blocks support the following modes: Simple dual-port True dual-port Shift-register ROM 1 Single-port FIFO Violating the setup or hold time on the M9K memory block input registers may corrupt memory contents. This applies to both read and write operations. Single-Port Mode Single-port mode supports non-simultaneous read and write operations from a single address. Figure 3­6 shows the single-port memory configuration for Cyclone IV devices M9K memory blocks. Figure 3­6. Single-Port Memory (Note 1), (2) data[ ] address[ ] wren byteena[] addressstall inclock inclocken rden aclr q[] outclock outclocken Notes to Figure 3­6: (1) You can implement two single-port memory blocks in a single M9K block. (2) For more information, refer to "Packed Mode Support" on page 3­4. © November 2009 Altera Corporation Cyclone IV Device Handbook, Volume 1 3­8 Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes During a write operation, the behavior of the RAM outputs is configurable. If you activate rden during a write operation, the RAM outputs show either the new data being written or the old data at that address. If you perform a write operation with rden deactivated, the RAM outputs retain the values they held during the most recent active rden signal. To choose the desired behavior, set the Read-During-Write option to either New Data or Old Data in the RAM MegaWizard Plug-In Manager in the Quartus II software. For more information about read-during-write mode, refer to "Read-During-Write Operations" on page 3­15. The port width configurations for M9K blocks in single-port mode are as follow: 8192 × 1 4096 × 2 2048 × 4 1024 × 8 1024 × 9 512 × 16 512 × 18 256 × 32 256 × 36 Figure 3­7 shows a timing waveform for read and write operations in single-port mode with unregistered outputs. Registering the outputs of the RAM simply delays the q output by one clock cycle. Figure 3­7. Cyclone IV Devices Single-Port Mode Timing Waveform clk_a wren_a rden_a address_a data_a q_a (old data) q_a (new data) Cyclone IV Device Handbook, Volume 1 a0 A a1 B C D E F a0(old data) A B a1(old data) D E A B C D E F © November 2009 Altera Corporation Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes 3­9 Simple Dual-Port Mode Simple dual-port mode supports simultaneous read and write operations to different locations. Figure 3­8 shows the simple dual-port memory configuration. Figure 3­8. Cyclone IV Devices Simple Dual-Port Memory data[ ] wraddress[ ] wren byteena[] wr_addressstall wrclock wrclocken aclr (Note 1) rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken Note to Figure 3­8: (1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown. Cyclone IV devices M9K memory blocks support mixed-width configurations, allowing different read and write port widths. Table 3­3 lists mixed-width configurations. Table 3­3. Cyclone IV Devices M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port 8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 256 × 32 1024 × 9 512 × 18 256 × 36 8192 × 1 v v v v v v - - - 4096 × 2 v v v v v v - - - 2048 × 4 v v v v v v - - - 1024 × 8 v v v v v v - - - 512 × 16 v v v v v v - - - 256 × 32 v v v v v v - - - 1024 × 9 - - - - - - v v v 512 × 18 - - - - - - v v v 256 × 36 - - - - - - v v v Read Port In simple dual-port mode, M9K memory blocks support separate wren and rden signals. You can save power by keeping the rden signal low (inactive) when not reading. Read-during-write operations to the same address can either output "Don't Care" data at that location or output "Old Data". To choose the desired behavior, set the Read-During-Write option to either Don't Care or Old Data in the RAM MegaWizard Plug-In Manager in the Quartus II software. For more information about this behavior, refer to "Read-During-Write Operations" on page 3­15. © November 2009 Altera Corporation Cyclone IV Device Handbook, Volume 1 3­10 Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes Figure 3­9 shows the timing waveform for read and write operations in simple dual-port mode with unregistered outputs. Registering the outputs of the RAM simply delays the q output by one clock cycle. Figure 3­9. Cyclone IV Devices Simple Dual-Port Timing Waveform wrclock wren wraddress an-1 data din-1 a0 a1 a2 a3 din a4 a5 din4 an din5 a6 din6 rdclock rden rdaddress q (asynch) bn doutn-1 b0 doutn b1 b2 b3 dout0 True Dual-Port Mode True dual-port mode supports any combination of two-port operations: two reads, two writes, or one read and one write, at two different clock frequencies. Figure 3­10 shows Cyclone IV devices true dual-port memory configuration. Figure 3­10. Cyclone IV Devices True Dual-Port Memory data_a[ ] address_a[ ] wren_a byteena_a[] addressstall_a clock_a clocken_a rden_a aclr_a q_a[] (Note 1) data_b[ ] address_b[] wren_b byteena_b[] addressstall_b clock_b clocken_b rden_b aclr_b q_b[] Note to Figure 3­10: (1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown. 1 The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit (18-bit with parity). Cyclone IV Device Handbook, Volume 1 © November 2009 Altera Corporation Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes 3­11 Table 3­4 lists the possible M9K block mixed-port width configurations. Table 3­4. Cyclone IV Devices M9K Block Mixed-Width Configurations (True Dual-Port Mode) Write Port 8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 1024 × 9 512 × 18 8192 × 1 v v v v v - - 4096 × 2 v v v v v - - 2048 × 4 v v v v v - - 1024 × 8 v v v v v - - 512 × 16 v v v v v - - 1024 × 9 - - - - - v v 512 × 18 - - - - - v v Read Port In true dual-port mode, M9K memory blocks support separate wren and rden signals. You can save power by keeping the rden signal low (inactive) when not reading. Read-during-write operations to the same address can either output "New Data" at that location or "Old Data". To choose the desired behavior, set the Read-During-Write option to either New Data or Old Data in the RAM MegaW