CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCES JESD22-A114-B APS2-FVD-06-003 ESCC21300 - Datasheet Archive

 

Detailed Specification - ICD 1. Introduction 1.7 Handling Precautions 1.1 Scope This version of the ICD is the version generated

 

CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Detailed Specification - ICD 1. Introduction 1.7 Handling Precautions 1.1 Scope This version of the ICD is the version generated after qualification campaign closure. This specification details the ratings, physical, geometrical, electrical and electro-optical characteristics, test- and inspection-data for the High Accuracy Star Tracker (HAS) Version 2 CMOS Active Pixel image Sensor (CMOS APS). The component is susceptible to damage by electro-static discharge. Therefore, suitable precautions shall be employed for protection during all phases of manufacture, testing, packaging, shipment and any handling. The following guidelines are applicable: Always manipulate the devices in an ESD controlled environment. Always store the devices in a shielded environment that protects against ESD damage (at least a non-ESD generating tray and a metal bag). 1.2 Component Type Variants A summary of the type variants of the basic CMOS image sensor is given in Table 1 on page 8. The complete list of detailed specifications for each type variant is given in Table 3 on page 9 for each type separately. Always wear a wrist strap when handling the devices and use ESD safe gloves. The HAS2 is classified as class 1A (JEDEC classification [AD03]) device for ESD sensitivity. The device described in this document is protected by US patent 6,225,670 and others. All specifications in Table 3 on page 9 are given at 25 ± 3°C, under nominal clocking and bias conditions. Exceptions are noted in the 'remarks' field. 1.8 Storage Information The components must be stored in a dust-free and temperature-, humidity and ESD controlled environment. 1.3 Maximum Rating The maximum ratings which shall not be exceeded at any time during use or storage are as scheduled in Table 2 on page 9. Devices must always be stored in special ESD-safe trays such that the glass window is never touched. The trays are closed with EDS-safe rubber bands. 1.4 Physical Dimensions and Geometrical Information The trays are sealed in an ESD-safe conductive foil in clean room conditions. For transport and storage outside a clean room the trays are packed in a second ESD-save bag that is sealed in clean room. The physical dimensions of the assembled component are shown in Figure 2 on page 25. The geometrical information in Figure 4 on page 26 describes the position of the die in the package. 1.5 Pin Assignment Figure 6 on page 27 contains the pin assignment. The figure contains a schematic drawing and a pin list. A detailed functional description of each pin can be found in "Pin List" on page 39. 1.9 Procurement Requirements The HAS2 image sensor can be procured at Cypress Semiconductor or its distributors, using the following references: Soldering is restricted to manual soldering only. No wave or reflow soldering is allowed. For the manual soldering, following restrictions are applicable: Flight sensors: CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS. 1.6 Soldering Instructions Engineering sensors: CYIH1SM1000AA-HHCES CYIH1SM1000AA-HHCES. The HAS sensor is subject to the standard European export regulations for dual use products. Solder 1 pin on each of the 4 sides of the sensor. A Certificate of Conformance will be issued upon request at no additional charge. The CoC will refer to this Detailed Specification. Cool down period of min. 1 minute before soldering another pin on each of the 4 sides. Additional screening tests can be done upon request at additional cost. Repeat soldering of 1 pin on each side, including a 1 minute cool down period. The following data is by default delivered with FM sensors: Temperature calibration data Certificate of Conformance to this detailed specification Visual inspection report · Sensor calibration data Cypress Semiconductor Corporation Document Number: 001-54123 Rev. *A Bad pixel map 198 Champion Court · San Jose, CA 95134-1709 · 408-943-2600 Revised September 18, 2009 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 2. Ordering Information Marketing Part Number Description Package Production CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Space qualified (mono version) 84 pin JLCC In production CYIH1SM1000AA-HHCES CYIH1SM1000AA-HHCES Standard Market (mono version) 84 pin JLCC Nov-09 3. Applicable Documents The following documents form part of this specification and shall be read in conjunction with it: Nr. Reference Title AD01 ESCC Generic Specification 9020 Charge Coupled Devices, Silicon, Photosensitive 2 Draft F Issue Date AD02 Cypress 001-06225[1] Electro-optical test methods for CMOS image sensors E October, 2008 AD03 JESD22-A114-B JESD22-A114-B Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) B June, 2000 AD04 APS2-FVD-06-003 APS2-FVD-06-003 Process Identification Document for HAS2 2 February, 2008 AD05 Cypress 001-49283 Visual Inspection for FM devices 1 January, 2008 AD06 Cypress 001-49280 HAS2 FM Screening 2 June, 2009 4. Acronyms Used For the purpose of this specification, the terms, definitions, abbreviations, symbols, and units specified in ESCC basic Specification 21300 shall apply. In addition, the following table contains terms that are specific to CMOS image sensors and are not listed in ESCC21300 ESCC21300 Abbreviation Description ADC Analog to Digital Convertor APS Active Pixel Sensor CDS Correlated Double Sampling DNL Differential Non Linearity DR Destructive Readout DSNU Dark Signal Non Uniformity EPPL European Preferred Parts List ESD Electro-Static Discharge FPN Fixed Pattern Noise HAS High Accuracy Startracker INL Integral Non Linearity MTF Modulated Transfer Function NDR Non Destructive Readout PRNU Pixel Response Non Uniformity TBC To be Confirmed TBD To be Defined RGA Residual Gas Analysis Note 1. This specification will be superseded by the ESCC basic specification 25000 which is currently under development. The current reference is an internal Cypress procedure which is a confidential document. Document Number: 001-54123 Rev. *A Page 2 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS The following formulas are applicable to convert % Vsat and mV/s into e- and e-/s: FPN [e-] = FPN [%Vsat ] *Vsat conversion _ gain Dark _ signal[e - / s ] = Dark _ signal[V / s ] conversion _ gain DSNU [%Vsat ] *Vsat DSNU [e-] = conversion _ gain Other definitions: Ana log Range ADC Re solution Conversion Gain ADC Quantization Noise = ADC Re solution Conversion gain for HAS: 14.8 µV/e- Definition for Local measurements: 32 x 32 pixels Definition for Global measurements: Full pixel array 5. Detailed Information tions and the tolerances as indicated in Figure 2 on page 25 and Figure 3 on page 26. 5.2.3 Weight The maximum weight of the components specified herein shall be as specified in Table 3 on page 9 - Mechanical Specifications, item 2. 5.3 Materials and Finishes The materials and finishes shall be as specified herein. Where a definite material is not specified, a material which will enable the components specified herein to meet the performance requirements of this specification shall be used. 5.3.1 Case The case shall be hermetically sealed and have a ceramic body and a glass window. Type JLCC-84 JLCC-84 Material Black Alumina BA-914 BA-914 Thermal expansion coefficient 7.6 x 10-6 /K Hermeticity < 5·10-7 atms. cm3/s Thermal resistance (Junction to case) 3.633 °C/W 5.3.2 Lead material and finish 5.1 Deviations from Generic Specification Lead material KOVAR Lot acceptance and screening are based on ESCC 9020 issue 2 draft F. section 5.9 on page 5 of this specification describes the lot acceptance and screening. 1e Finish Nickel, min 2 m 5.2 Mechanical Requirements 5.2.1 Dimension Check 2nd Finish Gold, min 1.5 m 5.3.3 Window The window material is a BK7G18 BK7G18 glass lid with anti-reflective coating applied on both sides. The dimensions of the components specified herein shall be checked. They shall comply with the specifications and the tolerances as indicated in Figure 2 on page 25. The optical quality of the glass shall have the following specification: 5.2.2 Geometrical Characteristics The anti reflective coating shall have a reflection coefficient < 1.3% absolute and < 0.8% on average, over a bandwidth from 440 nm to 1100 nm. The geometrical characteristics of the components specified herein shall be checked. They shall comply with the specifica- Document Number: 001-54123 Rev. *A See Table 3 on page 9 - glass window specification Page 3 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 5.4 Marking 5.4.1 General The marking Shall consist of a lead identification and traceability information. 5.4.2 Lead Identification An index to pin 1 shall be located on the top of the package in the position defined in Figure 2 on page 25. The pin numbering is counter clock-wise, when looking at the top-side of the component. 5.4.3 Traceability Information Each component shall be marked such that complete traceability can be maintained. The component shall bear a number that is constituted as follows: Indication of type. To be replaced by detail specification number when this is allocated. HAS2 - FM Type variant Serial number 000001 Production date (YYMMDD) 061006 5.5 Electrical and Electro-optical Measurements 5.6 Burn-in Test 5.5.1 Electrical and Electro-optical Measurements at Reference Temperature 5.6.1 Parameter Drift Values The parameters to be measured to verify the electrical and electro-optical specifications are scheduled in Table 4 on page 14 and Table 13 on page 24. Unless otherwise specified, the measurements shall be performed at a environmental temperature of 22±3°C. For all measurements the nominal power supply, bias and clocking conditions apply. The nominal power supply and bias conditions are given in Table 14 on page 24, the timing diagrams in Figure 35 on page 51 and Figure 37 on page 53. Remark: The given bias and power supply settings imply that the devices are measured in "soft- reset" condition. 5.5.2 Electrical and Electro-optical measurements at High and Low Temperature The parameters to be measured to verify the electrical and electro-optical specifications are scheduled in Table 5 on page 15 and Table 6 on page 16. Unless otherwise specified, the measurements shall be performed at -40 (-5 +0) °C and at +85 (+5 -0) °C. 5.5.3 Circuits for Electrical and Electro-optical Measurements Circuits for performing the electro-optical tests in Table 4 on page 14 and Table 13 on page 24 are shown in Figure 48 on page 63 to Figure 51 on page 63. Document Number: 001-54123 Rev. *A The parameter drift values for power burn-in are specified in Table 7 on page 18 of this specification. Unless otherwise specified the measurements shall be conducted at a environmental temperature of 22±3°C and under nominal power supply, bias and timing conditions. The parameter drift values shall not be exceeded. In addition to these drift value requirements, also the limit values of any parameter - as indicated in Table 4 on page 14 - shall not be exceeded. Conditions for high temperature reverse bias burn-in Not Applicable 5.6.2 Conditions for Power Burn-in The conditions for power burn-in shall be as specified in Table 10 on page 21 of this specification 5.6.3 Electrical Circuits for High Temperature Reverse Bias Burn-in Not Applicable 5.6.4 Electrical Circuits for Power Burn-in Circuits to perform the power burn-in test are shown in Figure 48 on page 63 and next ones of this specification. Page 4 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 5.7 Environmental and Endurance Tests 5.8 Total Dose Radiation Test 5.7.1 Electrical and Electro-optical Measurements on Completion of Environmental Test 5.8.1 Application The parameters to be measured on completion of environmental tests are scheduled in Table 11 on page 21. Unless otherwise stated, the measurements shall be performed at a environmental temperature of 22±3°C. Measurements of dark current must be performed at 22±1°C and the actual environmental temperature must be reported with the test results. 5.7.2 Electrical and Electro-optical Measurements At Intermediate Point During Endurance Test The total dose radiation test shall be performed in accordance with the requirements of ESCC Basic specification 22900. 5.8.2 Parameter Drift Values The allowable parameter drift values after total dose irradiation are listed in Table 8 on page 19. The parameters shown are valid after a total dose of 42KRad and 168h/100°C annealing. 5.8.3 Bias conditions The parameters to be measured at intermediate points during endurance test of environmental tests are scheduled in Table 11 on page 21. Unless otherwise stated, the measurements shall be performed at an environmental temperature of 22±3°C 5.7.3 Electrical and electro-optical measurements on Completion of Endurance Test The parameters to be measured on completion of endurance tests are scheduled in Table 11 on page 21. Unless otherwise stated, the measurements shall be performed at a environmental temperature of 22±3°C Continuous bias shall be applied during irradiation testing as shown in Figure 48 on page 63 and next ones of this specification. 5.8.4 Electrical and Electro-optical Measurements The parameters to be measured, prior to, during and on completion of the irradiation are listed in Table 13 on page 24 of this specification. Only devices that meet the specification in Table 4 on page 14 of this specification shall be included in the test samples. 5.9 Lot Acceptance and Screening The conditions for operating life tests shall be as specified in Table 10 on page 21 of this specification. This paragraph describes the Lot Acceptance Testing (LAT) and screening on the HAS FM devices. All tests on device level have to be performed on screened devices (see Table 5.9.6 on page 7). 5.7.5 Electrical Circuits for Operating Life Test 5.9.1 Wafer Lot Acceptance Circuits for performing the operating life test are shown in Figure 48 on page 63 and next ones of this specification. This is the acceptance of the silicon wafer lot. This has to be done on every wafer lot that will be used for the assembly of flight models. 5.7.4 Conditions for Operating Life Test 5.7.6 Conditions for High Temperature Storage Test The temperature to be applied shall be the maximum storage temperature specified in Table 2 on page 9 of this specification. Test Test method Number of devices Test condition Test location Wafer processing data review PID NA NA CY SEM ESCC 21400 4 naked dies NA Test house Total dose test ESCC 22900 3 devices 42 krad : 1krad/h ESTEC by CY Endurance test MIL-STD-883 MIL-STD-883 Method 1005 6 devices 2000h at +125 C Test House Before and after total dose test and endurance test: 5.9.2 Glass Lot Acceptance Electrical measurements before and after at high, low and room temperature. Conform Table 4 on page 14 and Table 5 on page 15,Table 6 on page 16 of this specification. Transmission and reflectance curves that are delievered with each lot shall be compared with the specifications in Table , "Glass Lid Specification," on page 10 Visual inspection before and after Detailed electro optical measurements before and after 3 glass lid shall be chosen randomly from the lot and will be measured in detail. All obtained results will be compared with Figure 5 on page 27. Document Number: 001-54123 Rev. *A Page 5 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 5.9.3 Package lot acceptance 5 packages shall be chosen randomly from the lot and will be measured in detail. All obtained results will be compared with Figure 2 on page 25. A solderability test is covered in the assembly lot acceptance tests (Table 5.9.4). 5.9.4 Assembly Lot Acceptance Test Test method Number of devices Test condition Special assembly house in process control Test location Assembly House Bond strength test MIL-STD-883 MIL-STD-883 method 2011 2 Assembly House Geometrical data review Review All Solder ability MIL-STD883 MIL-STD883, method 2003 Terminal strength MIL-STD 883, method 2004 Marking permanence D Assembly House CY D Test House 3 ESCC 24800 Geometrical measurements PID Temperature cycling MIL-STD 883, method 1010 All JEDEC Std. Method A101-B A101-B Test House 240h at 85°C/85% 5 Moisture resistance CY Condition B 50 cycles -55°C/+125°C Test House DPA: Die shear test MIL-STD-883 MIL-STD-883 method 2019 Bond pull test MIL-STD-883 MIL-STD-883 method 2011 N/A 4 Test House All wires Test House Before and after the following tests are done: Electrical measurements conform Table 4 on page 14 of this specification Detailed visual inspection Fine leak test + Gross leak test Fine- and gross-leak tests shall be performed using the following methods: Fine Leak test: MIL-STD-883 MIL-STD-883, Test Method 1014, Condition A Gross Leak test: MIL-STD-883 MIL-STD-883, Test Method 1014, Condition C The required leak rate for fine leak testing is 5·10-7 atms. cm3/s Document Number: 001-54123 Rev. *A Page 6 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 5.9.5 Periodic Testing Test Test method Number of devices Test condition Test location Mechanical Shock MIL-STD 883, method 2002 2 B - 5 shocks, 1500g ­ 0,5ms ­ ½ sine, 6 axes Test House Mechanical Vibration MIL-STD 883, method 2007 2 A - 4 cycles, 20g 80 to 2000 Hz, 0,06 inch 20 to 80 Hz, 3 axes Test House N/A Test House 2 All wires Test House DPA: Die shear test Bond pull test MIL-STD-883 MIL-STD-883 method 2019 MIL-STD-883 MIL-STD-883 method 2011 Periodic testing is required every 2 years. Before and after the following tests are done: Electrical measurements conform Table 4 on page 14. Detailed visual inspection Fine leak test + Gross leak test Fine- and gross-leak tests shall be performed using the following methods: Fine Leak test: MIL-STD-883 MIL-STD-883, Test Method 1014, Condition A Gross Leak test: MIL-STD-883 MIL-STD-883, Test Method 1014, Condition C The required leak rate for fine leak testing is 5·10 7 atms. cm3/s 5.9.6 Screening Nr. 1 Test Test method Number of devices Test condition HT +85°C LT -40°C RT +25°C Test location HCRT Electrical measurements 001-53958 All CY 2 Visual inspection 001-49283 + ICD All CY 3 Die placement measurements Cypress internal proc. All CY 4 XRAY ESCC 20900 All 5 Stabilization bake MIL-STD-883 MIL-STD-883 method 1008 All 48h at 125°C Test House 6 Fine leak test MIL-STD-883 MIL-STD-883 method 1014 All A Test House 7 Gross leak test MIL-STD-883 MIL-STD-883 method 1014 All C Test House 8 Temperature cycling MIL-STD-883 MIL-STD-883 method 1010 All B - 10 cycles -55°C +125°C Test House Test House 9 Biased Burn-in ICD All 240h at +125°C. CY 10 Mobile Particle Detection MIL-STD-883 MIL-STD-883 method 2020 All A Test House 11 Fine leak test MIL-STD-883 MIL-STD-883 method 1014 All A Test House 12 Gross leak test MIL-STD-883 MIL-STD-883 method 1014 All C Test House 13 HCRT Electrical measurements 001-53958 All HT +85°C LT -40°C RT +25°C CY 14 Final Visual Inspection 001-49283 + ICD All Document Number: 001-54123 Rev. *A CY Page 7 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 6. Tables and Figures 6.1 Specification Tables Table 1. Type Variant Summary HAS2 Type Variants Engineering samples (HHCES) Flight model samples (HHCS) Optical Quality (See "Optical quality - Definitions" on page 70.) Dead pixels 100 20 Bright pixels in FPN image 50 20 Bad pixels in PRNU image 150 50 Bad columns 5 0 Bad rows 5 0 2 adjacent bright pixels 25 2 4 or more adjacent bright pixels 10 0 DSNU defects @ 22 dec BOL 1200 1000 DSNU defects @ 22 dec EOL 1500 1250 N/A N/A Bright pixel clusters: Particle Contamination Fixed particles outside focal plane Mobile particles > 20um 0 0 Fixed particles on focal plane > 20um 0 0 Mobile particles > 10um and < 20um 20 10 Particles < 10um N/A N/A Wafer lot acceptance (section 5.9.1 on page 5) NO YES Glass lot acceptance (section 5.9.2 on page 5) NO YES Fixed particles on focal plane > 10um and < 20um Assembly lot acceptance (Table 5.9.4 on page 6) NO YES Periodic testing (Table 5.9.5 on page 7) NO YES Screening (Table 5.9.6 on page 7) NO YES Calibration data Optional YES Visual Inspection + particle mapping Optional YES Document Number: 001-54123 Rev. *A Page 8 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Table 2. Maximum Ratings No Min Typ Max Unit 1 Any supply voltage except VDD_RES Characteristic -0.5 3.3 +7.0 V 2 Supply voltage at VDD_RES -0.5 3.3 +5.0 V 3 Voltage on any input terminal -0.5 3.3 Vdd + 0.5 V 4 Soldering temperature NA NA 260 °C 5 Operating temperature -40 NA +85 °C 6 Storage temperature -55 NA +125 Remarks °C 3.3V for normal operation; up to 5V for increased full well capacity. Hand soldering only; See section 1.6 on page 1 for soldering instructions Table 3. Detailed Specification All Type Variants General Characteristics No Min Typ Max Unit 1 Image sensor format Characteristic N/A 1024x 1024 N/A pixels Remarks 2 Pixel size N/A 18 N/A m 3 ADC resolution N/A 12 N/A bit 10 bit accuracy at 5 Msamples / sec Min Typ Max Unit Remarks N/A N/A 20 um See "Type Variant Summary" on page 8 Min Typ Max Unit NA 7.4 NA m Silicon Particle Contamination Specification No 1 Characteristic Optical quality: Particle max size Mechanical Specifications No Characteristic Remarks 1a Flatness of image area 1b Flatness of glass lid NA 90 150 m 2 Mass 7.7 7.85 8.0 g 3 Total thickness 3.2 3.3 3.4 mm Package + epoxy + glass lid 4a Die position, X offset NA NA 0.1 mm Die in center of cavity Die in center of cavity 4b Die position, Y offset NA NA 0.1 mm 5 Die position, parallelism vs window Die position, parallelism vs backside -0.1 0.1 0 0 0.1 0.1 Die position, Y tilt -0.1 0 0.1 ° 7 Die position, X tilt -0.1 0 0.1 ° 8 Die ­ window distance 0.25 0.3 0.35 Towards ceramic package mm 6 Peak-to-peak at 25 ± 3 °C Specified by the foundry over an entire 8" wafer mm Document Number: 001-54123 Rev. *A Page 9 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Glass Lid Specification No Characteristic Min Typ Max Unit 26.7 x 26.7 26.8 x 26.8 26.9 x 26.9 mm 1a XY size 1b Thickness 1.4 1.5 1.6 mm 2a Spectral range for optical coating of window 440 NA 1100 nm 2b Reflection coefficient for window NA T0 T -T0 TDCNU ,d 2 ,L + aDCNU TID 2 T -T0 TDCNU , d 2, H for T < T0 for T > T0 with DC the dark current in e/s DC0 the dark current at 30 °C and 0 krad = 550 e/s TID the total ionizing dose (in krad(Si) T the temperature (in °C) aDC the slope of the curve at 30 °C = 480 e/s/krad(Si) TDC,d1,L = 6.6 °C and TDC,d2,L = 8 °C for T < T0 TDC,d1,H = 5 °C and TDC,d2,H = 6.5 °C for T > T0 DCNU0 the dark current non-uniformity at 30 °C and 0 krad = 400 e/s aDCNU the slope of the curve at 30 °C = 45 e/s/krad(Si) TDCNU,d1,L = 10.5 °C and TDCNU,d2,L = 10.5 °C for T < T0 TDCNU,d1,H = 8.5 °C and TDCNU,d2,H = 8.5 °C for T > T0 T0 = 30 °C Document Number: 001-54123 Rev. *A Page 34 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS DCNU Distributions Figure 17 and Figure 18 show the distributions of the dark current in mV/s and e/s respectively for a number of devices and the average distribution. Figure 17. Dark Current Distribution (in mV/s) at 25 ºC Ambient Temperature 10000 ext dev 1 ext dev 6 ext dev 10 int dev 1 1000 int dev 6 int dev 10 100 Relative frequency average 10 1 0.1 0.01 0.001 0 20 40 60 80 100 120 140 160 180 200 Dark current [mV/s] Figure 18. Dark Current Distribution (in e/s) at 25 ºC Ambient Temperature 10000 ext dev 1 ext dev 6 ext dev 10 int dev 1 1000 int dev 6 int dev 10 100 Relative frequency average 10 1 0.1 0.01 0.001 0 2000 4000 6000 8000 10000 12000 Dark current [e/s] Document Number: 001-54123 Rev. *A Page 35 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Figure 19 and Figure 20 show the cumulative distributions of the dark current in mV/s and e/s respectively for a number of devices and the average cumulative distribution. Figure 19. Cumulative Dark Current Distribution (in mV/s) at 25 ºC Ambient Temperature 100 ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 Cumulative frequency 10 average 1 0.1 0.01 0.001 0.0001 0 20 40 60 80 100 120 140 160 180 200 Dark current [mV/s] Figure 20. Cumulative Dark Current Distribution (in e/s) at 25 ºC Ambient Temperature 100 ext dev 1 ext dev 6 ext dev 10 int dev 1 Cumulative frequency 10 int dev 6 int dev 10 average 1 0.1 0.01 0.001 0.0001 0 2000 4000 6000 8000 10000 12000 Dark current [e/s] Document Number: 001-54123 Rev. *A Page 36 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Figure 21 shows the percentage of pixels versus their normalized dark current for the measurement and for a Gaussian distribution with the same average value and standard deviation. In the measured distribution, about 1.1-1.2 % of the pixels exhibit a dark current that exceeds the 3 limit that is typically used to exclude pixels from the measurements (about 10 times larger than for Gaussian distribution). Figure 21. Comparison between Measured Distribution and Gaussian Distribution 100 measurement gaussian distribution Percentage of pixels [%] 10 1 0.1 0.01 0.001 0.0001 0 1 2 3 4 5 6 7 8 9 10 (dark current - average dark current) / (st. dev. dark current) Figure 22 shows the DSNU distributions during TID irradiation Figure 22. DSNU Distributions during TID Irradiation DSNU distribution during Total Dose Irra diation and afte r annea ling 10000 Pre Rad 4Krad 14Krad 20Krad 41Krad 168h HT Annealing 3mnth RT Annealing 1000 Num ber of pix els Biased Conditions 100 10 1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 A DU value [0 - 2^12 ] Document Number: 001-54123 Rev. *A Page 37 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 6.3.5 Temperature Sensor Figure 23. Temperature Sensor Voltage Sensitivity: The solid line indicates a linear fit with 1.38 V as output voltage at 30 ºC and a slope of -4.64 mV/ºC 1 .4 5 measurement points fitted curve deviation 1.38 4 2 1.32 1 1 .3 0 1.28 -1 1.26 -2 1.24 -3 1.22 -4 1 .2 Deviation from fitted curve [mV] 3 1.34 Output voltage [V] 1.36 -5 30 35 40 45 50 55 60 65 70 75 Temperature [C] 6.3.6 Pixel-to-Pixel Cross Talk Figure 24. Cross talk with central pixel uniformly illuminated with 100 %. Estimation from Knife-edge measurements 0.0 0.2 1.3 0.2 0.0 Document Number: 001-54123 Rev. *A 0.2 1.3 9.8 1.3 0.2 1.3 9.8 49.0 9.8 1.3 0.2 1.3 9.8 1.3 0.2 0.0 0.2 1.3 0.2 0.0 Page 38 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 7. Pin Description 7.1 Pin Type Information The following conventions are used in the pin list. Pin Types AI Analogue Input AO Analogue Output AB Analogue Bias DI Digital Input DO Digital Output VDD Supply Voltage GND Supply Ground 7.2 Power Supply Considerations It is suggested to use one regulator for all digital supply pins together, one regulator for the sensor core analogue supplies together, and one regulator for the ADC analogue supply (if used). Analogue ground returns must be of very low impedance, as short-term peaks of 200mA can be encountered. The ADC can be disabled by connecting all of its power and ground pins to system ground, leaving all other pins open. 7.3 Pin List Doubled-up pins have the same pin name, but are indicated with (*). These pins are at the same potential on the chip. Pin No. Name Type Purpose Power Supply and Ground Connections 10 VDD_DIG (1) VDD 33 VDD_DIG (2) VDD 11 GND_DIG (1) GND 32 GND_DIG (2) GND 8 VDD_ANA (1) VDD Logic power, 3.3V 35 VDD_ANA (2) GND_ANA (1) GND 34 GND_ANA (2) GND 55 GND_ANA (3) GND 73 GND_ANA (4) GND 58 VDD_PIX (1) VDD Analogue power, 3.3V VDD 9 Logic ground 70 VDD_PIX (2) VDD_RES VDD Pixel array power, 3.3V VDD 74 Analogue ground Reset power, 3.3V, optionally up to 5V for increased full well Sensor Biasing 75 GND_AB AB Antiblooming ground, connect to system ground or to a low-impedant 1V source for enhanced anti-blooming 52 NBIAS_DEC AB Connect with 200k to VDD_ANA, decouple with 100nF to GND_ANA 51 NBIAS_PGA AB Connect with 200k to VDD_ANA, decouple with 100nF to GND_ANA Document Number: 001-54123 Rev. *A Page 39 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Pin No. Name Type Purpose 50 NBIAS_UNI40 UNI40 AB Connect with 75k to VDD_ANA, decouple with 100nF to GND_ANA 49 NBIAS_LOAD AB Connect to GND_ANA 48 NBIAS_PRECHARGE AB Connect with 110k to VDD_ANA, decouple with 100nF to GND_ANA 47 NBIAS_PREBUF AB Connect with 200k to VDD_ANA, decouple with 100nF to GND_ANA 46 NBIAS_COLUMN AB Connect with 110k to VDD_ANA, decouple with 100nF to GND_ANA Analog Signal Input and Outputs 31 SIGNAL_OUT AO Output of PGA, range ## . ## V, straight polarity i.e. a low output voltage corresponds to a dark pixel reading. 60 A_IN1 AI Input to PGA input multiplexer. 59 A_IN2 AI Input to PGA input multiplexer. 57 A_IN3 AI Input to PGA input multiplexer. 56 A_IN4 AI Input to PGA input multiplexer. 54 PHOTODIODE AO Reference photodiode Logic Control Inputs and Status Outputs 71 A9 DI 69 A8 DI 68 A7 DI 67 A6 DI 66 A5 DI 65 A4 DI 64 A3 DI 63 A2 Parallel sensor programming interface shared address/data bus, MSB DI 62 A1 DI 61 A0 DI Parallel sensor programming interface shared address/data bus, LSB 72 LD_Y DI Load strobe: copy A[9.0] into Y1 start register 76 LD_X DI Load strobe: copy A[9.0] into X1 start register 77 LD_REG DI Load strobe: copy A[7.0] into parameter register indicated by A[9.8] 78 RES_REGn DI Asynchronous reset for internal registers 82 SYNC_YRD DI Initialise Y read shift register (YRD) to position indicated by Y1 start register 84 SYNC_YRST DI Initialise Y reset shift register (YRST) to position indicated by Y1 start register 36 SYNC_XRD DI Initialise X read shift register (XRD) to position indicated by X1 start register 83 CLK_YRD DI Advance shift register YRD one position 1 CLK_YRST DI Advance shift register YRST one position Document Number: 001-54123 Rev. *A Page 40 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Pin No. Name Type Purpose 25 CLK_X DI Advance shift register XRD; note: two clock cycles needed for one pixel output 53 EOS DO End Of Scan monitor output for YRD,YRST,XRD shift registers, selected through an internal register 2 YRST_YRDn DI Enable YRD to address the pixel array when `0'; Enable YRST to address the pixel array when `1' 4 RESET DI Reset the line pointed to by YRST (YRST_YRDn='1') or pointed to by YRD (YRST_YRDn='0') 37 BLANK DI Assert when in line blanking / non-readout phase 3 SEL DI Select for readout the line pointed to by YRST (YRST_YRDn='1') or YRD (YRST_YRDn='0') 5 PRECHARGE DI Precharge column bus 6 R DI Sample the selected line's levels onto the column amplifier reset level bus 7 S DI Sample the selected line's levels onto the column amplifier signal level bus 38 CAL DI Calibrate PGA ADC 30 IN_ADC AI Analogue input to ADC 27 CLK_ADC DI ADC conversion clock, pixel rate, latency is 6.5 cycles ADC data output, MSB 23 DATA_11 DO 22 DATA_10 DO 21 DATA_9 DO 20 DATA_8 DO 19 DATA_7 DO 18 DATA_6 DO 17 DATA_5 DO 16 DATA_4 DO 15 DATA_3 DO 14 DATA_2 DO 13 DATA_1 DO 12 DATA_0 DO ADC data output, LSB 43 SPI_DIN DI Serial calibration interface data in 42 SPI_LD DI Serial calibration interface load strobe 41 SPI_CLK DI Serial calibration interface bit clock 44 ADC_NBIAS AB Connect with 60 kOhm resistor to ADC_PBIAS, decouple with 100nF to ground 45 ADC_PBIAS AB Connect with 60 kOhm resistor to ADC_NBIAS, decouple with 100nF to VDD_ADC_ANA 39 VLOW_ADC AI ADC low threshold reference voltage, connect with 90 Ohm to GND and 130 Ohm to VHIGH_ADC, decouple with 100nF to ground 40 VHIGH_ADC AI ADC high threshold reference voltage, connect with 130 Ohm to VDD_ANA_ADC, decouple with 100nF to ground 81 REF_COMP_LOW AO Decouple with 100nF to ground 80 REF_MID AO Decouple with 100nF to ground Document Number: 001-54123 Rev. *A Page 41 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Pin No. Name Type AO Purpose 79 REF_COMP_HIGH 29 VDD_ADC_ANA VDD Decouple with 100nF to ground 28 GND_ADC_ANA GND Analogue ground 24 VDD_ADC_DIG VDD Digital supply, 3.3V 26 GND_ADC_DIG GND Digital ground Analogue supply, 3.3V 7.4 Electrical Characteristics 7.4.1 Multiplexer Inputs Pin nr. Name Imput impedance Settling Time 60 A_IN1 Capacitive 10pF 100ns 59 A_IN2 Capacitive 10pF 100ns 57 A_IN3 Capacitive 10pF 100ns 56 A_IN4 Capacitive 10pF 100ns 7.4.2 Digital I/O Figure 25. Simulation results Digital "0" and Digital "1" DC simulation of different input buffers of HAS2 incertain if input is seen a s a high or lo w signa l 3.50E+00 3.00E+00 Output of buffert 2.50E+00 Lo w signa l L ow sign al, bu t le ackage curre nt thro ugh bu ffer 2.00E+00 1.50E+00 High sign al, bu t le acka ge curre nt thro ugh buffer 1.00E+00 5.00E-01 00E-01 0.00E+00 0.00E+00 High signal 5.00E-01 00E-01 1.00E+00 1.50E+00 2.00E+00 2.50E+00 3.00E+00 3.50E+00 Digital input Document Number: 001-54123 Rev. *A Page 42 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 7.5 Package Pin Assignment The HAS sensor is packaged in a 84 pins JLCC84 JLCC84 package with large cavity. The figure below shows the pin configuration. Figure 26. Pin Configuration A0 A_IN1 A_IN2 VDD_PIX A_IN3 A_IN4 GND_ANA PHOTO_DIODE A2 A1 (0,1023) x- direction ADC (1023,0) Output amplifier CLK_X GND_ADC_DIG CLK_ADC GND_ADC_ANA VDD_ADC_ANA IN_ADC SIGNAL_OUT GND_DIG Drivers Image Core 1024x1024 DATA VDD_ADC_DIG (0,0) (1023,1023) DATA DATA y-direction GND_AB LD_X LD_REG RES_REGn REF_COMP_HIGH REF_MID REF_COMP_LOW SYNC_YRD CLK_YRD SYNC_YRST CLK_YRST YRST_YRDn SEL RESET PRECHARGE R S VDD_ANA GND_ANA VDD_DIG GND_DIG DATA DATA DATA DATA DATA DATA DATA DATA DATA 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 A4 A3 VDD_RES GND_ANA LD_Y A9 VDD_PIX A8 A7 A6 A5 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 EOS NBIAS_DEC NBIAS_PGA NBIAS_UNI40 UNI40 NBIAS_LOAD NBIAS_PRECHARGE NBIAS_PREBUF NBIAS_COLUMN ADC_PBIAS ADC_NBIAS SPI_DIN SPI_LD SPI_CLK VHIGH_ADC VLOW_ADC CAL BLANK SYNC_XRD VDD_ANA GND_ANA VDD_DIG 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Document Number: 001-54123 Rev. *A Page 43 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 8. User Manual 8.1 Image Sensor Architecture Sensor Block Diagram Document Number: 001-54123 Rev. *A Page 44 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 8.1.1 Pixel Architecture A square array contains 1024x1024 three-transistor linearly-integrating pixels of each 18 x 18 m. Each pixel has a connection for a reset line, for power, an output select line, and eventually the pixel's output signal Figure 27. Three-transistor Pixe: Transistor-level Diagram (left), and Functional Equivalent (right) There are three transistors in a pixel. The first one acts as a switch between the power supply and the photodiode. The photodiode is equivalent to a capacitor with a light-controlled current source. The second transistor is a source follower amplifier, buffering the voltage at the photodiode/capacitor cathode for connection to the outside world. The third transistor again is a switch, connecting the output of the buffer amplifier to an output signal bus. Activating the reset line drains the charges present on the pixel's embedded photodiode capacitor, corresponding to a black, dark, pre-exposure state, or high voltage. As all pixels on a row (line) share their reset control lines, the pixels in a row can only be reset together. With both reset and select lines disabled the pixel amasses photo charges on its capacitor, charges generated in the photo- diode by impinging photons. During this integration the voltage on the photodiode cathode decreases. When the select line is asserted the voltage on the capacitor is connected to the pixel output through the source follower buffer transistor. All pixels in a line have their select lines tied together: upon selection a whole line of pixel output signals is driven onto the 1024 column buses that lead into the column amplifiers for further processing and complete or partial sequential readout to the ADC. All pixels on a line have their reset lines tied together: the reset mechanism works on all pixels in a line simultaneously, no individual or addressed pixel reset (IPR) is possible. Figure 28. Signal Lifetime in a Three-transistor Pixel: Reset to black level (high voltage), Photo Charge Integration (dropping voltage), voltage readout Document Number: 001-54123 Rev. *A Page 45 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 8.1.2 Array Coordinate System Figure 29. Front View of Sensor Die: Package pin 1 is on the left side. The focal plane origin is in the bottom-left corner. Lines (Y) are scanned down to top, pixels (X) left to right 8.1.3 Line Addressing The sensor operates line wise: a line of pixels can be selected and reset, and a line of pixels can be selected for readout into the column amplifier structures. There is no frame reset operation, there is no frame transfer. Image acquisition is done by sequencing over all lines of interest and applying the required reset and/or readout control to each line selected. The sensor array contains two vertical shift registers for line addressing. These registers are one-hot, i.e. they contain a pattern like "00001000000", at each time pointing to one line of pixels. Figure 30. Line Addressing Structures: YRD and YRST one-hot shift register pointers and Y1 programmable start-of-scan register Document Number: 001-54123 Rev. *A Page 46 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS In Double Sampling / Destructive readout, one of these registers is typically dedicated to addressing the lines to read, and the other is used for addressing the lines to reset as part of the electronic shutter operation. In Correlated Double Sampling / Non-Destructive Readout, it is the user's choice whether one or both shift registers will be used. Both Y shift registers can be initialized to a position indicated by an on-chip address register. This address register is written by the user through the parallel sensor programming interface. With this programmable initial position windowed readout (region-of-interest) is possible. 8.1.6 Input Signal Multiplexer An analogue signal multiplexer with six inputs connects a number of sources to the output buffer. One input always is connected to the pixel-serial output of the pixel array. Four inputs are connected to analogue input pins and are intended for monitoring voltages in the neighborhood of the sensor. The last multiplexer input is connected to the on-chip temperature sensor. Both registers can be advanced one position at a time under user control. The multiplexer is controlled by an internal register, written through the parallel sensor programming interface. 8.1.4 Pixel Addressing 8.1.7 Programmable Gain Amplifier (PGA) Pixels are read from left to right, generating a pixel-sequential output signal for each line. The pixel addressing is similar to the line addressing. A voltage amplifier conditions the output signal of the multiplexer for conversion by the ADC. Signal gain and offset can be controlled by a register written through the parallel sensor programming interface. Close to the column amplifiers resides a horizontal shift register for pixel/column addressing. This register is one-hot, i.e. it contains a pattern like "00001000000", at a time pointing to exactly one pixel and one column amplifier. Line acquisition is done by sequencing over all pixels of interest and applying each time the required pixel readout and ADC control signals. The X shift register can be initialized to a position indicated by an on-chip address register. This address register is written by the user through the parallel sensor programming interface. With this programmable initial position windowed readout (region-of-interest) is possible. The X register can be advanced one position under user control. This requires a pixel clock signal at twice the frequency of the desired pixel rate. 8.1.5 Column Amplifiers At the bottom of each column of pixels sits one column amplifier, for sampling the addressed pixel's signal and reset levels. These signals are then locally hold until that particular pixel is sent to the output channel, in this case PGA, multiplexer, buffer, and ADC. The combination of column amplifiers and PGA can perform Double Sampling: in this case a pixel's signal level is read into the structures, then the pixel is reset, then the reset level is read into the structures and subtracted from the previously-stored signal level, cancelling fixed pattern noise. In Correlated Double Sampling mode the column amplifiers are used in bypass mode, and the raw signal level (which can be either a dark reset level or a post-illumination signal level) is sent to the output amplifier, and then to the output for storage and correlated subtraction off-chip. This cancels fixed pattern noise as well as temporal KTC noise. Document Number: 001-54123 Rev. *A When connected to the pixel array, the PGA also subtracts pixel black level from pixel signal level when in DS/DR mode. 8.1.8 Parallel Sensor Programming Interface The sensor is controlled via a number of on-chip settings registers for X and Y addressing, PGA gain and offset, one-off calibration of the column amplifiers, . These registers are written by the user through a parallel bus. 8.1.9 12-bit Analog to Digital Convertor (ADC) The on-chip ADC is a 12 bit pipelined convertor. It has a latency of 6.5 pixel clock cycles, i.e. it samples the input on a rising clock edge, and outputs the converted signal 6 pixel clock periods afterwards on the falling edge. The ADC contains its own SPI serial interface for the optional upload of calibration settings, enhancing its performance. The ADC is electrically isolated from the actual sensor core: when unused it can be left non-powered for lower dissipation, and without risk for latch-up. When used, the input voltage range of the ADC is set with a two-node voltage divider connected to pins VLOW_ADC and VHIGH_ADC. The ADC has an accuracy of 10 bit at 5 Mhz operation speed. 8.1.10 Temperature Sensor A PN-junction type temperature sensor is integrated on the chip. The temperature-proportional voltage at its output can be routed to the ADC through one of the six analogue inputs of the multiplexer. The temperature sensor must be calibrated on a device-to-device base. Its nominal response is -4.64 mV/°C . Page 47 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS 8.2 Image Sensor Operation The following s describe the HAS' two readout mechanisms and give the detailed timing and control diagrams to implement these mechanisms. 8.2.1 Double Sampling - Destructive Readout In Double Sampling / Destructive Readout (DS/DR) mode the YRST pointer runs over the frame, top to bottom, each time resetting the line it addresses. Lagging behind this runs the YRD pointer, each time reading out the line it addresses. The distance between the YRD pointer and the YRD pointer is then propor- tional to the exposure time, hence the electronic shutter operation. At line readout the signal levels of the pixels in the addressed line are copied onto the column amplifiers' signal sample nodes. Immediately after this the line of pixels is reset, and the pixels' black levels are copied onto the column amplifiers' reset sample nodes. This is destructive readout. The column amplifiers/PGA then subtract the black levels from the signal levels during sequential pixel out. This is uncorrelated double sampling, eliminating any static pixel-to-pixel offsets of the sensor array. Figure 31. Double Sampling: Pixel signal is read (s), then pixel is reset, then reset level is read (r) 8.2.2 Correlated Double Sampling - Non-Destructive Readout In Correlated Double Sampling/Non-Destructive Readout (CDS/NDR) mode the YRST or YRD pointer quickly runs over the frame, top to bottom, resetting each line it addresses. This leaves the pixel array drained of charges, in black or dark state. Then the YRD or YRST pointer is run over the region of interest of the frame, and of each line addressed the pixels' black levels are read out and passed on to the ADC. The user stores these black levels in an off-chip frame-sized memory. Then the system is held idling during the exposure time. After the exposure time has elapsed, the frame is scanned once more with the YRD or YRST pointer, and each line addressed is read out again. These signal levels are passed on to the ADC and then to the end user. At the same time, the user retrieves the corresponding black levels from the memory and subtracts them from the signal levels. This is correlated double sampling, eliminating static offsets as well as kTC noise Document Number: 001-54123 Rev. *A Page 48 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Figure 32. Correlated Double Sampling: Pixel is reset, reset level is read and stored (r), pixel is exposed, signal level is read (s), difference is output 8.2.3 Possible Exposure Times The range of exposure times attainable by the HAS is entirely dependent on the user control strategy, although two obvious scenarios can be envisaged: In Destructive Readout/Double Sampling, a typical case would be a minimal exposure time equal to the line readout time, and a maximal exposure time equal to the frame time. With 1024x1024 pixels in a frame, 10 frames per second, this amounts to 98s and 100ms. In Non-Destructive Readout/Correlated Double Sampling it is not even possible to pinpoint a typical case, as all depends on the exact reset (R), reset-read (r) and signal-read (s) scheme the user employs. In the specific case of 10MHz pixel rate rate operation, 10 windowed frames per second, and 40 windows of 20x20, each receiving the same exposure time, and the whole FPA reset (R) at the start of the frame, the minimal exposure time would be 7.3ms, the maximal exposure time 90.2ms. Depending on window configuration, shorter and longer times are possible, though. 8.2.4 Timing and Control Sequences Windows or regions-of-interest are defined by their top-left and bottom-right coordinates (X1,Y1)-(X2,Y2). The full frame then corresponds to (0,0)-(1023,1023). Note that (X1,Y1) is to be programmed into the sensor, while (X2,Y2) is not: windowed readout is obtained by pointing the sensor to (X1,Y1), followed by reading out (Y2-Y1+1) lines of (X2-X1+1) pixels. A frame readout sequence consists of a number of line readout sequences. A line readout sequence consists of A line select sequence for the YRD and YRST pointer shift registers, during which a line may be selected for readout and another line may be selected for reset A line blanking sequence during which the line selected for readout copies its pixel signals into the column amplifiers, the column amplifiers are operated, and both lines selected are optionally reset (the line selected for read can be reset as part of the destructive readout/double sampling operation; the other line can be reset as part of the electronic shutter operation). A pixel readout sequence Definitions The HAS is a line-scan imager with 1024 horizontal lines (Y) each of 1024 pixels (X). Pixel coordinates are defined relative to an origin (X=0,Y=0), and projected onto the user's display view: the origin (0,0) is in the top-left corner of the displayed image, lines are scanned top-down, and the pixels in a line are scanned left to right. Document Number: 001-54123 Rev. *A A pixel readout sequence consists of Initialization of the pixel pointer XRD to position X1 A sequencing through the region-of-interest, While the output amplifier and the ADC are activated and pixel values are sequentially selected, connected to the PGA, and converted by the ADC. Page 49 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Figure 33. Line Selection Timing Diagram Above timing diagram is valid for CLK_YRD/SYNC_YRD and for CLK_YRST/SYNC_YRST. Description Min t1 SYNC_Y* setup CLK_Y* high width CLK_Y* period 200 ns t4 Address delay t5 Setup to next blanking Remarks 100 ns t3 Max 50 ns t2 Typ No constraint on duty cycle 30 ns 100 ns Destructive Readout Timing Diagram n this mode the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. Hence, the exposure time tEXP can be expressed as an equivalent number of lines. Table 16. Threads of Operation for Destructive Readout with Double Sampling Comment init YRD - read side Load registers Y1 and X1 with the window start coordinates Initialize YRD with Y1 expose .do nothing read For YRD = Y1 to Y2 loop .select line YRD .operate column amplifiers for DS/DR .read pixels X1 to X2 .advance YRD end loop YRST - reset side Initialise YRST with Y1 For YRST = Y1 to Y1+tEXP loop .select line YRST .reset line YRST .wait for one line time .advance YRST one position end loop .select line YRST .reset line YRST .advance YRST Figure 34. DS/DR Sequence: Exposure is initiated with running YRST over the array, resetting lines. After tEXP YRD sTarts running over the array too, reading and then resetting lines Document Number: 001-54123 Rev. *A Page 50 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Figure 35. Destructive Readout Timing Diagram Description Min Typ 13 ns 25 ns S setup 10 ns 25 ns PRECHARGE width 400 ns t1 BLANK setup t2 t3 t4 t5 30 ns S active when SEL t6 t7 Remarks 50 ns 2 s 11 ns RESET width Max 25 ns 400 ns t8 100 ns t9 100 ns t10 R active when SEL t11 2 s 10 ns 25 ns t12 YRST_YRDn setup 100 ns t13 YRST_YRDn hold 100 ns t14 BLANK hold 22 ns t15 BLANK hold 100 ns When no second RESET t16 CAL delay ref. BLANK 25 ns Once per frame or per line Second RESET is optional 25 ns The CAL signal initiates the programmable gain amplifier to a known 'black' state. This initialization should be done at the start of each frame. Document Number: 001-54123 Rev. *A Page 51 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Non-Destructive Readout Timing Diagram In describing this mode the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. Hence, the exposure time tEXP can be expressed as an equivalent number of lines. (Note however that the user is under no obligation to link tEXP to the line read time: tEXP can be chosen arbitrarily as its timing and nature are only dependent on the external system controlling the HAS). Table 17. Threads of Operation for Non-destructive Readout with Off-chip CDS Comment init YRD - read side YRST - reset side Load registers Y1 and X1 with the window start coordinates initialize YRD with Y1 Initialize YRST with Y1 clear frame .do nothing read black levels for YRD = Y1 to Y2 loop .select line YRD .operate column amplifiers for CDS/NDR, black levels .read pixels X1 to X2 .advance YRD end loop exposure wait for time tEXP read signal levels for YRST = 1 to 1023 loop .select line YRST .reset line YRST .advance YRST one position end loop for YRD = Y1 to Y2 loop .select line YRD .operate column amplifiers for CDS/NDR, signal levels .read pixels X1 to X2 .advance YRD end loop Proper operation can be attained by using just one Y pointer register, YRD or YRST, for all of the frame's phases. The above operation scheme is just an example, using YRST for the frame reset phase. Figure 36. CDS/NDR Sequence: First array is reset completely with YRST. Then black levels are read with YRD. Then, after a time tEXP, all signal levels are read, again with YRD Document Number: 001-54123 Rev. *A Page 52 of 71 [+] Feedback CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS Figure 37. Non-destructive Readout Timing Diagram Description Min Typ 25 ns t1 BLANK setup 13 ns t2 YRST_YRDn s/h 100 ns t3 RESET width BLANK setup 13 ns 25 ns t5 S/R setup 10 ns 25 ns t6 PRECHARGE width 400 ns S/R active when SEL 2.4s 11 ns 25 ns t10 SEL hold 11 ns 25 ns t11 BLANK hold 100 ns t12 CAL delay ref. BLANK 25 ns Remarks 400 ns t4 Max t7 t8 30 ns t9 Optional, only when YRST is used instead of YRD 50 ns once per frame or per