CY8C27143 CY8C27243 CY8C27443 CY8C27543 CY8C27643 CY8C27243-24PVI - Datasheet Archive

 

CY8C27543, CY8C27643 PSoCTM Mixed Signal Array Final Data Sheet August 28, 2003 Cypress MicroSystems 2700 162nd Street SW

 

CY8C27143 CY8C27143, CY8C27243 CY8C27243, CY8C27443 CY8C27443, CY8C27543 CY8C27543, CY8C27643 CY8C27643 PSoCTM Mixed Signal Array Final Data Sheet August 28, 2003 Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: 800.669.0557 FAX: 425.787.4641 http://www.cypress.com Document No. 38-12012 Rev. *C CY8C27xxx Final Data Sheet © Cypress MicroSystems, Inc. 2000-2003. All rights reserved. PSoCTM (Programmable System-on-ChipTM) is a trademark of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems' products in life-support system applications implies that the manufacturer assumes all risk of such use and in doing so, indemnifies Cypress MicroSystems against all charges. 2 Document No. 38-12012 Rev. *C August 28, 2003 Contents SECTION A OVERVIEW 13 Features .13 Getting Started .14 Development Kits .14 Tele-Training .14 Consultants .14 Technical Support .14 Top-Level Architecture .15 Development Tools .16 PSoC Designer Software Subsystems .16 Hardware Tools .17 User Modules and Development Process .17 Ordering Information .19 Organization and Conventions .20 Document Organization .20 Document Conventions .20 1. Pin Information .23 1.1 1.2 2. Pin Summary .23 Pinouts .24 Packaging Information .29 2.1 2.2 Packaging Dimensions.29 Thermal Impedances .33 SECTION B CORE ARCHITECTURE 35 Top-Level Core Architecture .35 Core Register Summary .36 3. CPU Core (M8C) .39 3.1 3.2 3.3 3.4 August 28, 2003 Internal Registers .39 Address Spaces .39 Instruction Set Summary.41 Instruction Format .42 3.4.1 One-Byte Instructions.42 3.4.2 Two-Byte Instructions.42 3.4.3 Three-Byte Instructions .43 Document No. 38-12012 Rev. *C 3 Contents CY8C27xxx Final Data Sheet 3.5 3.6 4. Supervisory ROM (SROM) . 49 4.1 4.2 4.3 5. Register Definitions.67 8.1.1 IMO_TR Register .67 Internal Low Speed Oscillator (ILO) . 69 9.1 4 Register Definitions.66 7.1.1 ABF_CR0 Register .66 Internal Main Oscillator (IMO) . 67 8.1 9. Architectural Description .61 Register Definitions.62 6.2.1 PRTxDR Registers.62 6.2.2 PRTxIE Registers .62 6.2.3 PRTxGS Registers.62 6.2.4 PRTxDMx Registers .63 6.2.5 PRTxICx Registers .63 Analog Output Drivers . 65 7.1 8. Architectural Description .56 Register Definitions.56 5.2.1 INT_CLRx Register.56 5.2.2 INT_MSKx Register .56 5.2.3 INT_VC Register.57 5.2.4 CPU_F Register.57 General Purpose IO (GPIO) . 59 6.1 6.2 7. Architectural Description .49 4.1.1 Additional SROM Feature .50 4.1.2 SROM Function Descriptions.50 Register Definitions.53 4.2.1 CPU_SCR1 Register .53 Clocking .53 Interrupt Controller . 55 5.1 5.2 6. Addressing Modes .43 3.5.1 Source Immediate.43 3.5.2 Source Direct .44 3.5.3 Source Indexed.44 3.5.4 Destination Direct.44 3.5.5 Destination Indexed .45 3.5.6 Destination Direct Source Immediate .45 3.5.7 Destination Indexed Source Immediate .45 3.5.8 Destination Direct Source Direct.46 3.5.9 Source Indirect Post Increment.46 3.5.10 Destination Indirect Post Increment .46 Register Definitions.47 3.6.1 CPU_F (Flag) Register .47 Register Definitions.69 9.1.1 ILO_TR Register .69 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet Contents 10. 32 kHz Crystal Oscillator (ECO) .71 10.1 10.2 ECO External Components.72 Register Definitions .72 10.2.1 OSC_CR0 Register.72 10.2.2 ECO_TR Register .73 10.2.3 CPU_SCR1 Register.73 11. Phase Locked Loop (PLL) .75 11.1 Register Definitions .75 11.1.1 OSC_CR0 Register.75 11.1.2 OSC_CR2 Register.76 12. Sleep and Watchdog .77 12.1 12.2 12.3 12.4 12.5 Architectural Description .77 12.1.1 32 kHz Clock Selection .77 12.1.2 Sleep Timer .78 12.1.3 Sleep Bit.78 Application Description.78 Register Definitions .79 12.3.1 INT_MSK0 Register .79 12.3.2 RES_WDT Register .79 12.3.3 OSC_CR0 Register.79 12.3.4 CPU_SCR1 Register.80 12.3.5 ILO_TR Register .80 12.3.6 ECO_TR Register .80 12.3.7 CPU_SCR0 Register.80 Timing Diagrams .81 12.4.1 Sleep Sequence.81 12.4.2 Wake Up Sequence .82 12.4.3 Bandgap Refresh .83 12.4.4 Watchdog Timer (WDT) .83 Power Consumption.84 SECTION C REGISTER REFERENCE 85 Register Conventions .85 Register Mapping Tables .85 Register Map 0 Table: User Space .86 Register Map 1 Table: Configuration Space .87 13. Register Details .89 13.1 August 28, 2003 Bank 0 Registers.90 13.1.1 PRTxDR .90 13.1.2 PRTxIE .91 13.1.3 PRTxGS .92 13.1.4 PRTxDM2 .93 13.1.5 DxBxxDR0 .94 13.1.6 DxBxxDR1 .95 13.1.7 DxBxxDR2 .96 13.1.8 DxBxxCR0 .97 13.1.9 DxBxxCR0 .98 Document No. 38-12012 Rev. *C 5 Contents CY8C27xxx Final Data Sheet 13.1.10 13.1.11 13.1.12 13.1.13 13.1.14 13.1.15 13.1.16 13.1.17 13.1.18 13.1.19 13.1.20 13.1.21 13.1.22 13.1.23 13.1.24 13.1.25 13.1.26 13.1.27 13.1.28 13.1.29 13.1.30 13.1.31 13.1.32 13.1.33 13.1.34 13.1.35 13.1.36 13.1.37 13.1.38 13.1.39 13.1.40 13.1.41 13.1.42 13.1.43 13.1.44 13.1.45 13.1.46 13.1.47 13.1.48 13.1.49 13.1.50 13.1.51 13.1.52 13.1.53 13.1.54 13.1.55 13.1.56 13.1.57 13.1.58 13.1.59 13.1.60 13.1.61 13.1.62 6 DxBxxCR0 .99 DxBxxCR0 .100 DCBxxCR0 .101 DCBxxCR0 .102 DCBxxCR0 .103 DCBxxCR0 .104 AMX_IN .105 ARF_CR .106 CMP_CR0 .107 ASY_CR .108 CMP_CR1 .109 ACBxxCR3 .110 ACBxxCR0 .111 ACBxxCR1 .112 ACBxxCR2 .113 ASCxxCR0 .114 ASCxxCR1 .115 ASCxxCR2 .116 ASCxxCR3 .117 ASDxxCR0 .118 ASDxxCR1 .119 ASDxxCR2 .120 ASDxxCR3 .121 RDIxRI .122 RDIxSYN .123 RDIxIS .124 RDIxLT0 .125 RDIxLT1 .126 RDIxRO0 .127 RDIxRO1 .128 I2C_CFG .129 I2C_SCR .130 I2C_DR .131 I2C_MSCR .132 INT_CLR0 .133 INT_CLR1 .135 INT_CLR3 .137 INT_MSK3 .138 INT_MSK0 .139 INT_MSK1 .140 INT_VC .141 RES_WDT .142 DEC_DH .143 DEC_DL .144 DEC_CR0 .145 DEC_CR1 .146 MUL_X .147 MUL_Y .148 MUL_DH .149 MUL_DL .150 MAC_X/ACC_DR1 .151 MAC_Y/ACC_DR0 .152 MAC_CL0/ACC_DR3 .153 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet 13.2 Contents 13.1.63 MAC_CL1/ACC_DR2 .154 13.1.64 CPU_F .155 13.1.65 CPU_SCR1 .156 13.1.66 CPU_SCR0 .157 Bank 1 Registers.158 13.2.1 PRTxDM0 .158 13.2.2 PRTxDM1 .159 13.2.3 PRTxIC0 .160 13.2.4 PRTxIC1 .161 13.2.5 DxBxxFN .162 13.2.6 DxBxxIN .164 13.2.7 DxBxxOU .165 13.2.8 CLK_CR0 .167 13.2.9 CLK_CR1 .168 13.2.10 ABF_CR0 .169 13.2.11 AMD_CR0 .170 13.2.12 AMD_CR1 .171 13.2.13 ALT_CR0 .172 13.2.14 ALT_CR1 .173 13.2.15 CLK_CR2 .174 13.2.16 GDI_O_IN .175 13.2.17 GDI_E_IN .176 13.2.18 GDI_O_OU .177 13.2.19 GDI_E_OU .178 13.2.20 OSC_CR4 .179 13.2.21 OSC_CR3 .180 13.2.22 OSC_CR0 .181 13.2.23 OSC_CR1 .182 13.2.24 OSC_CR2 .183 13.2.25 VLT_CR .184 13.2.26 VLT_CMP .185 13.2.27 IMO_TR .186 13.2.28 ILO_TR .187 13.2.29 BDG_TR .188 13.2.30 ECO_TR .189 SECTION D DIGITAL SYSTEM 191 Top-Level Digital Architecture .191 Digital Register Summary .192 14. Global Digital Interconnect (GDI) . 195 14.1 14.2 Architectural Description .195 Register Definitions .197 14.2.1 GDI_O_IN and GDI_E_IN Registers.197 14.2.2 GDI_O_OU and GDI_E_OU Registers .197 15. Array Digital Interconnect (ADI) . 199 15.1 Architectural Description .199 16. Row Digital Interconnect (RDI) . 201 16.1 16.2 August 28, 2003 Architectural Description .201 Register Definitions .204 Document No. 38-12012 Rev. *C 7 Contents CY8C27xxx Final Data Sheet 16.3 16.2.1 RDIxRI Register .204 16.2.2 RDIxSYN Register .204 16.2.3 RDIxIS Register .204 16.2.4 RDIxLTx Registers .205 16.2.5 RDIxROx Registers.205 Timing Diagram .205 17. Digital Blocks . 207 17.1 17.2 17.3 Architectural Description .207 17.1.1 Input Multiplexers.207 17.1.2 Input Clock Resynchronization .208 17.1.3 Output De-Multiplexers .209 17.1.4 Block Chaining Signals .209 17.1.5 Timer Function .210 17.1.6 Counter Function .210 17.1.7 Dead Band Function . 211 17.1.8 CRCPRS Function .212 17.1.9 SPI Protocol Function .213 17.1.10 SPI Master Function .214 17.1.11 SPI Slave Function .214 17.1.12 Asynchronous Transmitter Function .215 17.1.13 Asynchronous Receiver Function .215 Register Definitions.216 17.2.1 DxBxxDRx Registers .216 17.2.2 DxBxxCR0 Register .221 17.2.3 INT_MSK1 Register .221 17.2.4 DxBxxFN Registers.221 17.2.5 DxBxxIN Registers.222 17.2.6 DxBxxOU Registers .222 Timing Diagrams.222 17.3.1 Timer Timing .223 17.3.2 Counter Timing .224 17.3.3 Dead Band Timing .224 17.3.4 CRCPRS Timing .226 17.3.5 SPI Mode Timing .226 17.3.6 SPIM Timing .227 17.3.7 SPIS Timing .230 17.3.8 Transmitter Timing .233 17.3.9 Receiver Timing .234 SECTION E ANALOG SYSTEM 237 Top-Level Analog Architecture .237 Analog Register Summary .239 18. Analog Interface . 241 18.1 8 Architectural Description .241 18.1.1 Analog Data Bus Interface .241 18.1.2 Analog Comparator Bus Interface.241 18.1.3 Analog Column Clock Generation.243 18.1.4 Decimator and Incremental ADC Interface .244 18.1.5 Analog Modulator Interface (Mod Bits) .244 18.1.6 Analog Synchronization Interface (Stalling) .244 18.1.7 SAR Hardware Acceleration .244 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet 18.2 Contents Register Definitions .246 18.2.1 CMP_CR0 Register.246 18.2.2 CMP_CR1 Register.246 18.2.3 ASY_CR Register .246 18.2.4 DEC_CR0 Register .247 18.2.5 DEC_CR1 Register .247 18.2.6 CLK_CR0 Register.248 18.2.7 CLK_CR1 Register.248 18.2.8 CLK_CR2 Register.248 18.2.9 AMD_CR0 Register.248 18.2.10 AMD_CR1 Register.248 18.2.11 ALT_CR0 Register .248 18.2.12 ALT_CR1 Register .248 19. Analog Array . 249 19.1 19.2 Architectural Description .249 19.1.1 Analog Comparator Bus.252 Temperature Sensing Capability.253 20. Analog Input Configuration . 255 20.1 20.2 Register Definitions .255 20.1.1 AMX_IN Register .255 20.1.2 ABF_CR0 Register.255 Architectural Description .256 21. Analog Reference . 257 21.1 21.2 Architectural Description .257 Register Definitions .258 21.2.1 ARF_CR Register .258 22. Switched Capacitor Block . 259 22.1 22.2 22.3 Architectural Description .260 Application Description.261 Register Definitions .261 22.3.1 ASCxxCR0 Register.262 22.3.2 ASCxxCR1 Register.262 22.3.3 ASCxxCR2 Register.262 22.3.4 ASCxxCR3 Register.263 22.3.5 ASDxxCR0 Register.263 22.3.6 ASDxxCR1 Register.263 22.3.7 ASDxxCR2 Register.263 22.3.8 ASDxxCR3 Register.264 23. Continuous Time Block . 265 23.1 23.2 August 28, 2003 Architectural Description .265 Register Definitions .267 23.2.1 ACBxxCR0 Register.267 23.2.2 ACBxxCR1 Register.267 23.2.3 ACBxxCR2 Register.267 23.2.4 ACBxxCR3 Register.267 Document No. 38-12012 Rev. *C 9 Contents CY8C27xxx Final Data Sheet SECTION F SYSTEM RESOURCES 271 Top-Level System Resources Architecture .271 System Resources Register Summary .272 24. Digital Clocks . 273 24.1 24.2 Architectural Description .273 24.1.1 Internal Main Oscillator .273 24.1.2 Internal Low Speed Oscillator .274 24.1.3 32 kHz Crystal Oscillator.274 24.1.4 External Clock.274 Register Definitions.276 24.2.1 INT_CLR0 Register.276 24.2.2 INT_MSK0 Register .276 24.2.3 OSC_CR0 Register.276 24.2.4 OSC_CR1 Register.277 24.2.5 OSC_CR2 Register.277 24.2.6 OSC_CR3 Register.278 24.2.7 OSC_CR4 Register.278 25. Multiply Accumulate (MAC) . 279 25.1 25.2 25.3 Architectural Description .279 Application Description .280 25.2.1 Multiplication with No Accumulation.280 25.2.2 Accumulation After Multiplication .280 Register Definitions.280 25.3.1 MUL_X Register.280 25.3.2 MUL_Y Register.280 25.3.3 MUL_DH Register.280 25.3.4 MUL_DL Register .280 25.3.5 MAC_X/ACC_DR1.280 25.3.6 MAC_Y/ACC_DR0.281 25.3.7 MAC_CL0/ACC_DR3.281 25.3.8 MAC_CL1/ACC_DR2.281 26. Decimator . 283 26.1 Register Definitions.283 26.1.1 DEC_DH Register.283 26.1.2 DEC_DL Register .284 26.1.3 DEC_CR0 Register.284 26.1.4 DEC_CR1 Register.284 27. I2C . 285 27.1 27.2 27.3 10 Architectural Description .286 27.1.1 Basic I2C Data Transfer.286 Application Description .287 27.2.1 Slave Operation .287 27.2.2 Master Operation .288 Register Definitions.289 27.3.1 I2C_CFG Register .289 27.3.2 I2C_SCR Register .291 27.3.3 I2C_DR Register.293 27.3.4 I2C_MSCR Register .293 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet 27.4 Contents Timing Diagrams .294 27.4.1 Clock Generation .294 27.4.2 Enable and Command Synchronization.295 27.4.3 Basic Input/Output Timing .295 27.4.4 Status Timing.296 27.4.5 Master Start Timing .297 27.4.6 Master Restart Timing .298 27.4.7 Master Stop Timing .298 27.4.8 Master/Slave Stall Timing.299 27.4.9 Master Lost Arbitration Timing .299 27.4.10 Master Clock Synchronization.300 28. POR and LVD . 301 28.1 Register Definitions .301 28.1.1 VLT_CR Register .301 28.1.2 VLT_CMP Register .301 29. Internal Voltage Reference . 303 29.1 29.2 Architectural Description .303 Register Definitions .303 29.2.1 BDG_TR Register .303 30. Switch Mode Pump (SMP) . 305 30.1 Register Definitions .306 30.1.1 VLT_CR Register .306 31. System Resets . 307 31.1 31.2 31.3 Register Definitions .307 31.1.1 CPU_SCR0 Register.307 31.1.2 CPU_SCR1 Register.308 Timing Diagrams .308 31.2.1 Power On Reset (POR).308 31.2.2 External Reset (XRES) .308 31.2.3 Watchdog Timer Reset (WDR).308 31.2.4 Reset Details .310 Power Consumption.311 SECTION G ELECTRICAL SPECIFICATIONS 313 Absolute Maximum Ratings .314 Operating Temperature .314 DC Electrical Characteristics .315 DC Chip-Level Specifications .315 DC General Purpose IO (GPIO) Specifications .315 DC Operational Amplifier Specifications .316 DC Analog Output Buffer Specifications .318 DC Switch Mode Pump Specifications .319 DC Analog Reference Specifications .320 DC Analog PSoC Block Specifications .322 DC POR and LVD Specifications .322 DC Programming Specifications .323 August 28, 2003 Document No. 38-12012 Rev. *C 11 Contents CY8C27xxx Final Data Sheet AC Electrical Characteristics .324 AC Chip-Level Specifications .324 AC General Purpose IO (GPIO) Specifications .324 AC Operational Amplifier Specifications .325 AC Digital Block Specifications .327 AC Analog Output Buffer Specifications .328 AC External Clock Specifications .329 AC Programming Specifications .329 AC I2C Specifications .330 SECTION H REVISION HISTORY 12 331 Document No. 38-12012 Rev. *C August 28, 2003 SECTION A OVERVIEW The PSoCTM family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pin-outs. The Overview section discusses the Features, Getting Started, Top-Level Architecture, Development Tools, User Modules and Development Process, along with Ordering Information. It also lists the Conventions used in this document. This section encompasses the following chapters: Pin Information on page 23 Packaging Information on page 29 Flexible On-Chip Memory ­16K Bytes Flash Program Storage 50,000 Erase/write Cycles ­256 Bytes SRAM Data Storage ­In-System Serial Programming (ISSP) ­Partial Flash Updates ­Flexible Protection Modes ­EEPROM Emulation in Flash Programmable Pin Configurations ­25 mA Drive on all GPIO ­Pull up, Pull down, High Z, Strong, or Open Drain ­Drive Modes on all GPIO ­Up to 12 Analog Inputs on GPIO ­Four 40 mA Analog Outputs on GPIO ­Configurable Interrupt on all GPIO Additional System Resources ­I2C Slave, Master and Multi-Master to 400 kHz ­Watchdog and Sleep Timers ­User-Configurable Low Voltage Detection ­Integrated Supervisory Circuit ­On-Chip Precision Voltage Reference Complete Development Tools ­Free Development Software (PSoC Designer) ­Full-Featured In-Circuit Emulator and Programmer ­Full Speed Emulation ­Complex Breakpoint Structure ­128K Bytes Trace Memory Features Powerful Harvard Architecture Processor ­M8C Processor Speeds to 24 MHz ­8x8 Multiply, 32-Bit Accumulate ­Low Power at High Speed ­3.0 to 5.25 V Operating voltage ­Operating Voltages Down to 1.0 V Using On-Chip Switch Mode Pump (SMP) ­Industrial Temperature Range: -40 oC to + 85 oC Advanced Peripherals (PSoC Blocks) ­12 Rail-to-Rail Analog PSoC Blocks Provided - -Up to 14 Bit ADCs - -Up to 9 Bit DACs - -Programmable Gain Amplifiers - -Programmable Filters and Comparators ­8 Digital PSoC Blocks Provide: - -8- to 32-Bit Timers, Counters and PWMs - -CRC and PRS Modules - -Up to 2 Full-Duplex UARTs - -Multiple SPI Masters Or Slaves - -Connectable to all GPIO Pins ­Complex peripherals by combining blocks Precision, Programmable Clocking ­Internal +/- 2.5% 24/48 MHz Oscillator ­24/48 MHz with Optional 32 kHz Crystal ­Optional External Oscillator, up to 24 MHz ­Internal Oscillator for Watchdog and Sleep August 28, 2003 Document No. 38-12012 Rev. *C 13 SECTION A OVERVIEW CY8C27xxx Final Data Sheet Getting Started The quickest path to understanding the PSoC silicon is through the PSoC Designer software GUI. This data sheet is useful for understanding the details of the PSoC integrated circuit, but is not a good starting point for a new PSoC developer seeking to get a general overview of this new technology. PSoC developers are not required to build their own ADCs, DACs, and other peripherals. Embedded in the PSoC Designer software are the individual data sheets, performance graphs, and PSoC User Modules (graphically selected code packets) for the peripherals, such as the incremental ADCs, DACs, LCD controllers, op amps, low-pass filters, etc. With simple GUI-based selection, placement, and connection, the basic architecture of a design may be developed within PSoC Designer software without ever writing a single line of code. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress.com http://www.onfulfillment.com/cypressstore/ Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Online Store web site and click on PSoC (Programmable System-on-Chip) to view a current list of available items. Tele-Training PSoC "Tele-training" is available for beginners every Friday at 10 am Pacific Time taught by a live marketing or application engineer over the phone. Please see http://www.cypress.com/support/training.cfm for more details. Five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to the following web site, http://www.cypress.com/support/cypros.cfm. Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. 14 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet SECTION A OVERVIEW Top-Level Architecture The figure below illustrates the top-level architecture of the PSoC CY8C27xxx. SYSTEM BUS Port 5 Port 4 Port 3 Port 2 Port 1 Analog Drivers Port 0 Global Digital Interconnect Global Analog Interconnect PSoC CORE Supervisory ROM (SROM) SRAM Flash Nonvolatile Memory CPU Core (M8C) Interrupt Controller 24 MHz Internal Main Oscillator (IMO) Sleep and Watchdog Internal Low Speed Oscillator (ILO) 32 kHz Crystal Oscillator (ECO) Phased Locked Loop (PLL) DIGITAL SYSTEM ANALOG SYSTEM Analog Refs Analog PSoC Block Array Digital PSoC Block Array DB DB DB DC DC CT DC Multiply Accumulate (MAC) CT SC SC SC SC SC SC Analog Bi-Columns Digital Rows Digital Clocks CT SC DC CT SC DB Analog Input Muxing Decimator I2C POR and LVD System Resets Internal Voltage Reference Switch Mode Pump SYSTEM RESOURCES PSoC CY8C27xxx Top-Level Block Diagram August 28, 2003 Document No. 38-12012 Rev. *C 15 SECTION A OVERVIEW CY8C27xxx Final Data Sheet Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer runs on Windows 98, Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses Context Sensitive Help Results Commands Graphical Designer Interface Importable Design Database Device Database PSoC Configuration Sheet Application Database Project Database Manufacturing Information File User Modules Database Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Subsystems PSoC Designer Software Subsystems Device Editor PSoC Designer has several main functions. In the Design Editor you can easily configure a design and APIs are automatically generated for the user modules. The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configuration at run time. 16 PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at runtime. PSoC Designer can print out a configuration sheet for given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet SECTION A OVERVIEW Design Browser Online Help System The Design Browser allows users to select and import preconfigured designs into the user's project. User's can easily browse a catalog of preconfigured designs to facilitate timeto-design. Recent examples provided in the tools include a 300-baud modem, Lin Bus master and slave, fan controller, and magnetic card reader. The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Application Editor Hardware Tools In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. In-Circuit Emulator Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. An ANSI C language compiler supports Cypress MicroSystems' PSoC family devices (except for 64-bit doubles). Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulation consists of a base unit that connects to the PC by way of the parallel port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and write program and data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. PSoC Development Tool Kit User Modules and Development Process The development process for the PSoC is different than a traditional fixed function microcontroller. The flexibility of the PSoC architecture comes from configurable analog and digital hardware blocks called PSoC Blocks. These blocks have the capability to implement a wide variety of user selectable functions. Each block has several registers that allow you to select the function. These registers also determine the interconnections between this block and other blocks, as well as the connection to the I/O pins. (Reference Figure below.) To make the entire development process of your project easier, the PSoC Designer Integrated Development Environment (IDE) has libraries of open source code software modules, called "User Modules," that simplify the configura- August 28, 2003 tion process. These user modules have been created to make selecting and implementing peripheral functions very easy. User modules come in analog, digital, and mixed signal varieties. Each user module contains all the register settings to implement the selected function and also contains Application Programmer Interface (API) software to make the interface to your source code simple. The development process starts when you open a new project. You then pick a set of user modules, as the basis of the custom configuration for that project. You can view the details of all the available user modules inside the development software and pick the user modules that are perfect for your application. You then must assign each of these user Document No. 38-12012 Rev. *C 17 SECTION A OVERVIEW CY8C27xxx Final Data Sheet modules to hardware resources. You also make the interconnections between the user modules, and between the user modules and the I/O pins. This process step takes place in the Device Editor subsystem within PSoC Designer. There are two views inside this step: one for selecting user modules and one for assigning them to the hardware blocks and interconnecting them. The last action in this step is to "Generate Application," which causes the development software to automatically generate the required files for the selected configuration. Device Editor ! ! ! ! ! ! ! Browse libraries of User Module View datasheets for User Modules Select individual User Modules to add to configuration Calculate resource requirements for slected User Modules User Module Selection View Assign User Modules to Hardware PSoC Blocks Make interconnections between User Modules Make interconnections to device pins User Module Placement View "Generate Application" Application Editor ! ! ! ! Edit source code files written in C and Assembly language Assemble/Compile See breakpoints "Make" function for generation of enitre project including subfiles Source Code Editor "Make" Automatic Object Code Generation ! ! ! ! ! Interface to In-Circuit Emulator for debug Define complex break events Enable trace capability View contents of program/ register/ram space Run/stop/step program Debugger Interface to In-Circuit Emulator User Modules and Development Process Flow Chart The next step in the process is to write your main program, and any other sub-routines required by your application. This step takes place in the Application Editor subsystem. You will have all the subroutines automatically generated for the user modules you have chosen and the source code for these routines can be viewed in this step as well. The different files created for the project are all contained in a tree structure for easy reference. The development software has 18 a handy "Make" function, which assembles and compiles all source files, and links them into an object file ready for the debugging process. The last step in development takes place in the Debugger subsystem. This is where the object code is downloaded into the In-Circuit Emulator and run. The Debugger is both the interface to the ICE and also contains an advanced set Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet SECTION A OVERVIEW of tools for finding and removing bugs from your software. Some of the capabilities of the tools are full-speed emula- tion, defining complex breakpoint events, and a large trace memory. Ordering Information The following table lists the PSoC Device family's key features and ordering codes. Digital IO Pins Analog inputs Analog Outputs XRES Pin 256 No -40C to +85C 8 12 6 4 4 No 20 Pin (210 Mil) SSOP CY8C27243-24PVI CY8C27243-24PVI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin (210 Mil) SSOP (Tape and Reel) CY8C27243-24PVIT CY8C27243-24PVIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 28 Pin (300 Mil) DIP CY8C27443-24PI CY8C27443-24PI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP CY8C27443-24PVI CY8C27443-24PVI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP (Tape and Reel) CY8C27443-24PVIT CY8C27443-24PVIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 44 Pin TQFP CY8C27543-24AI CY8C27543-24AI 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 44 Pin TQFP (Tape and Reel) CY8C27543-24AIT CY8C27543-24AIT 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 48 Pin (300 Mil) SSOP CY8C27643-24PVI CY8C27643-24PVI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (300 Mil) SSOP (Tape and Reel) CY8C27643-24PVIT CY8C27643-24PVIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF CY8C27643-24LFI CY8C27643-24LFI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF (Tape and Reel) CY8C27643-24LFIT CY8C27643-24LFIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes August 28, 2003 Document No. 38-12012 Rev. *C (Columns of 3) Temperature Range Analog PSoC Blocks Switch Mode Pump 16 (Rows of 4) RAM (Bytes) CY8C27143-24PI CY8C27143-24PI Ordering Code 8 Pin (300 Mil) DIP Package Flash (Kbytes) Digital PSoC Blocks Device Family Key Features 19 SECTION A OVERVIEW CY8C27xxx Final Data Sheet Organization and Conventions Document Organization Units of Measure This document is organized into the following sections: The following table lists the units of measure used in this document. Overview Core Architecture Register Reference Symbol Units of Measure oC degree Celsius Digital System AC alternating current Analog System dB decibels System Resources DC direct current Electrical Specifications fF femto Farad Revision History Hz hertz Each section and its associated chapters is organized according to PSoC functionality. If applicable, all chapters have a brief introduction, an architectural/application description, register definitions, and timing diagrams. The last section, Electrical Specifications, has no chapters associated with it and presents the PSoC device's electrical specifications. The Revision History section chronologically lists the document's history. k kilo, 1000 K 210, 1024 KB 1024 bytes Kbit 1024 bits kHz kilohertz k kilohm MHz megahertz M megaohm Document Conventions µA microampere µs microsecond Register Conventions µV microvolts The following table lists the register conventions that are specific to this document. µVrms microvolts root-mean-square mA milliampere ms Convention Example `x' in a register name ACBxxCR1 millisecond mV millivolts Multiple instances/address ranges of the same register. nA nanoamphere nanosecond Description RW RW:00 Read and write register or bit(s) ns R R:00 Read register or bit(s) nV nanovolts W W:00 Write register or bit(s) ohm L RL:00 Logical register or bit(s) pF pico Farad C RC:00 Clearable register or bit(s) pp peak-to-peak 00 RW:00 Reset value is 0x00 or 00h XX RW:XX Register is not reset 0, 0,04h Register is in bank 0 1, 1, 23h Register is in bank 1 x, x,F7h Empty, grayedout table cell ppm parts per million sps samples per second Register exists in register bank 0 and register bank 1 sigma: one standard deviation V volts Reserved bit or group of bits, unless otherwise stated. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. 20 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet SECTION A OVERVIEW Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC AI API APOR BC CMRR CPU CRC CT DAC DC DNL DO ECO EEPROM FB full scale range GIE integrated development environment ILO internal low speed oscillator INL integral nonlinearity IO input/output IOW IO write IPOR imprecise power on reset IRA interrupt request acknowledge IRQ interrupt request ISR interrupt service routine ISSP in-circuit system serial programming IVR interrupt vector read LFSR linear feedback shift register LPF low pass filter LSB least-significant bit LUT lookup table MISO master-in-slave-out MOSI master-out-slave-in MSB most-significant bit PC program counter PCH program counter high PCL program counter low PD power down PDDSC power system sleep duty cycle PGA programmable gain amplifier POR power on reset PPOR precision power on reset PRS pseudo random sequence PSoCTM Programmable System-on-Chip PSRR watchdog reset in-circuit emulator IDE watchdog timer WDR general purpose IO ICE voltage controlled oscillator global interrupt enable GPIO terminal count VCO WDT electrically erasable programmable read-only memory serial peripheral interconnect TC external crystal oscillator sequential phase detector SPI digital or data output stack pointer SPD differential nonlinearity start of instruction SP direct current signal-to-noise ratio SOI digital-to-analog converter switched capacitor SNR continuous time successive approximation register SC cyclic redundancy check read only memory SAR central processing unit row output ROM common mode rejection ratio row input RO broadcast clock return from interrupt RI analog power on reset ROM access strobe RETI application programming interface random access memory RAS analog input pulse width modulator RAM alternating current FSR Description process voltage temperature PWM Description feedback Acronym PVT power supply rejection ratio August 28, 2003 Document No. 38-12012 Rev. *C 21 SECTION A OVERVIEW 22 CY8C27xxx Final Data Sheet Document No. 38-12012 Rev. *C August 28, 2003 1. Pin Information This chapter lists, describes, and illustrates the PSoC device pins and pinouts. Table 1-1 presents a summary of the device pins, and the following tables and illustrations detail a representation of the device's pinouts. 1.1 Pin Summary Table 1-1. PSoC Device Pin Descriptions Pin Name Description Input/Output SMP Switch Mode Pump Power Vdd Supply Voltage Power Vss Ground Power XRES External Reset (Active High) Input P0[0] ­ P0[1] Port 0[0], 0[1], Analog Input Input/Output P0[2] ­ P0[5] Port 0[2], 0[3], 0[4], 0[5], Analog Input/Output Input/Output P0[6] ­ P0[7] Port 0[6], 0[7], Analog Input Input/Output P1[0] Port 1[0], XTALOut/SDATA / I C SDA Input/Output P1[1] Port 1[1], XTALIn/SCLK / I2C SCL Input/Output P1[2] Port 1[2] Input/Output P1[3] Port 1[3] Input/Output P1[4] Port 1[4], EXTCLK 2 Input/Output P1[5] Port 1[5], I C SDA Input/Output P1[6] Port 1[6] Input/Output 2 P1[7] Port 1[7], I C SCL Input/Output P2[0] ­ P2[3] Port 2[0], 2[1], 2[2], 2[3], Non-Multiplexed Analog Input (Switched Capacitor) Input/Output P2[4] Port 2[4], External AGND Input/Output P2[5] Port 2[5] Input/Output P2[6] Port 2[6], External VREF Input/Output P2[7] Port 2[7] Input/Output P3[0]-P3[7] Port 3[0], 3[1], 3[2], 3[3], 3[4], 3[5], 3[6], 3[7] Input/Output P4[0]-P4[7] Port 4[0], 4[1], 4[2], 4[3], 4[4], 4[5], 4[6], 4[7] Input/Output P5[0]-P5[3] Port 5[0], 5[1], 5[2], 5[3] Input/Output August 28, 2003 2 Document No. 38-12012 Rev. *C 23 Pin Information 1.2 CY8C27xxx Final Data Sheet Pinouts The PSoC devices are available in a variety of packages. Refer to the following information for details on individual devices. Note that every port pin (labeled with a "P"), except for Vss, Vdd, SMP, and XRES in the following tables and illustrations, is capable of Digital IO. Table 1-2. 8-Pin Part Pinout (PDIP) Pin No. Pin No. Description 1 P0[5], A in, out 2 P0[3], A in, out 3 P1[1], XTALin, Description Pin No. Description 4 P0[4], A in, out P1[0], XTALout, I2C SDA 8 Vdd 6 SCL 7 5 I2C Vss P0[2], A in, out LEGEND A: analog, D: digital, IO: input or output. AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 PDIP Vdd P0[4], AIO P0[2], AIO P1[0], XTALout, I2C SDA 8 7 6 5 Table 1-3. 20-Pin Part Pinout (SSOP) Pin No. Pin No. Description Description Pin No. Description 1 P0[7], A in 8 P1[3] 15 XRES 2 P0[5], A in, out 9 P1[1], XTALin, I2C SCL 16 P0[0], A in 3 P0[3], A in, out 10 Vss 17 P0[2], A in, out 4 P0[1], A in 11 P1[0], XTALout, I2C SDA 18 P0[4], A in, out 5 SMP 12 P1[2] 19 P0[6], A in 20 Vdd 6 P1[7], SCL 13 P1[4], EXTCLK 7 P1[5], I2C SDA 14 P1[6] I2C LEGEND A: analog, D: digital, IO: input or output. AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 24 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet Pin Information Table 1-4. 28-Pin Part Pinout (PDIP, SSOP) Pin No. Pin No. Description Description Pin No. Description 1 P0[7], A in 11 P1[5], I2C SDA 21 P2[2], A in (ASD13 ASD13, ASC23 ASC23) 2 P0[5], A in, out 12 P1[3] 22 P2[4], A in (AGND) 3 P0[3], A in, out 13 P1[1], XTALin, I2C SCL 23 P2[6], A in (Ref) 4 P0[1], A in 14 Vss 24 P0[0], A in 5 P2[7] 15 P1[0], XTALout, I2C SDA 25 P0[2], A in, out 6 P2[5] 16 P1[2], 26 P0[4], A in, out 7 P2[3], A in (ASC10 ASC10) 17 P1[4], EXTCLK 27 P0[6], A in 8 P2[1], A in (ASD20 ASD20, ASC10 ASC10) 18 P1[6] 28 Vdd 9 SMP 19 XRES 10 P1[7], I2C SCL 20 P2[0], A in (ASC23 ASC23) LEGEND A: analog, D: digital, IO: input or output. AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI (ASC10 ASC10), P2[3] AI (ASD20 ASD20, ASC10 ASC10), P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss August 28, 2003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP / SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], AI (Ref) P2[4], AI (AGND) P2[2], AI (ASD13 ASD13, ASC23 ASC23) P2[0], AI (ASC23 ASC23) XRES P1[6] P1[4] EXTCLK P1[2] P1[0], XTALout, I2C SDA Document No. 38-12012 Rev. *C 25 Pin Information CY8C27xxx Final Data Sheet Table 1-5. 44-Pin Part Pinout (TQFP) Pin No. Pin No. Description Description Pin No. Description 1 P2[5] 16 P1[1], XTALin, I2C SCL 31 P2[0], A in (ASC23 ASC23) 2 P2[3], A in (ASC10 ASC10) 17 Vss 32 P2[2], A in (ASD13 ASD13, ASC23 ASC23) 3 P2[1], A in (ASD20 ASD20, ASC10 ASC10) 18 P1[0], XTALout, I2C SDA 33 P2[4], A in (AGND) 4 P4[7] 19 P1[2] 34 P2[6], A in (Ref) 5 P4[5] 20 P1[4], EXTCLK 35 P0[0], A in 6 P4[3] 21 P1[6] 36 P0[2], A in, out 7 P4[1] 22 P3[0] 37 P0[4], A in, out 8 SMP 23 P3[2] 38 P0[6], A in 9 P3[7] 24 P3[4] 39 Vdd 10 P3[5] 25 P3[6] 40 P0[7], A in 11 P3[3] 26 XRES 41 P0[5], A in, out 12 P3[1] 27 P4[0] 42 P0[3], A in, out 13 P1[7], I2C SCL 28 P4[2] 43 P0[1], A in 14 I2 P1[5], C SDA 29 P4[4] 44 P2[7] 15 P1[3] 30 P4[6] 44 43 42 41 40 39 38 37 36 35 34 P2[7] P0[1], AI P0[3], AIO P0[5], AIO P0[7], AI Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], AI (Ref) LEGEND A: analog, D: digital, IO: input or output. TQFP 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 P2[4], AI (AGND) P2[2], AI (ASD13 ASD13, ASC23 ASC23) P2[0], AI (ASC23 ASC23) P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P3[0] P2[5] AI (ASC10 ASC10), P2[3] AI (ASD20 ASD20, ASC10 ASC10), P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] 26 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet Pin Information Table 1-6. 48-Pin Part Pinout (SSOP) Pin No. Pin No. Description Description Pin No. Description 1 P0[7], A in 17 P3[1] 33 P3[4] 2 P0[5], A in, out 18 P5[3] 34 P3[6] 3 P0[3], A in, out 19 P5[1] 35 XRES 4 P0[1], A in 20 P1[7], I2C SCL 36 P4[0] 5 P2[7] 21 P1[5], I2C SDA 37 P4[2] 6 P2[5] 22 P1[3] 38 P4[4] 7 P2[3], A in (ASC10 ASC10) 23 P1[1], XTALin, I2C SCL 39 P4[6] 8 P2[1], A in (ASD20 ASD20, ASC10 ASC10) 24 Vss 40 P2[0], A in (ASC23 ASC23) 9 P4[7] 25 P1[0], XTALout, I2C SDA 41 P2[2], A in (ASD13 ASD13, ASC23 ASC23) 10 P4[5] 26 P1[2] 42 P2[4], A in (AGND) 11 P4[3] 27 P1[4], EXTCLK 43 P2[6], A in (Ref) 12 P4[1] 28 P1[6] 44 P0[0], A in 13 SMP 29 P5[0] 45 P0[2], A in, out 14 P3[7] 30 P5[2] 46 P0[4], A in, out 15 P3[5] 31 P3[0] 47 P0[6], A in 16 P3[3] 32 P3[2] 48 Vdd LEGEND A: analog, D: digital, IO: input or output. AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI (ASC10 ASC10), P2[3] AI (ASD20 ASD20, ASC10 ASC10), P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] 2 I C SCL, P1[7] 2 I C SDA, P1[5] P1[3] 2 I C SCL, XTALin, P1[1] Vss August 28, 2003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], AI (Ref) P2[4], AI (AGND) P2[2], AI, (ASD13 ASD13, ASC23 ASC23) P2[0], AI (ASC23 ASC23) P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA Document No. 38-12012 Rev. *C 27 Pin Information CY8C27xxx Final Data Sheet Table 1-7. 48-Pin Part Pinout (MLF) Pin No. Description Pin No. Description Pin No. Description 1 P2[3], A in (ASC10 ASC10) 17 P1[1], XTALin, I2C SCL 33 P4[6] 2 P2[1], A in (ASD20 ASD20, ASC10 ASC10) 18 Vss 34 P2[0], A in (ASC23 ASC23) 3 P4[7] 19 P1[0], XTALout, I2C SDA 35 P2[2], A in (ASD13 ASD13, ASC23 ASC23) 4 P4[5] 20 P1[2] 36 P2[4], A in (AGND) 5 P4[3] 21 P1[4], EXTCLK 37 P2[6], A in (Ref) 6 P4[1] 22 P1[6] 38 P0[0], A in 7 SMP 23 P5[0] 39 P0[2], A in, out 8 P3[7] 24 P5[2] 40 P0[4], A in, out 9 P3[5] 25 P3[0] 41 P0[6], A in 10 P3[3] 26 P3[2] 42 Vdd 11 P3[1] 27 P3[4] 43 P0[7], A in 12 P5[3] 28 P3[6] 44 P0[5], A in, out 13 P5[1] 29 XRES 45 P0[3], A in, out 14 P1[7], I2C SCL 30 P4[0] 46 P0[1], A in 15 P1[5], I2C SDA 31 P4[2] 47 P2[7] 16 P1[3] 32 P4[4] 48 P2[5] LEGEND A: analog, D: digital, IO: input or output. 48 47 46 45 44 43 42 41 40 39 38 37 P2[5] P2[7] P0[1] A in P0[3] A in, out P0[5] A in, out P0[7] A in Vdd P0[6] A in P0[4] A in, out P0[2] A in, out P0[0], A in P2[6] A in (Ref) Note The MLF package has a center pad that must be connected to the ground (Vss). 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 MLF (Top View) P2[4] A in (AGND) P2[2] A in (ASD13 ASD13, ASC23 ASC23) P2[0] A in (ASC23 ASC23) P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[1] P1[7] I2C SCL P1[5] I2C SDA P1[3] P1[1] XTALin, I2C SCL Vss P1[0] XTALout, I2C SDA P1[2] P1[4] EXTCLK P1[6] P5[0] P5[2] 13 14 15 16 17 18 19 20 21 22 23 24 P2[3] A in (ASC10 ASC10) P2[1] A in (ASD20 ASD20, ASC10 ASC10) P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 28 Document No. 38-12012 Rev. *C August 28, 2003 2. Packaging Information This chapter presents and illustrates the packaging specifications for the PSoC device, along with the thermal impedances for each package. 2.1 Packaging Dimensions 51-85075 *A Figure 2-1. 8-Lead (300-Mil) PDIP August 28, 2003 Document No. 38-12012 Rev. *C 29 Packaging Information CY8C27xxx Final Data Sheet 51-85077 *C Figure 2-2. 20-Lead (210-Mil) SSOP 51-85079 *C Figure 2-3. 28-Lead (210-Mil) SSOP 30 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet Packaging Information 51-85014-B 51-85014-B Figure 2-4. 28-Lead (300-Mil) Molded DIP 51-85064-B 51-85064-B Figure 2-5. 44-Lead TQFP August 28, 2003 Document No. 38-12012 Rev. *C 31 Packaging Information CY8C27xxx Final Data Sheet 51-85061-C 51-85061-C Figure 2-6. 48-Lead (300-Mil) SSOP 51-85152-*A Figure 2-7. 48-Lead (7x7 mm) MLF 32 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet 2.2 Packaging Information Thermal Impedances Table 2-1. Thermal Impedances per Package Package Typical JA 8 PDIP 120 oC/W 20 SSOP 95 oC/W 28 PDIP 67 oC/W 28 SSOP 95 oC/W 44 TQFP 58 oC/W 48 SSOP 69 oC/W 48 MLF 18 oC/W August 28, 2003 Document No. 38-12012 Rev. *C 33 Packaging Information 34 CY8C27xxx Final Data Sheet Document No. 38-12012 Rev. *C August 28, 2003 SECTION B CORE ARCHITECTURE The Architecture section discusses the core components of the PSoC device and the registers associated with those components. This section encompasses the following chapters: CPU Core (M8C) on page 39 Internal Main Oscillator (IMO) on page 67 Supervisory ROM (SROM) on page 49 Internal Low Speed Oscillator (ILO) on page 69 Interrupt Controller on page 55 32 kHz Crystal Oscillator (ECO) on page 71 General Purpose IO (GPIO) on page 59 Phase Locked Loop (PLL) on page 75 Analog Output Drivers on page 65 Sleep and Watchdog on page 77 Top-Level Core Architecture The figure below displays the top-level architecture of the PSoC's core. Each component of the figure is discussed at length in this section. Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers SYSTEM BUS Supervisory ROM (SROM) SRAM Flash Nonvolatile Memory CPU Core (M8C) Interrupt Controller 24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Sleep and Watchdog 32 kHz Crystal Oscillator (ECO) Phased Locked Loop (PLL) PSoC Core Block Diagram August 28, 2003 Document No. 38-12012 Rev. *C 35 SECTION B CORE ARCHITECTURE CY8C27xxx Final Data Sheet Core Register Summary The table below lists all the PSoC registers that the core of the device uses. Summary Table of the Core Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Carry Zero GIE RL : 00 STOP RW : 17 IRAMDIS RW : 00 M8C REGISTERS M8C Register x,F7h XOI CPU_F Related Registers 1,E0h OSC_CR0 x,FFh CPU_SCR0 x,FEh CPU_SCR1 32k Select PLL Mode GIES No Buzz WDRS Sleep[1:0] PORS CPU Speed[2:0] Sleep RW : 00 SUPERVISORY ROM (SROM) REGISTER ECO_EXW ECO_EX INTERRUPT CONTROLLER REGISTERS 0,DAh INT_CLR0 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor RW : 00 0,DBh INT_CLR1 DCB13 DCB13 DCB12 DCB12 DBB11 DBB11 DBB10 DBB10 DCB03 DCB03 DCB02 DCB02 DBB01 DBB01 DBB00 DBB00 RW : 00 0,DDh INT_CLR3 I2C RW : 00 0,DEh INT_MSK3 ENSWINT I2C RW : 00 0,E0h INT_MSK0 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor RW : 00 0,E1h INT_MSK1 DCB13 DCB13 DCB12 DCB12 DBB11 DBB11 DBB10 DBB10 DCB03 DCB03 DCB02 DCB02 DBB01 DBB01 DBB00 DBB00 RW : 00 Carry Zero GIE 0,E2h INT_VC x,F7h CPU_F Pending Interrupt[7:0] XOI RC : 00 RL : 00 GENERAL PURPOSE IO (GPIO) REGISTERS 0,00h PRT0DR Data Input[7:0] 0,01h PRT0IE Interrupt Enables[7:0] RW : 00 RW : 00 0,02h PRT0GS Global Select[7:0] RW : 00 RW : FF 0,03h PRT0DM2 Drive Mode 2[7:0] 1,00h PRT0DM0 Drive Mode 0[7:0] RW : 00 1,01h PRT0DM1 Drive Mode 1[7:0] RW : FF 1,02h PRT0IC0 Interrupt Control 0[7:0] RW : 00 1,03h PRT0IC1 Interrupt Control 1[7:0] RW : 00 0,04h PRT1DR Data Input[7:0] RW : 00 0,05h PRT1IE Interrupt Enables[7:0] RW : 00 0,06h PRT1GS Global Select[7:0] RW : 00 RW : FF 0,07h PRT1DM2 Drive Mode 2[7:0] 1,04h PRT1DM0 Drive Mode 0[7:0] RW : 00 1,05h PRT1DM1 Drive Mode 1[7:0] RW : FF 1,06h PRT1IC0 Interrupt Control 0[7:0] RW : 00 1,07h PRT1IC1 Interrupt Control 1[7:0] RW : 00 0,08h PRT2DR Data Input[7:0] RW : 00 0,09h PRT2IE Interrupt Enables[7:0] RW : 00 0,0Ah PRT2GS Global Select[7:0] RW : 00 RW : FF 0,0Bh PRT2DM2 Drive Mode 2[7:0] 1,08h PRT2DM0 Drive Mode 0[7:0] RW : 00 1,09h PRT2DM1 Drive Mode 1[7:0] RW : FF 1,0Ah PRT2IC0 Interrupt Control 0[7:0] RW : 00 1,0Bh PRT2IC1 Interrupt Control 1[7:0] RW : 00 0,0Ch PRT3DR Data Input[7:0] RW : 00 0,0Dh PRT3IE Interrupt Enables[7:0] RW : 00 0,0Eh PRT3GS Global Select[7:0] RW : 00 RW : FF 0,0Fh PRT3DM2 Drive Mode 2[7:0] 1,0Ch PRT3DM0 Drive Mode 0[7:0] RW : 00 1,0Dh PRT3DM1 Drive Mode 1[7:0] RW : FF 1,0Eh PRT3IC0 Interrupt Control 0[7:0] RW : 00 1,0Fh PRT3IC1 Interrupt Control 1[7:0] RW : 00 0,10h PRT4DR Data Input[7:0] RW : 00 36 Document No. 38-12012 Rev. *C August 28, 2003 CY8C27xxx Final Data Sheet SECTION B CORE ARCHITECTURE Summary Table of the Core Registers (continued) Address 0,11h Name Bit 7 Bit 6 Bit 5 PRT4IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Enables[7:0] Access RW : 00 0,12h PRT4GS Global Select[7:0] RW : 00 0,13h PRT4DM2 Drive Mode 2[7:0] RW : FF 1,10h PRT4DM0 Drive Mode 0[7:0] RW : 00 1,11h PRT4DM1 Drive Mode 1[7:0] RW : FF 1,12h PRT4IC0 Interrupt Control 0[7:0] RW : 00 1,13h PRT4IC1 Interrupt Control 1[7:0] RW : 00 0,14h PRT5DR Data Input[7:0] RW : 00 0,15h PRT5IE Interrupt Enables[7:0] RW : 00 0,16h PRT5GS Global Select[7:0] RW : 00 RW : FF 0,17h PRT5DM2 Drive Mode 2[7:0] 1,14h PRT5DM0 Drive Mode 0[7:0] RW : 00 1,15h PRT5DM1 Drive Mode 1[7:0] RW : FF 1,16h PRT5IC0 Interrupt Control 0[7:0] RW : 00 1,17h PRT5IC1 Interrupt Control 1[7:0] RW : 00 1,62h ABF_CR0 ANALOG OUTPUT DRIVER REGISTER ACol1Mux Acol2Mux ABUF1EN0 ABUF2EN0 ABUF0EN0 ABUF3EN0 Bypass PWR RW : 00 INTERNAL MAIN OSCILLATOR (IMO) REGISTER 1,E8h IMO_TR 1,E9h Trim[7:0] ILO_TR W : 00 INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER Bias Trim[1:0] Freq Trim[3:0] W : 00 32 kHz CRYSTAL OSCILLATOR (ECO) REGISTER 1,E0h OSC_CR0 1,EBh ECO_TR x,FEh OSC_CR0 PLL Mode No Buzz Sleep[1:0] CPU_SCR1 1,E0h 32k Select CPU Speed[2:0] RW : 00 PSSDC[1:0] W : 00 ECO_EXW ECO_EX IRAMDIS RW : 00 PHASE LOCKED LOOP (PLL) REGISTERS 1,E2h OSC_CR2 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 EXTCLKEN PLLGAIN IMODIS SYSCLKX2 DIS Analog 1 Analog 0 V Monitor RW : 00 IRAMDIS RW : 00 RW : 00 SLEEP AND WATCHDOG REGISTERS 0,E0h INT_MSK0 0,E3h RES_WDT x,FEh CPU_SCR1 1,E0h OSC_CR0 1,E9h ECO_TR x,FFh CPU_SCR0 Sleep GPIO Analog 3 Analog 2 WDSL_Clear[7:0] ECO EXW ILO_TR 1,EBh VC3 32k Select PLL Mode No Buzz Sleep[1:0] Bias Trim[1:0] W : 00 ECO EX CPU Speed[2:0] RW : 00 Freq Trim[3:0] W : 00 PSSDC[1:0] GIES W : 00 WDRS PORS Sleep STOP RW : XX LEGEND L: The AND, OR, and XOR flag instructions can be used to modify this register. #: Access is bit specific. Refer to register detail for additional information. X: The value for power on reset is unknown. x: An "x" before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. August 28, 2003 Document No. 38-12012 Rev. *C 37 SECTION B CORE ARCHITECTURE 38 CY8C27xxx Final Data Sheet Document No. 38-12012 Rev. *C August 28, 2003 3. CPU Core (M8C) This chapter explains the CPU Core, called M8C, and its associated registers. It covers the internal M8C registers, address spaces, instruction formats, and addressing modes. For additional information concerning the M8C instruction set, reference the Assembly Language User Guide available at the CypressMicro.com web site. Table 3-1. M8C Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Carry Zero GIE RL : 00 STOP RW : 17 M8C Register x,F7h CPU_F XOI Related Registers 1,E0h OSC_CR0 x,FF CPU_SCR0 32k Select PLL Mode GIES No Buzz WDRS Sleep[1:0] PORS CPU Speed[2:0] Sleep RW : 00 LEGEND L: The AND, OR, and XOR flag instructions can be used to modify this register. x: An "x" before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. Code selectable processor clock speeds from 93.7 kHz to 24 MHz allow the M8C to be tuned to a particular application's performance and power requirements. The M8C supports a rich instruction set which allows for efficient low-level language support. With the exception of the F register, the M8C internal registers are not accessible via an explicit register address. The internal M8C registers are accessed using instructions such as: 3.1 Internal Registers The M8C has five internal registers that are used in program execution. The following is a list of these registers. Accumulator (A) Index (X) Program Counter (PC) ­ internal use only Stack Pointer (SP) Flags (F) The F register may be read by using address F7h in either register bank. 3.2 All of the internal M8C registers are eight bits in width except for the PC which is 16 bits wide. Upon reset, A, X, PC, and SP are reset to 00h. The Flag register (F) is reset to 02h, indicating that the Z flag is set. With each stack operation, the SP is automatically incremented or decremented so that it always points to the next stack byte in RAM. If the last byte in the stack is at address FFh the Stack Pointer will wrap to RAM address 00h. It is the firmware developer's responsibility to ensure that the stack does not overlap with user-defined variables in RAM. August 28, 2003 MOV A, expr MOV X, expr SWAP A, SP OR F, expr JMP LABEL Address Spaces The M8C has three address spaces: ROM, RAM, and registers. The ROM address space includes the supervisory ROM (SROM) and the Flash. The ROM address space is accessed via its own address and data bus. Figure 3-1 illustrates the arrangement of the PSoC microcontroller address spaces. The ROM address space is composed of the Supervisory ROM and the on-chip Flash program store. Flash is organized into 64-byte blocks. The user need not be concerned with program store page boundaries, as the M8C automatically increments the 16-bit PC on every instruction making the block boundaries invisible to user code. Instructions occurring on a 256-byte Flash page boundary (with the Document No. 38-12012 Rev. *C 39 CPU Core (M8C) CY8C27xxx Final Data Sheet bit