CY8C24094 CY8C24794 CY8C24894 CY8C24994 DBB00 DBB01 DCB02 DCB03 ASD20 DBB00DR0 - Datasheet Archive

 

CY8C24894, CY8C24994 PSoC® Programmable System-on-ChipTM 1. Features Powerful Harvard Architecture Processor M8C Processor

 

CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 PSoC® Programmable System-on-ChipTM 1. Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Two 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3V to 5.25V Operating Voltage Industrial Temperature Range: -40°C to +85°C USB Temperature Range: -10°C to +85°C Programmable Pin Configurations 25 mA Sink, 10 mA Drive on all GPI/O Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPI/O Up to 48 Analog Inputs on GPI/O Two 33 mA Analog Outputs on GPI/O Configurable Interrupt on all GPI/O Precision, Programmable Clocking Internal ±4% 24 and 48 MHz Oscillator Internal Oscillator for Watchdog and Sleep 0.25% Accuracy for USB with no External Components Additional System Resources 2 I C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User Configurable Low Voltage Detection XRES Pin to Support In-System Serial Programming (ISSP) and External Reset Control in CY8C24894 CY8C24894 Flexible On-Chip Memory 16K Flash Program Storage 50,000 Erase and Write Cycles 1K SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Full Speed USB (12 Mbps) Four Uni-Directional Endpoints One Bi-Directional Control Endpoint USB 2.0 Compliant Dedicated 256 Byte Buffer No External Crystal Required Advanced Peripherals (PSoC® Blocks) 6 Rail-to-Rail Analog PSoC Blocks Provide: · Up to 14-Bit ADCs · Up to 9-Bit DACs · Programmable Gain Amplifiers · Programmable Filters and Comparators Four Digital PSoC Blocks Provide: · 8 to 32-Bit Timers, Counters, and PWMs · CRC and PRS Modules · Full-Duplex UART · Multiple SPITM Masters or Slaves · Connectable to all GPI/O Pins Complex Peripherals by Combining Blocks Capacitive Sensing Application Capability 2. Logic Block Diagram P o rt 5 System Bus P o rt 7 P o rt 4 P o rt 3 G lo b a l D ig ita l In t e r c o n n e c t P o rt 2 P o rt 1 P o rt 0 A n a lo g D r iv e r s G lo b a l A n a lo g In te r c o n n e c t PSoC C O R E SR AM 1K SR O M F la s h 1 6 K S le e p a n d W a tc h d o g C P U C o re (M 8 C ) In te rru p t C o n tr o lle r C lo c k S o u r c e s ( I n c lu d e s IM O a n d I L O ) D IG IT A L S Y S TEM A N A LO G SYSTEM A n a lo g R e f. D ig ita l B lo c k A rra y D ig ita l C lo c k s 2 M AC s D e c im a to r Type 2 A n a lo g B lo c k A rra y I2 C PO R and LVD S y s te m R e s e ts In te rn a l V o lta g e R e f. U S B A n a lo g In p u t M u x in g SY S TE M R E S O U R C E S Cypress Semiconductor Corporation Document Number: 38-12018 Rev. *O · 198 Champion Court · San Jose, CA 95134-1709 · 408-943-2600 Revised June 11, 2009 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 The PSoC family consists of many programmable system-on-chips with On-Chip Controller devices. All PSoC family devices are designed to replace traditional MCUs, system ICs, and the numerous discrete components that surround them. The PSoC CY8C24x94 devices are unique members of the PSoC family because it includes a full featured, full speed (12 Mbps) USB port. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of industrial, consumer, and communication applications. 2.2 The Digital System The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 2-1. Digital System Block Diagram Port 7 This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 8% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. In USB systems, the IMO self tunes to ± 0.25% accuracy for USB communication. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin is also capable of generating a system interrupt on high level, low level, and change from last read. Document Number: 38-12018 Rev. *O To System Bus Port 0 To Analog System DIGITAL SYSTEM 8 8 Row 0 DBB00 DBB00 DBB01 DBB01 DCB02 DCB02 4 DCB03 DCB03 4 GIE[7:0] GIO[7:0] Global Digital Interconnect 8 Row Output Configuration Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. Port 1 Port 2 Digital PSoC Block Array 2.1 The PSoC Core The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Port 3 Digital Clocks From Core The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources including a full speed USB port. Configurable global busing enables all the device resources to be combined into a complete custom system. The PSoC CY8C24x94 devices can have up to seven I/O ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks. The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPI/O (General Purpose I/O). Port 5 Port 4 Row Input Configuration 2. PSoC Functional Overview 8 GOE[7:0] GOO[7:0] Digital peripheral configurations include the following: Full Speed USB (12 Mbps) PWMs (8 to 32 bit) PWMs with Dead band (8 to 24 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks are connected to any GPI/O through a series of global buses that can route any signal to any pin. The buses also enable signal multiplexing and performing logic operations. This configurability frees the designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This enables you the optimum choice of system resources for your application. Family resources are shown in Table 2-1 on page 4. Page 2 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 Figure 2-2. Analog System Block Diagram The Analog System is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are as follows. P 0 [5 ] Instrumentation amplifiers (1 with selectable gain to 93x) DACs (up to 2, with 6- to 9-bit resolution) Multiplying DACs (up to 2, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a PSoC Core Resource) 1.3V reference (as a System Resource) DTMF Dialer P 2 [6 ] Comparators (up to 2, with 16 selectable thresholds) P 0 [0 ] P 2 [3 ] Amplifiers (up to 2, with selectable gain to 48x) P 0 [2 ] P 0 [1 ] Filters (2 and 4 pole band-pass, low-pass, and notch) P 0 [4 ] P 0 [3 ] Analog-to-digital converters (up to 2, with 6 to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) P 0 [6 ] AGNDIn RefIn P 0 [7 ] Analog A ll IO (E x c e p t P o r t 7 ) Mux Bus 2.3 The Analog System P 2 [1 ] P 2 [4 ] P 2 [2 ] P 2 [0 ] A C I 0 [1 :0 ] A C I 1 [1 :0 ] A r r a y In p u t C o n f ig u r a t io n B lo c k A rray AC B00 A C B 01 Modulators A SC 10 A SD 11 Correlators ASD20 ASD20 A SC 21 Peak Detectors Many other topologies possible A n a lo g R e f e r e n c e Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in Figure 2-2. In t e r f a c e t o D ig it a l S y s t e m R e fH i R e fL o AGND R e fe r e n c e G e n e ra to rs A G N D In R e fIn B andgap M 8 C In t e r f a c e ( A d d r e s s B u s , D a t a B u s , E t c .) 2.3.1 The Analog Multiplexer System The Analog Mux Bus can connect to every GPI/O pin in ports 0-5. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It is split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: Track pad, finger sensing. Chip-wide mux that enables analog input from up to 48 I/O pins. Crosspoint connection between any I/O pin combinations. When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, which are found under http://www.cypress.com > Design Resources > Application Notes. In general, and unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1. Document Number: 38-12018 Rev. *O Page 3 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 3. Getting Started 2.4 Additional System Resources System Resources, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow. Full Speed USB (12 Mbps) with 5 configurable endpoints and 256 bytes of RAM. No external components required except two series resistors. Wider than commercial temperature USB operation (-10°C to +85°C). Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers. Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. Decimator provides a custom hardware filter for digital signal processing applications including creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, multi-master are supported. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. Versatile analog multiplexer system. 2.5 PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this data sheet is shown in the highlighted row of the table Digital I/O Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAM Size Flash Size Table 2-1. PSoC Device Characteristics CY8C29x66 up to 64 4 16 12 4 4 12 2K 32K CY8C27x43 up to 44 2 8 12 4 4 12 256 Bytes 16K CY8C24x94 56 1 4 48 2 2 6 1K 16K CY8C24x23A up to 24 1 4 12 2 2 6 256 Bytes up to 28 1 4 28 0 2 4 512 Bytes 16 1 4 8 0 2 4 256 Bytes up to 28 0 0 28 0 0 3 512 Bytes 3.1 Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab. 3.2 Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. 3.3 Training Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. 3.4 CyPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. 3.5 Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. 4K CY8C20x34 For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc. 8K CY8C21x23 For in depth information, along with detailed programming information, see the PSoC® Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. 4K CY8C21x34 The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. 8K PSoC Part Number Document Number: 38-12018 Rev. *O 3.6 Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Page 4 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 4. Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. 4.1 PSoC Designer Software Subsystems 4.1.1 System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. 4.1.2 Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration enables changing configurations at run time. 4.1.3 Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. Document Number: 38-12018 Rev. *O 4.1.4 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 4.1.5 Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. 4.1.6 Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. 4.2 In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Page 5 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 5. Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug 5.3 Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer's output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. 5.1 Select Components 5.4 Generate, Verify, and Debug Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called "drivers" and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. In the chip-level view, the components are called "user modules". User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. 5.2 Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. Document Number: 38-12018 Rev. *O Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Page 6 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 6. Document Conventions 6.2 Units of Measure 6.1 Acronyms Used A units of measure table is located in the Electrical Specifications section. Table 9-1 on page 20 lists all the abbreviations used to measure the PSoC devices. The following table lists the acronyms that are used in this document. Acronym Description AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory FSR full scale range GPI/O general purpose I/O GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator I/O input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC® Programmable System-on-ChipTM PWM pulse width modulator SC switched capacitor SRAM Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. continuous time DAC 6.3 Numeric Naming static random access memory Document Number: 38-12018 Rev. *O Page 7 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 7. Pin Information This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration. The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin (labeled with a "P") is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O. Note CY8C24794 CY8C24794 must use Power Cycle programming when using the MiniProg. 7.1 56-Pin Part Pinout Table 7-1. 56-Pin Part Pinout (QFN[2]) See LEGEND details and footnotes in Table 7-2 on page 9. P2[4],M 44 43 46 45 QFN P7[0] 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P2[2], A, I, M P2[0], A, I, M P4[6], M P4[4], M P4[2], M P4[0], M P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M M, I2C SDA, P1[0] M,P1[2] EXTCLK, M,P1[4] M, P1[6] M,P1[3] M, I2C SCL, P1[1] Vss D+ DVdd P7[7] 21 22 23 24 (Top V ie w ) 15 16 17 18 19 20 M, I2C SCL, P1[7] M, I2C SDA, P1[5] Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6],M P0[7], A, I, M Vss 51 50 49 48 47 56 55 54 53 52 P0[5], A, IO, M CY8C24794 CY8C24794 56-Pin PSoC Device P2[5],M P2[7],M P0[1], A, I, M P0[3], A, IO, M Type Pin Figure 7-1. Description No. Digital Analog Name 1 I/O I, M P2[3] Direct switched capacitor block input. 2 I/O I, M P2[1] Direct switched capacitor block input. 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] A, I, M , P2[3] 1 6 I/O M P4[1] A, I, M , P2[1] 2 7 I/O M P3[7] M , P4[7] 3 8 I/O M P3[5] M , P4[5] 4 9 I/O M P3[3] M , P4[3] 5 10 I/O M P3[1] M , P4[1] 6 M , P3[7] 7 11 I/O M P5[7] M , P3[5] 8 12 I/O M P5[5] M , P3[3] 9 13 I/O M P5[3] M , P3[1] 10 14 I/O M P5[1] M , P5[7] 11 15 I/O M P1[7] I2C Serial Clock (SCL). M , P5[5] 12 M , P5[3] 13 16 I/O M P1[5] I2C Serial Data (SDA). M , P5[1] 14 17 I/O M P1[3] 18 I/O M P1[1] I2C Serial Clock (SCL), ISSP SCLK[1]. 19 Power Vss Ground connection. 20 USB D+ 21 USB D22 Power Vdd Supply voltage. 23 I/O P7[7] 24 I/O P7[0] 25 I/O M P1[0] I2C Serial Data (SDA), ISSP SDATA[1]. 26 I/O M P1[2] 27 I/O M P1[4] Optional External Clock Input (EXTCLK). 28 I/O M P1[6] 29 I/O M P5[0] Type Pin No. Digital Analog Name 30 I/O M P5[2] Description 31 I/O M P5[4] 44 I/O M P2[6] External Voltage Reference (VREF) input. 32 I/O M P5[6] 45 I/O I, M P0[0] Analog column mux input. 33 I/O M P3[0] 46 I/O I, M P0[2] Analog column mux input. 34 I/O M P3[2] 47 I/O I, M P0[4] Analog column mux input VREF. 35 I/O M P3[4] 48 I/O I, M P0[6] Analog column mux input. 36 I/O M P3[6] 49 Power Vdd Supply voltage. 37 I/O M P4[0] 50 Power Vss 38 I/O M P4[2] 51 I/O I, M P0[7] Analog column mux input,. 39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog column mux input and column output. 40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog column mux input and column output. 41 I/O I, M P2[0] Direct switched capacitor block input. 54 I/O I, M P0[1] Analog column mux input. 42 I/O I, M P2[2] Direct switched capacitor block input. 55 I/O M P2[7] 43 I/O M P2[4] External Analog Ground (AGND) input. 56 I/O M P2[5] Document Number: 38-12018 Rev. *O Ground connectI/On. Page 8 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 7.2 56-Pin Part Pinout (with XRES) Table 7-2. 56-Pin Part Pinout (QFN[2]) I, I, I, I, A, A, A, A, M M I, M IO, M IO, M I, M 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 QFN (Top View) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0], A, I, M A, I, M M M M M M M M M M M M M, I2C SCL, M, I2C SDA, M, M, I2C SCL, P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[0] M, I2C SDA, P1[0] M, P1[2] EXTCLK, M, P1[4] M, P1[6] A, I, M, A, I, M, M, M, M, M, M, M, M, M, M, M, M, M, 56 55 54 53 52 51 50 49 P2[5], P2[7], P0[1], P0[3], P0[5], P0[7], Vss Vdd P0[6], P0[4], P0[2], P0[0], P2[6], P2[4], M M A, A, A, A, M M M M Figure 7-2. CY8C24894 CY8C24894 56-Pin PSoC Device Type Pin Description No. Digital Analog Name 1 I/O I, M P2[3] Direct switched capacitor block input. 2 I/O I, M P2[1] Direct switched capacitor block input. 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] 6 I/O M P4[1] 7 I/O M P3[7] 8 I/O M P3[5] 9 I/O M P3[3] 10 I/O M P3[1] 11 I/O M P5[7] 12 I/O M P5[5] 13 I/O M P5[3] 14 I/O M P5[1] 15 I/O M P1[7] I2C Serial Clock (SCL). 16 I/O M P1[5] I2C Serial Data (SDA). 17 I/O M P1[3] 18 I/O M P1[1] I2C Serial Clock (SCL), ISSP SCLK[1]. 19 Power Vss Ground connection. 20 USB D+ 21 USB D22 Power Vdd Supply voltage. 23 I/O P7[7] 24 I/O P7[0] 25 I/O M P1[0] I2C Serial Data (SDA), ISSP SDATA[1]. 26 I/O M P1[2] 27 I/O M P1[4] Optional External Clock Input (EXTCLK). 28 I/O M P1[6] 29 I/O M P5[0] 30 I/O M P5[2] Type Pin No. Digital Analog Name 31 I/O M P5[4] 44 I/O M P2[6] External Voltage Reference (VREF) input. 32 I/O M P5[6] 45 I/O I, M P0[0] Analog column mux input. 33 I/O M P3[0] 46 I/O I, M P0[2] Analog column mux input. 34 I/O M P3[2] 47 I/O I, M P0[4] Analog column mux input VREF. 35 I/O M P3[4] 48 I/O I, M P0[6] Analog column mux input. 49 Vdd Supply voltage. 36 Input 37 I/O M XRES Active high external reset with internal pull down. P4[0] 38 I/O M P4[2] 51 I/O I, M P0[7] Analog column mux input,. 39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog column mux input and column output. 40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog column mux input and column output. 41 I/O I, M P2[0] Direct switched capacitor block input. 54 I/O I, M P0[1] Analog column mux input. 42 I/O I, M P2[2] Direct switched capacitor block input. 55 I/O M P2[7] 43 I/O M P2[4] External Analog Ground (AGND) input. 56 I/O M P2[5] 50 Power Description Power Vss Ground connection. LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Notes 1. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details. 2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 38-12018 Rev. *O Page 9 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 7.3 68-Pin Part Pinout The following 68-pin QFN part table and drawing is for the CY8C24994 CY8C24994 PSoC device. Table 7-3. 68-Pin Part Pinout (QFN[2]) M M M P4[0] P4[2] P4[4] P2[6], M, Ext. VREF P2[4], M, Ext. AGND P2[2], M, AI 53 52 P0[2], M, AI P0[0], M, AI 55 54 58 57 56 P0[7], M, AI Vss Vdd P0[6], M, AI P0[4], M, AI P0[1], M, AI P0[3], M, AIO P0[5], M, AIO 63 62 61 60 59 64 P2[3], M, AI P2[5], M P2[7], M P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] 63 64 65 I/O I/O I/O I/O,M I,M M P0[3] P0[1] P2[7] 66 67 68 I/O I/O I/O M I,M I,M P2[5] P2[3] P2[1] 50 51 52 Optional External Clock Input (EXTCLK). 53 54 55 56 57 58 59 60 61 62 I2C Serial Data (SDA), ISSP SDATA[1]. No connection. No connection. Active high pin reset with internal pull down. 66 65 Type Digital Analog I/O M I/O I,M I/O I,M I/O M I/O M I/O I,M I/O I,M I/O I,M I/O I,M Power Power I/O I,M I/O I/O,M Pin No. Name 31 32 33 34 38 37 36 35 P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES NC NC P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M EXTCLK, M, P1[4] Supply voltage. I2C SDA, M, P1[0] M, P1[2] I2C Serial Clock (SCL) ISSP SCLK[1]. Ground connection. QFN (Top View) 28 29 30 I2C Serial Clock (SCL). I2C Serial Data (SDA). 49 48 47 46 45 44 43 42 41 40 39 P7[3] P7[2] P7[1] P7[0] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1] I2C SCL, M, P1[7] I2C SDA, M, P1[5] 51 50 24 25 26 27 M, P4[1] NC NC Vss M, P3[7] M, P3[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 P7[7] P7[6] P7[5] P7[4] M, P4[7] M, P4[5] M, P4[3] 20 21 22 23 I/O I/O I/O P2[1], M, AI 47 48 49 68 67 Input NC NC XRES No connection. No connection. Ground connection. 18 19 44 45 46 Figure 7-3. CY8C24994 CY8C24994 68-Pin PSoC Device Description M, P1[3] P4[7] P4[5] P4[3] P4[1] NC NC Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] Name I2C SCL, M, P1[1] Vss D+ DVdd Type Pin No. Digital Analog 1 I/O M 2 I/O M 3 I/O M 4 I/O M 5 6 7 Power 8 I/O M 9 I/O M 10 I/O M 11 I/O M 12 I/O M 13 I/O M 14 I/O M 15 I/O M 16 I/O M 17 I/O M 18 I/O M 19 I/O M 20 Power 21 USB 22 USB 23 Power 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O M 33 I/O M 34 I/O M 35 I/O M 36 I/O M 37 I/O M 38 I/O M 39 I/O M 40 I/O M 41 I/O M 42 I/O M 43 I/O M Description Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Ground connection. Analog column mux input, integration input #1 Analog column mux input and column output, integration input #2. Analog column mux input and column output. Analog column mux input. Direct switched capacitor block input. Direct switched capacitor block input. LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input. Document Number: 38-12018 Rev. *O Page 10 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 7.4 68-Pin Part Pinout (On-Chip Debug) The following 68-pin QFN part table and drawing is for the CY8C24094 CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7-4. 68-Pin Part Pinout (QFN[2]) Type Pin No. Digital Analog 50 I/O M I2C Serial Data (SDA), ISSP SDATA[1]. 51 I/O I,M 52 I/O I,M Optional External Clock Input (EXTCLK). 53 I/O M 54 I/O M 55 I/O I,M 56 I/O I,M 57 I/O I,M 58 I/O I,M 59 Power 60 Power 61 I/O I,M 62 I/O I/O,M I/O I/O I/O P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] P0[3] P0[1] P2[7] 47 I/O M P4[0] 66 I/O M 48 I/O M P4[2] 67 I/O I,M 49 I/O M P4[4] 68 I/O I,M LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger. P2[5] P2[3] P2[1] Document Number: 38-12018 Rev. *O 63 64 65 Name I/O,M I,M M Input P2[6], M, Ext. VREF P2[4], M, Ext. AGND P2[2], M, AI I2C SDA, M, P1[0] M, P1[2] EXTCLK M, P1[4] 28 29 30 31 32 33 34 P7[3] P7[2] P7[1] P7[0] 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M , 55 54 53 52 58 57 56 P0[7], M, AI Vss Vdd P0[6], M, AI P0[4], M, AI P0[2], M, AI P0[0], M, AI 64 63 62 61 60 59 P2[3], M, AI P2[5], M P2[7], M P0[1], M, AI P0[3], M, AIO P0[5], M, AIO QFN (Top View) P7[7] P7[6] P7[5] P7[4] Supply voltage. OCD high speed clock output. OCD CPU clock output. Active high pin reset with internal pull down. 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 27 I2C Serial Clock (SCL), ISSP SCLK[1]. Ground connection. M, P4[7] M, P4[5] M, P4[3] M, P4[1] OCDE OCDO Vss M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1] I2C SCL, M, P1[7] I2C SDA, M, P1[5] 20 21 22 I2C Serial Clock (SCL). I2C Serial Data (SDA). P2[1], M, AI HCLK CCLK XRES OCD even data I/O. OCD odd data output. Ground connection. 68 67 44 45 46 Figure 7-4. CY8C24094 CY8C24094 68-Pin OCD PSoC Device Description 18 19 P4[7] P4[5] P4[3] P4[1] OCDE OCDO Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] Name M, P1[3] I2C SCL, M, P1[1] Vss D+ DVdd Type Pin No. Digital Analog 1 I/O M 2 I/O M 3 I/O M 4 I/O M 5 6 7 Power 8 I/O M 9 I/O M 10 I/O M 11 I/O M 12 I/O M 13 I/O M 14 I/O M 15 I/O M 16 I/O M 17 I/O M 18 I/O M 19 I/O M 20 Power 21 USB 22 USB 23 Power 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O M 33 I/O M 34 I/O M 35 I/O M 36 I/O M 37 I/O M 38 I/O M 39 I/O M 40 I/O M 41 I/O M 42 I/O M 43 I/O M Description Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Ground connection. Analog column mux input, integration input #1 Analog column mux input and column output, integration input #2. Analog column mux input and column output. Analog column mux input. Direct switched capacitor block input. Direct switched capacitor block input. Page 11 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 7.5 100-Ball VFBGA Part Pinout The 100-ball VFBGA part is for the CY8C24994 CY8C24994 PSoC device. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Power Power Vss Vss NC NC NC Power Vdd NC NC Power Vss Power Vss Power Vss Power Vss I/O I,M P2[1] I/O I,M P0[1] I/O I,M P0[7] Power Vdd I/O I,M P0[2] I/O I,M P2[2] Power Vss Power Vss NC I/O M P4[1] I/O M P4[7] I/O M P2[7] I/O I/O,M P0[5] I/O I,M P0[6] I/O I,M P0[0] I/O I,M P2[0] I/O M P4[2] NC NC I/O M P3[7] I/O M P4[5] I/O M P2[5] I/O I/O,M P0[3] I/O I,M P0[4] I/O M P2[6] I/O M P4[6] I/O M P4[0] NC NC NC I/O M P4[3] I/O I,M P2[3] Power Vss Power Vss I/O M P2[4] I/O M P4[4] I/O M P3[6] NC Description Ground connection. Ground connection. No connection. No connection. No connection. Supply voltage. No connection. No connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Direct switched capacitor block input. Ground connection. Ground connection. No connection. Pin No. F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 Analog column mux input and column output. H5 Analog column mux input. H6 Analog column mux input. H7 Direct switched capacitor block input. H8 H9 No connection. H10 No connection. J1 J2 J3 J4 Analog column mux input and column output. J5 Analog column mux input. J6 External Voltage Reference (VREF) input. J7 J8 J9 No connection. J10 No connection. K1 No connection. K2 K3 Direct switched capacitor block input. K4 Ground connection. K5 Ground connection. K6 External Analog Ground (AGND) input. K7 K8 K9 No connection. K10 Analog Name Digital Analog Pin No. Digital Table 7-5. 100-Ball Part Pinout (VFBGA) I/O M I/O M I/O M Power Power I/O M I/O M I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M M M M M I/O M I/O M I/O M I/O M I/O M I/O M I/O M I/O M I/O Power Power USB USB Power I/O I/O I/O M Power Power Power Power Power I/O I/O I/O Power Power Name NC P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1] NC P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] Vss Vss D+ DVdd P7[7] P7[0] P5[2] Vss Vss Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss Description No connection. Ground connection. Ground connection. Active high pin reset with internal pull down. No connection. I2C Serial Clock (SCL). I2C Serial Clock (SCL), ISSP SCLK[1]. I2C Serial Data (SDA), ISSP SDATA[1]. No connection. I2C Serial Data (SDA). Optional External Clock Input (EXTCLK). Ground connection. Ground connection. Supply voltage. Ground connection. Ground connection. Ground connection. Ground connection. No connection. No connection. Supply voltage. Ground connection. Ground connection. LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection. Document Number: 38-12018 Rev. *O Page 12 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 Figure 7-5. CY8C24094 CY8C24094 OCD (Not for Production) 1 2 3 4 5 6 7 8 9 10 A Vss Vss NC NC NC Vdd NC NC Vss Vss B Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss C NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2] NC D NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] NC E NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] NC F NC P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1] G NC P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] H NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] J Vss Vss D+ D- Vdd P7[7] P7[0] P5[2] Vss Vss K Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss BGA (Top View) 7.6 100-Ball VFBGA Part Pinout (On-Chip Debug) The following 100-pin VFBGA part table and drawing is for the CY8C24094 CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 Power Power C6 C7 I/O I/O Power Power Power Power Power I/O I,M I/O I,M I/O I,M Power I/O I,M I/O I,M Power Power I/O I/O I/O I/O M M M I/O, M I,M I,M Description Vss Vss NC NC NC Vdd NC NC Vss Vss Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss NC P4[1] P4[7] P2[7] P0[5] Ground connection. Ground connection. No connection. No connection. No connection. Supply voltage. No connection. No connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Direct switched capacitor block input. Ground connection. Ground connection. No connection. P0[6] P0[0] Analog column mux input. Analog column mux input. Pin No. F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 Analog column mux input and column output. H5 Document Number: 38-12018 Rev. *O H6 H7 Analog Name Digital Digital Pin No. Analog Table 7-6. 100-Ball Part Pinout (VFBGA) Name I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M M M M M I/O I/O I/O I/O M M M M OCDE P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1] OCDO P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] NC P5[3] P3[1] P1[5] P1[3] I/O I/O M M P1[2] P1[4] I/O M I/O M I/O M Power Power I/O M I/O M I/O Description OCD even data I/O. Ground connection. Ground connection. Active high pin reset with internal pull down. OCD odd data output. I2C Serial Clock (SCL). I2C Serial Clock (SCL), ISSP SCLK[1]. I2C Serial Data (SDA), ISSP SDATA[1]. No connection. I2C Serial Data (SDA). Optional External Clock Input (EXTCLK). Page 13 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 Table 7-6. 100-Ball Part Pinout (VFBGA) (continued) C8 C9 C10 D1 D2 D3 D4 D5 I/O I/O I,M M I/O I/O I/O I/O D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 I/O I/O I/O I/O M M M I/O, M I,M M M M I/O M I/O I,M Power Power I/O M I/O M I/O M P2[0] P4[2] NC NC P3[7] P4[5] P2[5] P0[3] Direct switched capacitor block input. H8 H9 No connection. H10 No connection. J1 J2 J3 J4 Analog column mux input and column output. J5 I/O M I/O M I/O Power Power USB USB Power P3[2] P5[4] P7[3] Vss Vss D+ DVdd P0[4] P2[6] P4[6] P4[0] CCLK NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] HCLK Analog column mux input. External Voltage Reference (VREF) input. I/O I/O I/O M Power Power Power Power P7[7] P7[0] P5[2] Vss Vss Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 OCD CPU clock output. No connection. No connection. Direct switched capacitor block input. Ground connection. Ground connection. External Analog Ground (AGND) input. OCD high speed clock output. Power I/O I/O I/O Power Power Ground connection. Ground connection. Supply voltage. Ground connection. Ground connection. Ground connection. Ground connection. No connection. No connection. Supply voltage. Ground connection. Ground connection. LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger. Figure 7-6. CY8C24094 CY8C24094 OCD (Not for Production) 1 2 3 4 5 6 7 8 9 10 A Vss Vss NC NC NC Vdd NC NC Vss Vss B Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss C NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2] NC D NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] CClk E NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] HClk F ocde P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1] G ocdo P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] H NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] J Vss Vss D+ D- Vdd P7[7] P7[0] P5[2] Vss Vss K Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss BGA (Top View) Document Number: 38-12018 Rev. *O Page 14 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 7.7 100-Pin Part Pinout (On-Chip Debug) The 100-pin TQFP part is for the CY8C24094 CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 NC NC I/O I, M P0[1] I/O M P2[7] I/O M P2[5] I/O I, M P2[3] I/O I, M P2[1] I/O M P4[7] I/O M P4[5] I/O M P4[3] I/O M P4[1] OCDE OCDO NC Power Vss I/O M P3[7] I/O M P3[5] I/O M P3[3] I/O M P3[1] I/O M P5[7] I/O M P5[5] I/O M P5[3] I/O M P5[1] I/O M P1[7] NC NC NC I/O P1[5] I/O P1[3] I/O P1[1] Power USB USB Power I/O I/O I/O I/O I/O I/O I/O I/O NC Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] NC NC NC NC 48 I/O P1[0] 49 I/O I/O P1[4] No connection. No connection. Analog column mux input. Direct switched capacitor block input. Direct switched capacitor block input. OCD even data I/O. OCD odd data output. No connection. Ground connection. I2C Serial Clock (SCL). No connection. No connection. No connection. I2C Serial Data (SDA) Crystal (XTALin), I2C Serial Clock (SCL), ISSP SCLK[1]. No connection. Ground connection. Supply voltage. No connection. No connection. No connection. No connection. P1[2] 50 Description Crystal (XTALout), I2C Serial Data (SDA), ISSP SDATA[1]. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O I/O I/O I/O I/O I/O I/O I/O I/O 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 I/O I, M Power Document Number: 38-12018 Rev. *O M M M M M M M M M 100 Name Description I/O I/O I I/O I, M I/O I, M Power I/O I, M I/O I/O, M I/O I/O, M P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] Vss P4[4] P4[6] P2[0] P2[2] P2[4] NC P2[6] NC P0[0] NC NC P0[2] NC P0[4] NC Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. No connection. External Voltage Reference (VREF) input. No connection. Analog column mux input. No connection. No connection. Analog column mux input and column output. No connection. Analog column mux input and column output. No connection. P0[6] Vdd NC Vss NC NC NC NC NC NC NC NC NC NC P0[7] NC P0[5] Analog column mux input. Supply voltage. No connection. Ground connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. Analog column mux input. No connection. Analog column mux input and column output. NC Input I/O M I/O M Power I/O M I/O M I/O I, M I/O I, M I/O 98 99 Optional External Clock Input (EXTCLK). Analog Name Digital 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Analog Pin No. Digital Table 7-7. 100-Pin Part Pinout (TQFP) No connection. P0[3] Analog column mux input and column output. NC No connection. OCD high speed clock output. OCD CPU clock output. Active high pin reset with internal pull down. Ground connection. Page 15 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 Table 7-7. 100-Pin Part Pinout (TQFP) (continued) LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger. Document Number: 38-12018 Rev. *O NC P0[2], M, AI NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC P0[0], M , AI NC P2[6], M , External VREF NC P2[4], M , External AGND P2[2], M , AI P2[0], M , AI P4[6], M P4[4], M Vss P4[2], M P4[0], M XRES CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M M, P1[2] EXTCLK, M, P1[4] 46 47 48 49 50 P7[1] P7[0] NC NC NC NC I2C SDA, M, P1[0] P7[3] P7[2] 36 37 38 39 40 41 42 43 44 45 P7[7] P7[6] P7[5] P7[4] 31 32 33 34 35 77 76 80 79 78 NC Vdd P0[6], M, AI NC P0[4], M, AI NC NC Vss 87 86 85 84 83 82 81 90 89 88 NC NC NC NC NC NC NC NC P0[7], M, AI NC 95 94 93 92 91 P0[3], M, AI NC P0[5], M, AI 98 97 96 28 29 30 26 27 TQFP NC I2C SDA, M, P1[5] M, P1[3] I2C SCL, M, P1[1] NC Vss D+ DVdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC AI, M , P0[1] M , P2[7] M , P2[5] AI, M , P2[3] AI, M , P2[1] M , P4[7] M , P4[5] M , P4[3] M , P4[1] OCDE OCDO NC Vss M , P3[7] M , P3[5] M , P3[3] M , P3[1] M , P5[7] M , P5[5] M , P5[3] M , P5[1] I2C SCL, P1[7] NC 100 99 NC Figure 7-7. CY8C24094 CY8C24094 OCD (Not for Production) Page 16 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 8. Register Reference This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual. 8.1 Register Conventions 8.2 Register Mapping Tables The register conventions specific to this section are listed in the following table. The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Note In the following register mapping tables, blank fields are Reserved and should not be accessed. Access is bit specific Document Number: 38-12018 Rev. *O Page 17 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 8.3 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) Access Name 00 RW PMA0_DR 01 RW PMA1_DR 02 RW PMA2_DR 03 RW PMA3_DR 04 RW PMA4_DR 05 RW PMA5_DR 06 RW PMA6_DR 07 RW PMA7_DR 08 RW USB_SOF0 09 RW USB_SOF1 0A RW USB_CR0 0B RW USBI/O_CR0 0C RW USBI/O_CR1 0D RW 0E RW EP1_CNT1 0F RW EP1_CNT 10 RW EP2_CNT1 11 RW EP2_CNT 12 RW EP3_CNT1 13 RW EP3_CNT 14 RW EP4_CNT1 15 RW EP4_CNT 16 RW EP0_CR 17 RW EP0_CNT 18 EP0_DR0 19 EP0_DR1 1A EP0_DR2 1B EP0_DR3 PRT7DR 1C RW EP0_DR4 PRT7IE 1D RW EP0_DR5 PRT7GS 1E RW EP0_DR6 PRT7DM2 1F RW EP0_DR7 DBB00DR0 DBB00DR0 20 # AMX_IN DBB00DR1 DBB00DR1 21 W AMUXCFG DBB00DR2 DBB00DR2 22 RW DBB00CR0 DBB00CR0 23 # ARF_CR DBB01DR0 DBB01DR0 24 # CMP_CR0 DBB01DR1 DBB01DR1 25 W ASY_CR DBB01DR2 DBB01DR2 26 RW CMP_CR1 DBB01CR0 DBB01CR0 27 # DCB02DR0 DCB02DR0 28 # DCB02DR1 DCB02DR1 29 W DCB02DR2 DCB02DR2 2A RW DCB02CR0 DCB02CR0 2B # DCB03DR0 DCB03DR0 2C # TMP_DR0 DCB03DR1 DCB03DR1 2D W TMP_DR1 DCB03DR2 DCB03DR2 2E RW TMP_DR2 DCB03CR0 DCB03CR0 2F # TMP_DR3 30 ACB00CR3 ACB00CR3 31 ACB00CR0 ACB00CR0 32 ACB00CR1 ACB00CR1 33 ACB00CR2 ACB00CR2 34 ACB01CR3 ACB01CR3 35 ACB01CR0 ACB01CR0 36 ACB01CR1 ACB01CR1 37 ACB01CR2 ACB01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and should not be accessed. Document Number: 38-12018 Rev. *O Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW R R RW # RW # RW # RW # RW # RW # # RW RW RW RW RW RW RW RW RW RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR0 ASC10CR1 ASC10CR1 ASC10CR2 ASC10CR2 ASC10CR3 ASC10CR3 ASD11CR0 ASD11CR0 ASD11CR1 ASD11CR1 ASD11CR2 ASD11CR2 ASD11CR3 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 ASD20CR0 90 ASD20CR1 ASD20CR1 91 ASD20CR2 ASD20CR2 92 ASD20CR3 ASD20CR3 93 ASC21CR0 ASC21CR0 94 ASC21CR1 ASC21CR1 95 ASC21CR2 ASC21CR2 96 ASC21CR3 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W W R R RW RW RW RW RW RW RW RW RW RW RW Name CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F DAC_D CPU_SCR1 CPU_SCR0 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL RW # # Page 18 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 8.4 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) Access Name 00 RW PMA0_WA 01 RW PMA1_WA 02 RW PMA2_WA 03 RW PMA3_WA 04 RW PMA4_WA 05 RW PMA5_WA 06 RW PMA6_WA 07 RW PMA7_WA 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW PMA0_RA 11 RW PMA1_RA 12 RW PMA2_RA 13 RW PMA3_RA 14 RW PMA4_RA 15 RW PMA5_RA 16 RW PMA6_RA 17 RW PMA7_RA 18 19 1A 1B PRT7DM0 1C RW PRT7DM1 1D RW PRT7IC0 1E RW PRT7IC1 1F RW DBB00FN DBB00FN 20 RW CLK_CR0 DBB00IN DBB00IN 21 RW CLK_CR1 DBB00OU DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN DBB01FN 24 RW CMP_GO_EN DBB01IN DBB01IN 25 RW DBB01OU DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN DCB02FN 28 RW DCB02IN DCB02IN 29 RW DCB02OU DCB02OU 2A RW 2B DCB03FN DCB03FN 2C RW TMP_DR0 DCB03IN DCB03IN 2D RW TMP_DR1 DCB03OU DCB03OU 2E RW TMP_DR2 2F TMP_DR3 30 ACB00CR3 ACB00CR3 31 ACB00CR0 ACB00CR0 32 ACB00CR1 ACB00CR1 33 ACB00CR2 ACB00CR2 34 ACB01CR3 ACB01CR3 35 ACB01CR0 ACB01CR0 36 ACB01CR1 ACB01CR1 37 ACB01CR2 ACB01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and should not be accessed. Document Number: 38-12018 Rev. *O Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR0 ASC10CR1 ASC10CR1 ASC10CR2 ASC10CR2 ASC10CR3 ASC10CR3 ASD11CR0 ASD11CR0 ASD11CR1 ASD11CR1 ASD11CR2 ASD11CR2 ASD11CR3 ASD11CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 ASD20CR1 ASD20CR1 91 ASD20CR2 ASD20CR2 92 ASD20CR3 ASD20CR3 93 ASC21CR0 ASC21CR0 94 ASC21CR1 ASC21CR1 95 ASC21CR2 ASC21CR2 96 ASC21CR3 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name USBI/O_CR2 USB_CR1 Addr (1,Hex) Access C0 RW C1 # EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW CPU_F DAC_CR CPU_SCR1 CPU_SCR0 # # # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R W W RW W RW RW RL RW # # Page 19 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9. Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. Figure 9-1. Voltage versus CPU Frequency 5.25 Vdd Voltage lid ng Va rati n e io Op Reg 4.75 3.00 93 kHz 12 MHz 24 MHz CPU Frequency The following table lists the units of measure that are used in this chapter. Table 9-1. Units of Measure Symbol oC dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Document Number: 38-12018 Rev. *O Symbol W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Page 20 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.1 Absolute Maximum Ratings Table 9-2. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature Min -55 Typ 25 Max +100 TA Vdd VI/O Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage ­ ­ ­ VI/O2 DC Voltage Applied to Tri-state IMI/O IMAI/O Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss 0.5 Vss 0.5 -25 -50 ­ ­ +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 mA mA 2000 ­ ­ ­ ­ 200 V mA Min -40 -10 -40 Typ ­ ­ ­ Max +85 +85 +100 Units oC oC oC ESD LU ­ Units o C Notes Higher storage temperatures reduces data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC degrades reliability. o C V V V Human Body Model ESD. 9.2 Operating Temperature Table 9-3. Operating Temperature Symbol Description TA Ambient Temperature TAUSB Ambient Temperature using USB TJ Junction Temperature Document Number: 38-12018 Rev. *O Notes The temperature rise from ambient to junction is package specific. See Thermal Impedance on page 41. The user must limit the power consumption to comply with this requirement. Page 21 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.3 DC Electrical Characteristics 9.3.1 DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-4. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage Min 3.0 Typ ­ Max 5.25 Units V IDD5 Supply Current, IMO = 24 MHz (5V) ­ 14 27 mA IDD3 Supply Current, IMO = 24 MHz (3.3V) ­ 8 14 mA ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[3] ­ 3 6.5 A ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[3] ­ 4 25 A Notes See DC POR and LVD specifications, Table 9-14 on page 28. Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC, analog power = off. 9.3.2 DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-5. DC GPI/O Specifications Symbol Description RPU Pull Up Resistor RPD Pull Down Resistor VOH High Output Level VOL Low Output Level VIL VIH VH IIL CIN Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input COUT Capacitive Load on Pins as Output Min 4 4 Vdd - 1.0 Typ 5.6 5.6 ­ Max 8 8 ­ Units k k V ­ ­ 0.75 V ­ 2.1 ­ ­ ­ ­ ­ 60 1 3.5 0.8 ­ ­ 10 V V mV nA pF ­ 3.5 10 pF Notes I/OH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]). 80 mA maximum combined I/OH budget. I/OL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]). 200 mA maximum combined I/OL budget. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Note 3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. Document Number: 38-12018 Rev. *O Page 22 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.3.3 DC Full Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -10°C TA 85°C, or 3.0V to 3.6V and -10°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-6. DC Full Speed (12 Mbps) USB Specifications Symbol Description USB Interface Differential Input Sensitivity VDI Differential Input Common Mode Range VCM VSE Single Ended Receiver Threshold Transceiver Capacitance CIN High-Z State Data Line Leakage II/O REXT External USB Series Resistor Static Output High, Driven VUOH Min Typ Max Units 0.2 0.8 0.8 ­ -10 23 2.8 ­ ­ ­ ­ ­ ­ ­ ­ 2.5 2.0 20 10 25 3.6 V V V pF A W V VUOHI Static Output High, Idle 2.7 ­ 3.6 V VUOL Static Output Low ­ ­ 0.3 V ZO VCRS USB Driver Output Impedance D+/D- Crossover Voltage 28 1.3 ­ ­ 44 2.0 W V Notes | (D+) - (D-) | 0V < VIN < 3.3V. In series with each USB pin. 15 k ± 5% to Ground. Internal pull up enabled. 15 k ± 5% to Ground. Internal pull up enabled. 15 k ± 5% to Ground. Internal pull up enabled. Including REXT Resistor. 9.3.4 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 9-7. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) IEBOA Input Capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) GOLOA Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Document Number: 38-12018 Rev. *O Min Typ Max Units ­ ­ ­ ­ ­ ­ 1.6 1.3 1.2 10 8 7.5 mV mV mV 7.0 20 4.5 35.0 ­ 9.5 V/oC pA pF 0.0 0.5 ­ ­ Vdd Vdd - 0.5 V ­ ­ dB 60 60 80 Notes Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Page 23 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 Table 9-7. 5V DC Operational Amplifier Specifications (continued) Symbol VOHIGHO Description High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High A Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High VOLOWOA Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio Min Typ Max Units Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 ­ ­ ­ ­ ­ ­ V V V ­ ­ ­ ­ ­ ­ 0.2 0.2 0.5 V V V ­ ­ ­ ­ ­ ­ 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 A A A A A A 65 80 ­ dB Notes Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd. 9.3.5 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, 3.0V to 3.6V and -40°C TA 85°C, or 2.4V to 3.0V and -40°C TA 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-8. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Document Number: 38-12018 Rev. *O Min 0.2 Typ ­ Max Vdd - 1 Units V ­ ­ 10 2.5 40 30 Notes A mV Page 24 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.3.6 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-9. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSO Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Min ­ ­ Typ 3 +6 Max 12 ­ Units mV V/°C Common-Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High 0.5 ­ Vdd - 1.0 V ­ ­ 0.6 0.6 ­ ­ W W 0.5 x Vdd + 1.1 0.5 x Vdd + 1.1 ­ ­ ­ ­ V V ­ ­ ­ ­ 0.5 x Vdd 1.3 0.5 x Vdd 1.3 V V ­ ­ 53 1.1 2.6 64 5.1 8.8 ­ mA mA dB Typ 3 +6 - Max 12 ­ Vdd - 1.0 Units mV V/°C V 1 1 ­ ­ W W ­ ­ ­ ­ V V ­ ­ 0.5 x Vdd 1.0 0.5 x Vdd 1.0 V V 0.8 2.0 64 2.0 4.3 ­ mA mA dB Notes B VCMOB ROUTOB VOHIGHO B VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High ISOB PSRROB Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio (0.5 x Vdd - 1.3) VOUT (Vdd - 2.3). Table 9-10. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Min Input Offset Voltage (Absolute Value) ­ Average Input Offset Voltage Drift ­ Common-Mode Input Voltage Range 0.5 Output Resistance Power = Low ­ Power = High ­ VOHIGHO High Output Voltage Swing (Load = 1K ohms to Vdd/2) 0.5 x Vdd + B Power = Low 1.0 Power = High 0.5 x Vdd + 1.0 VOLOWOB Low Output Voltage Swing (Load = 1K ohms ­ to Vdd/2) ­ Power = Low Power = High ISOB PSRROB Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Document Number: 38-12018 Rev. *O ­ 34 Notes (0.5 x Vdd - 1.0) VOUT (0.5 x Vdd + 0.9). Page 25 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.3.7 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 9-11. 5V DC Analog Reference Specifications Symbol BG ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ Description Min Typ Max Bandgap Voltage Reference 1.28 1.30 1.32 AGND = Vdd/2[4, 5] Vdd/2 - 0.04 Vdd/2 - 0.01 Vdd/2 + 0.007 AGND = 2 x BandGap[4, 5] 2 x BG - 0.048 2 x BG - 0.030 2 x BG + 0.024 [4, 5] AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.011 P2[4] P2[4] + 0.011 AGND = BandGap[4, 5] BG - 0.009 BG + 0.008 BG + 0.016 AGND = 1.6 x BandGap[4, 5] 1.6 x BG - 0.022 1.6 x BG - 0.010 1.6 x BG + 0.018 AGND Block to Block Variation (AGND = Vdd/2)[4, 5] -0.034 0.000 0.034 RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 RefHi = 3 x BandGap 3 x BG - 0.06 3 x BG 3 x BG + 0.06 RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] 2 x BG + P2[6] 2 x BG + P2[6] + 0.113 0.018 0.077 RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6]+ 0.133 0.016 0.100 RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 RefLo = Vdd/2 ­ BandGap Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04 RefLo = BandGap BG - 0.06 BG BG + 0.06 RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] 2 x BG - P2[6] + 2 x BG - P2[6] + 0.084 0.025 0.134 RefLo = P2[4] ­ BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] P2[4] - P2[6] + P2[4] - P2[6] + 0.057 0.026 0.110 Units V V V V V V V V V V V V V V V V V V Table 9-12. 3.3V DC Analog Reference Specifications Symbol BG ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ Description Bandgap Voltage Reference AGND = Vdd/2[4, 5] AGND = 2 x BandGap[4, 5] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[4, 5] AGND = 1.6 x BandGap[4, 5] AGND Column to Column Variation (AGND = Vdd/2)[4, 5] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Document Number: 38-12018 Rev. *O Min 1.28 Vdd/2 - 0.03 P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.027 -0.034 P2[4] + P2[6] 0.075 Typ Max 1.30 1.32 Vdd/2 - 0.01 Vdd/2 + 0.005 Not Allowed P2[4] + 0.001 P2[4] + 0.009 BG + 0.005 BG + 0.015 1.6 x BG - 0.010 1.6 x BG + 0.018 0.000 0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.009 P2[4] + P2[6] + 0.057 Units V V V V V V V Page 26 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 Table 9-12. 3.3V DC Analog Reference Specifications (continued) Symbol ­ ­ ­ ­ ­ ­ Description Min RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] ­ BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 Typ Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4]- P2[6] + 0.022 Max Units P2[4] - P2[6] + 0.092 V 9.3.8 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-13. DC Analog PSoC Block Specifications Symbol Description RCT Resistor Unit Value (Continuous Time) CSC Capacitor Unit Value (Switched Capacitor) Min ­ ­ Typ 12.2 80 Max ­ ­ Units k fF Notes Note 4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V. 5. Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Document Number: 38-12018 Rev. *O Page 27 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.3.9 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip Technical Reference Manual for more information on the VLT_CR register. Table 9-14. DC POR and LVD Specifications Symbol Description VPPOR0R VPPOR1R VPPOR2R Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Units ­ 2.91 4.39 4.55 ­ V V V ­ 2.82 4.39 4.55 ­ V V V ­ ­ ­ 92 0 0 ­ ­ ­ mV mV mV 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98[6] 3.08 3.20 4.08 4.57 4.74[7] 4.82 4.91 V V V V V V V V V PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Max Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VPH0 VPH1 VPH2 Typ Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VPPOR0 VPPOR1 VPPOR2 Min Notes Notes 6. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 7. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 38-12018 Rev. *O Page 28 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.3.10 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-15. DC Programming Specifications Symbol IDDP VILP Description Min Supply Current During Programming or Verify ­ Input Low Voltage During Programming or ­ Verify VIHP Input High Voltage During Programming or 2.1 Verify IILP Input Current when Applying Vilp to P1[0] or ­ P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or ­ P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or ­ Verify VOHV Output High Voltage During Programming or Vdd - 1.0 Verify FlashENP Flash Endurance (per block) 50,000 Typ 15 ­ Max 30 0.8 Units mA V Notes ­ ­ V ­ 0.2 mA ­ 1.5 mA ­ V ­ Vss + 0.75 Vdd ­ ­ ­ Erase/write cycles per block. ­ ­ ­ Erase/write cycles. ­ ­ Years Driving internal pull down resistor. Driving internal pull down resistor. V B FlashENT Flash Endurance (total)[8] FlashDR Flash Data Retention 1,800,0 00 10 Note 8. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 38-12018 Rev. *O Page 29 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.4 AC Electrical Characteristics 9.4.1 AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-16. AC Chip-Level Specifications Symbol FIMO245V FIMO245V Description Internal Main Oscillator Frequency for 24 MHz (5V) FIMO243V FIMO243V Internal Main Oscillator Frequency for 24 MHz (3.3V) FIMOUSB5 Internal Main Oscillator Frequency with USB (5V) V Frequency locking enabled and USB traffic present. FIMOUSB3 Internal Main Oscillator Frequency with USB (3.3V) V Frequency locking enabled and USB traffic present. FCPU1 CPU Frequency (5V Nominal) FCPU2 CPU Frequency (3.3V Nominal) FBLK5 Digital PSoC Block Frequency (5V Nominal) Min 23.04 Typ 24 Max 24.96[9,10] Units MHz 22.08 24 25.92[10,11] MHz 23.94 24 24.06[10] MHz 23.94 24 24.06[10] MHz 0.93 0.93 0 24 12 48 24.96[9,10] 12.96[10,11] 49.92[9,10,12] MHz MHz MHz FBLK3 F32K1 F32K1 Jitter32k Step24M Fout48M 0 15 ­ ­ 46.08 24 32 100 50 48.0 25.92[10,12] 64 MHz kHz ns kHz MHz ­ 300 ­ ­ 12.96 MHz 0 ­ ­ s Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency 32 kHz Period Jitter 24 MHz Trim Step Size 48 MHz Output Frequency Jitter24M 24 MHz Period Jitter (IMO) Peak-to-Peak 1 FMAX Maximum frequency of signal on row input or row output. TRAMP Supply Ramp Time ­ 49.92[9,11] Notes Trimmed for 5V operation using factory trim values. Trimmed for 3.3V operation using factory trim values. -10°C TA 85°C 4.35 Vdd 5.15 -0°C TA 70°C 3.15 Vdd 3.45 Refer to the AC Digital Block Specifications. Trimmed. Utilizing factory trim values. ps Figure 9-2. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F24M Notes 9. 4.75V < Vdd < 5.25V. 10. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 11. 3.0V < Vdd < 3.6V. See Application Note AN2012 AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. 12. See the individual user module data sheets for information on maximum frequencies for user modules Document Number: 38-12018 Rev. *O Page 30 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.4.2 AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-17. AC GPI/O Specifications Symbol FGPI/O TRiseF TFallF TRiseS TFallS Description GPI/O Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ ­ ­ ­ 27 22 Max 12 18 18 ­ ­ Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Figure 9-3. GPI/O Timing Diagram 90% G PIO Pin O utput Voltage 10% TRiseF TRiseS TFallF TFallS 9.4.3 AC Full Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -10°C TA 85°C, or 3.0V to 3.6V and -10°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-18. AC Full Speed (12 Mbps) USB Specifications Symbol TRFS TFSS TRFMFS TDRATEFS Description Transition Rise Time Transition Fall Time Rise/Fall Time Matching: (TR/TF) Full Speed Data Rate Document Number: 38-12018 Rev. *O Min 4 4 90 12 0.25% Typ ­ ­ ­ 12 Max 20 20 111 12 + 0.25% Units ns ns % Mbps Notes For 50 pF load. For 50 pF load. For 50 pF load. Page 31 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.4.4 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 9-19. 5V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA SRFOA BWOA ENOA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units ­ ­ ­ ­ ­ ­ 3.9 0.72 0.62 s s s ­ ­ ­ ­ ­ ­ 5.9 0.92 0.72 s s s 0.15 1.7 6.5 ­ ­ ­ ­ ­ ­ V/s V/s V/s 0.01 0.5 4.0 ­ ­ ­ ­ ­ ­ V/s V/s V/s 0.75 3.1 5.4 ­ ­ ­ ­ 100 ­ ­ ­ ­ MHz MHz MHz nV/rt-Hz Min Typ Max Units ­ ­ ­ ­ 3.92 0.72 s s ­ ­ ­ ­ 5.41 0.72 s s 0.31 2.7 ­ ­ ­ ­ V/s V/s 0.24 1.8 ­ ­ ­ ­ V/s V/s 0.67 2.8 ­ ­ ­ 100 ­ ­ ­ MHz MHz nV/rt-Hz Table 9-20. 3.3V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA SRFOA BWOA ENOA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Document Number: 38-12018 Rev. *O Page 32 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 9-4. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 9-5. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 Document Number: 38-12018 Rev. *O 0.01 0.1 Freq (kHz) 1 10 100 Page 33 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.4.5 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, 3.0V to 3.6V and -40°C TA 85°C, or 2.4V to 3.0V and -40°C TA 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 9-21. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min ­ Typ ­ Max 50 Units s Notes 50 mV overdrive comparator reference set within VREFLPC. 9.4.6 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-22. AC Digital Block Specifications Function Min Typ Max Units 50[13] ­ ­ ns Maximum Frequency, No Capture ­ ­ 49.92 MHz Maximum Frequency, With Capture ­ ­ 25.92 MHz 50[13] ­ ­ ns Maximum Frequency, No Enable Input ­ ­ 49.92 MHz Maximum Frequency, Enable Input ­ ­ 25.92 MHz Asynchronous Restart Mode 20 ­ ­ ns Synchronous Restart Mode 50[13] ­ ­ ns Disable Mode 50[13] ­ ­ ns Maximum Frequency ­ ­ 49.92 MHz 4.75V < Vdd < 5.25V. CRCPRS Maximum Input Clock Frequency (PRS Mode) ­ ­ 49.92 MHz 4.75V < Vdd < 5.25V. CRCPRS Maximum Input Clock Frequency (CRC Mode) ­ ­ 24.6 MHz SPIM Maximum Input Clock Frequency ­ ­ 8.2 MHz SPIS Maximum Input Clock Frequency Timer Counter Dead Band Description Capture Pulse Width Enable Pulse Width Notes 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Kill Pulse Width: Width of SS_ Negated Between Transmissions ­ ­ 4.1 MHz 50[13] ­ ­ Maximum data rate at 4.1 MHz due to 2 x over clocking. ns Transmitter Maximum Input Clock Frequency ­ ­ 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Receiver Maximum Input Clock Frequency ­ ­ 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Note 13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 38-12018 Rev. *O Page 34 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 9.4.7 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-23. AC External Clock Specifications Symbol Description FOSCEXT Frequency for USB Applications Min Typ Max Units 23.94 24 24.06 MHz ­ Duty Cycle 47 50 53 % ­ Power up to IMO Switch 150 ­ ­ Notes s 9.4.8 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9-24. 5V AC Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Document Number: 38-12018 Rev. *O Min Typ Max Units ­ ­ ­ ­ 2.5 2.5 s s ­ ­ ­ ­ 2.2 2.2 s s 0.65 0.65 ­ ­ ­ ­ V/s V/s 0.65 0.65 ­ ­ ­ ­ V/s V/s 0.8 0.8 ­ ­ ­ ­ MHz MHz 300 300 ­ ­ ­ ­ Notes kHz kHz Page 35 of 47 [+] Feedback CY8C24094 CY8C24094, CY8C24794 CY8C24794 CY8C24894 CY8C24894, CY8C24994 CY8C24994 Table 9-25. 3.3V AC Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min Typ Max Units ­ ­ ­ ­ 3.8 3.8 s s ­ ­ ­ ­ 2.6 2.6 s s 0.5 0.5 ­ ­ ­ ­ V/s V/s 0.5 0.5 ­ ­ ­ ­ V/s V/s 0.7 0.7 ­ ­ ­ ­ MHz MHz 200 200 ­ ­ ­ ­ Notes kHz k