CY7C65013 CY7C65113 12-BIT SSOP/48 80-8F 90-9F 010X0001 01XX0001 - Datasheet Archive

 

CY7C65013 CY7C65113 CY7C65013 CY7C65113 USB Hub with Microcontroller Cypress Semiconductor Corporation · 3901 North First

 

3 CY7C65013 CY7C65013 CY7C65113 CY7C65113 CY7C65013 CY7C65013 CY7C65113 CY7C65113 USB Hub with Microcontroller Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 June 13, 2000 CY7C65013 CY7C65013 CY7C65113 CY7C65113 TABLE OF CONTENTS 1.0 FEATURES . 5 2.0 FUNCTIONAL OVERVIEW . 6 3.0 PIN CONFIGURATIONS . 8 4.0 PRODUCT SUMMARY TABLES . 9 4.1 Pin Assignments .9 4.2 I/O Register Summary . 9 4.3 Instruction Set Summary .11 5.0 PROGRAMMING MODEL .12 5.1 14-Bit Program Counter (PC) .12 5.1.1 Program Memory Organization . 13 5.2 8-Bit Accumulator (A) .14 5.3 8-Bit Temporary Register (X) .14 5.4 8-Bit Program Stack Pointer (PSP) .14 5.4.1 Data Memory Organization . 14 5.5 8-Bit Data Stack Pointer (DSP) .15 5.6 Address Modes .15 5.6.1 Data (Immediate) . 15 5.6.2 Direct .15 5.6.3 Indexed . 15 6.0 CLOCKING .16 7.0 RESET .16 7.1 Power-On Reset (POR) .16 7.2 Watch Dog Reset (WDR) .17 8.0 SUSPEND MODE .17 9.0 GENERAL-PURPOSE I/O (GPIO) PORTS .18 9.1 GPIO Configuration Port .19 9.2 GPIO Interrupt Enable Ports .20 10.0 12-BIT 12-BIT FREE-RUNNING TIMER .20 10.1 Timer (LSB) .20 10.2 Timer (MSB) .20 11.0 I2C CONFIGURATION REGISTER .21 12.0 I2C CONTROLLER .21 13.0 PROCESSOR STATUS AND CONTROL REGISTER .23 14.0 INTERRUPTS .24 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 Interrupt Vectors .24 Interrupt Latency .26 USB Bus Reset Interrupt .26 Timer Interrupt .26 USB Endpoint Interrupts .26 USB Hub Interrupt .26 GPIO Interrupt .27 I2C Interrupt .27 15.0 USB OVERVIEW .28 2 CY7C65013 CY7C65013 CY7C65113 CY7C65113 15.1 USB Serial Interface Engine (SIE) .28 15.2 USB Enumeration .28 16.0 USB HUB .29 16.1 16.2 16.3 16.4 16.5 Connecting/Disconnecting a USB Device .29 Enabling/Disabling a USB Device .29 Hub Downstream Ports Status and Control .30 Downstream Port Suspend and Resume .31 USB Upstream Port Status and Control .32 17.0 USB SERIAL INTERFACE ENGINE OPERATION .33 17.1 17.2 17.3 17.4 17.5 17.6 USB Device Addresses .33 USB Device Endpoints .33 USB Control Endpoint Mode Registers .34 USB Non-Control Endpoint Mode Registers .34 USB Endpoint Counter Registers .35 Endpoint Mode/Count Registers update and Locking Mechanism .35 18.0 USB MODE TABLES .37 19.0 ABSOLUTE MAXIMUM RATINGS .41 20.0 ELECTRICAL CHARACTERISTICS .41 21.0 SWITCHING CHARACTERISTICS .42 22.0 ORDERING INFORMATION .42 23.0 PACKAGE DIAGRAMS .43 LIST OF FIGURES Figure 5-1. Program Memory Space with Interrupt Vector Table . 13 Figure 6-1. Clock Oscillator On-Chip Circuit . 16 Figure 7-1. Watch Dog Reset (WDR) . 17 Figure 9-1. Block Diagram of a GPIO Pin . 18 Figure 9-2. Port 0 Data 0x00 (read/write) . 18 Figure 9-3. Port 1 Data 0x01 (read/write) . 18 Figure 9-4. Port 2 Data 0x02 (read/write) . 18 Figure 9-5. Port 3 Data 0x03 (read/write) . 18 Figure 9-6. GPIO Configuration Register 0x08 (read/write) . 19 Figure 9-7. Port 0 Interrupt Enable 0x04 (read/write) . 20 Figure 9-8. Port 1 Interrupt Enable 0x05 (read/write) . 20 Figure 9-9. Port 2 Interrupt Enable 0x06 (read/write) . 20 Figure 9-10. Port 3 Interrupt Enable 0x07 (read/write) . 20 Figure 10-1. Timer Register 0x24 (read only) . 20 Figure 10-2. Timer Register 0x25 (read only) . 20 Figure 10-3. Timer Block Diagram . 21 Figure 11-1. I2C Configuration Register 0x09 (read/write) . 21 Figure 12-1. I2C Data Register 0x29 (separate read/write registers) . 22 Figure 12-2. I2C Status and Control Register 0x28 (read/write) . 22 Figure 13-1. Processor Status and Control Register 0xFF . 23 Figure 14-1. Global Interrupt Enable Register 0x20 (read/write) . 24 Figure 14-2. USB Endpoint Interrupt Enable Register 0x21 (read/write) . 24 Figure 14-3. Interrupt Controller Functional Diagram . 25 3 CY7C65013 CY7C65013 CY7C65113 CY7C65113 Figure 14-4. Interrupt Vector Register 0x23 (read only) . 26 Figure 14-5. GPIO Interrupt Structure . 27 Figure 16-1. Hub Ports Connect Status 0x48 (read/write), 1 = connect, 0 = disconnect . 29 Figure 16-2. Hub Ports Speed 0x4A (read/write), 1 = Low-Speed, 0 = Full-Speed . 29 Figure 16-3. Hub Ports Enable Register 0x49 (read/write), 1 = Enabled, 0 = Disabled . 30 Figure 16-4. Hub Downstream Ports Control Register 0x4B (read/write) . 30 Figure 16-5. Hub Ports Force Low Register (read/write) 0x51, 1 = Force Low, 0 = no force . 31 Figure 16-6. Hub Ports Force High Register (read/write) 0x52, 1=Force High, 0=no force . 31 Figure 16-7. Hub Ports SE0 Status Register 0x4F (read only), 1 = SE0, 0 = non-SE0 . 31 Figure 16-8. Hub Ports Data Register 0x50 (read only), 1 = (D+ > D­), 0 = (D+ < D­) . 31 Figure 16-9. Hub Ports Suspend Register 0x4D (read/write), 1 = Port is Selectively Suspended . 31 Figure 16-10. Hub Ports Resume Status Register 0x4E (read only), 1 = Port is in Resume State . 32 Figure 16-11. USB Status and Control Register 0x1F (read/write) . 32 Figure 17-1. USB Device Address Registers 0x10, 0x40 (read/write) . 33 Figure 17-2. USB Device Endpoint Zero Mode Registers 0x12 and 0x42, (read/write) . 34 Figure 17-3. USB Non-Control Device Endpoint Mode Registers 0x14, 0x16, 0x44, (read/write) . 35 Figure 17-4. USB Endpoint Counter Registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/write) . 35 Figure 17-5. Token/Data Packet Flow Diagram . 36 Figure 21-1. Clock Timing . 42 Figure 21-2. USB Data Signal Timing . 42 LIST OF TABLES Table 4-1. Pin Assignments .9 Table 4-2. I/O Register Summary . 9 Table 4-3. Instruction Set Summary .11 Table 9-1. Port Configurations .19 Table 11-1. I2C Port Configuration .21 Table 12-1. I2C Status and Control Register Bit Definitions .22 Table 14-1. Interrupt Vector Assignments .25 Table 16-1. Control Bit Definition for Downstream Ports .30 Table 16-2. Control Bit Definition for Upstream Port .33 Table 17-1. Memory Allocation for Endpoints .34 Table 18-1. USB Register Mode Encoding .37 Table 18-2. Decode table for Table 18-3: "Details of Modes for Differing Traffic Conditions" .38 Table 18-3. Details of Modes for Differing Traffic Conditions .39 4 CY7C65013 CY7C65013 CY7C65113 CY7C65113 1.0 Features · USB Hub with an integrated microcontroller · 8-bit USB Optimized Microcontroller - Harvard architecture - 6-MHz external clock source - 12-MHz internal CPU clock - 48-MHz internal Hub clock · Internal memory - 256 bytes of RAM - 8 KB of PROM · Integrated Master/Slave I2C Controller (100 kHz) enabled through General-Purpose I/O (GPIO) pins · I/O ports - Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical) - An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs - Higher current drive achievable by connecting multiple GPIO pins together to drive a common output - Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs · · · · - Maskable interrupts on all I/O pins 12-bit free-running timer with one microsecond clock ticks Watch Dog Timer (WDT) Internal Power-On Reset (POR) USB Specification Compliance - Conforms to USB Specification, Version 1.1 - Conforms to USB HID Specification, Version 1.1 - Supports one or two device addresses with up to 5 user configured endpoints Up to two 8-byte control endpoints Up to four 8-byte data endpoints Up to two 32-byte data endpoints - Integrated USB transceivers - Supports 7 (CY7C65013 CY7C65013) or 4 (CY7C65113 CY7C65113) Downstream USB ports - GPIO pins can provide individual power control outputs for each Downstream USB port · · · · · · - GPIO pins can provide individual port over current inputs for each Downstream USB port Improved output drivers to reduce EMI Operating voltage from 4.0V to 5.5V DC Operating temperature from 0 to 70 degrees Celsius CY7C65013 CY7C65013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages CY7C65113 CY7C65113 available in 28-pin SOIC (-SC) or 28-pin PDIP (-PC) packages Industry standard programmer support 5 CY7C65013 CY7C65013 CY7C65113 CY7C65113 2.0 Functional Overview The CY7C65x13 devices are One Time Programmable 8-bit microcontrollers with a built-in 12-Mbps USB hub that supports up to seven downstream ports. The microcontroller instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. The CY7C65013 CY7C65013 features 22 GPIO pins to support USB and other applications. The I/O pins are grouped into four ports (P0[7:0], P1[7:4,2:0], P2[7:3], P3[1:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Ports 0 to 2 are rated at 7 mA per pin (typical) sink current. Port 3 pins are rated at 12 mA per pin (typical) sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts all share the same "GPIO" interrupt vector. The CY7C65113 CY7C65113 has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental crystal that reduces the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution within the microcontroller. The CY7C65013 CY7C65013 and the CY7C65113 CY7C65113 are offered with 8 KB of PROM. These parts include power-on reset logic, a watch dog timer, and a 12-bit free-running timer. The Power-On Reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The watch dog timer is used to ensure the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The microcontroller can communicate with external electronics through the GPIO pins. An I2C interface accommodates a 100-kHz serial link with an external device. The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read. The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus Reset interrupt, the 128-µs (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five USB endpoints, the USB hub, the GPIO ports, and the I2C master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles from LOW `0' to HIGH `1'. The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge (`0' to `1') or falling edge (`1' to `0'). The CY7C65013 CY7C65013 and CY7C65113 CY7C65113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated peripherals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the hub (two endpoints) and a device address for a compound device (three endpoints). The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller. The CY7C65113 CY7C65113 part includes a 1:4 hub repeater with one upstream port and four downstream ports, while the CY7C65013 CY7C65013 part includes a 1:7 hub repeater. The USB Hub allows power management control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the downstream ports together with a single pair of power management pins, or providing power management for each port with four (CY7C65113 CY7C65113) or seven (CY7C65013 CY7C65013) pairs of power management pins. 6 CY7C65013 CY7C65013 CY7C65113 CY7C65113 . Logic Block Diagram 6-MHz crystal USB Transceiver D+[0] Upstream D­[0] USB Port Downstream USB Ports PLL USB Transceiver D+[1] D­[1] USB Transceiver D+[4] D­[4] USB SIE USB Transceiver D+[5] D­[5] Interrupt Controller USB Transceiver D+[7] D­[7] 48 MHz Clock Divider 12-MHz 8-bit CPU Repeater 12 MHz RAM 256 byte 8-bit Bus PROM 8 KB CY7C65013 CY7C65013 only 6 MHz 12-bit Timer Watch Dog Timer P0[0] GPIO PORT 0 Power management under firmware control using GPIO pins P0[7] P1[0] GPIO PORT 1 P1[2] GPIO PORT 1 P1[7:4] Power-On Reset GPIO PORT 2 P2[7] GPIO PORT 3 P3[1] High Current P3[0] Outputs P2[3] CY7C65013 CY7C65013 only I2C Interface SCLK SDATA *I 2C interface enabled by firmware through P2[1:0] or P1[1:0] 7 CY7C65013 CY7C65013 CY7C65113 CY7C65113 3.0 Pin Configurations TOP VIEW CY7C65013 CY7C65013 CY7C65113 CY7C65113 48-pin SSOP/48 SSOP/48 PDIP 28-pin SOIC/PDIP XTALOUT 1 48 VCC XTALIN 2 47 P1[0] P1[1] 3 46 P1[2] P1[5] 4 45 P1[4] P1[7] 5 44 P1[6] P3[1] 6 43 P3[0] D+[0] 7 42 D­[3] D­[0] 8 41 D+[3] GND 9 40 D+[1] 10 D­[1] XTALOUT 1 28 VCC XTALIN 2 27 P1[1] VREF 3 26 P1[0] GND 4 25 P1[2] D+[0] 5 24 D­[3] D­[0] 6 23 D+[3] D+[1] 7 22 D­[4] D­[1] 8 21 D+[4] GND D+[2] 9 20 GND 39 D­[4] D­[2] 10 19 VPP 11 38 D+[4] P0[7] 11 18 P0[0] VREF 12 37 VREF P0[5] 12 17 P0[2] D+[2] 13 36 D­[5] P0[3] 13 16 P0[4] D­[2] 14 35 D+[5] P0[1] 14 15 P0[6] P2[3] 15 34 GND GND 16 33 P2[4] P2[5] 17 32 D­[6] D+[7] 18 31 D+[6] D­[7] 19 30 P2[6] P2[7] 20 29 VPP P0[7] 21 28 P0[0] P0[5] 22 27 P0[2] P0[3] 23 26 P0[4] P0[1] 24 25 P0[6] 8 CY7C65013 CY7C65013 CY7C65113 CY7C65113 4.0 Product Summary Tables 4.1 Pin Assignments Table 4-1. Pin Assignments Name I/O 48-Pin 28-Pin D+[0], D­[0] I/O 7, 8 5, 6 Description Upstream port, USB differential data. D+[1], D­[1] I/O 10, 11 7, 8 Downstream Port 1, USB differential data. D+[2], D­[2] I/O 13, 14 9, 10 Downstream Port 2, USB differential data. D+[3], D­[3] I/O 41, 42 23, 24 Downstream Port 3, USB differential data. D+[4], D­[4] I/O 38, 39 21, 22 Downstream Port 4, USB differential data. D+[5], D­[5] I/O 35, 36 Downstream Port 5, USB differential data. D+[6], D­[6] I/O 31, 32 Downstream Port 6, USB differential data. D+[7], D­[7] I/O 18, 19 Downstream Port 7, USB differential data. P0 I/O P1[7:0] 21, 25, 22, 26, 23, 27, 24, 28 P1[7:0] 11, 15, 12, 16, 13, 17, 14, 18 GPIO Port 0 capable of sinking 7 mA (typical). P1 I/O P1[7:4,2:0] 5, 44, 4, 45; 46, 3, 47 P1[2:0] 25, 27, 26 GPIO Port 1 capable of sinking 7 mA (typical). P2 I/O P2[7:3] 20, 30, 17, 33, 15 GPIO Port 2 capable of sinking 12 mA (typical). P3 I/O P3[1:0] 6, 43 GPIO Port 3, capable of sinking 12 mA (typical). XTALIN IN 2 OUT VPP 6-MHz crystal or external clock input. 1 1 6-MHz crystal out. 29 XTALOUT 2 19 Programming voltage supply, tie to ground during normal operation. Voltage supply. VCC 48 28 GND 9, 16, 34, 40 4, 20 12, 37 3 VREF 4.2 IN Ground. External 3.3V supply voltage for the downstream differential data output buffers and the D+ pull up. I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X. All undefined registers are reserved. Do not write to reserved registers as this may cause an undefined operation or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with `0'. Table 4-2. I/O Register Summary I/O Address Read/Write Port 0 Data Register Name 0x00 R/W GPIO Port 0 Data Function 18 Port 1 Data 0x01 R/W GPIO Port 1 Data 18 Port 2 Data 0x02 R/W GPIO Port 2 Data 18 Port 3 Data 0x03 R/W GPIO Port 3 Data 18 Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 20 Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 20 Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 20 9 Page CY7C65013 CY7C65013 CY7C65113 CY7C65113 Table 4-2. I/O Register Summary (continued) Register Name I/O Address Read/Write Port 3 Interrupt Enable 0x07 W GPIO Configuration 0x08 R/W 2 Function Page Interrupt Enable for Pins in Port 3 20 GPIO Port Configurations 19 2 I C Configuration 0x09 R/W I C Position Configuration 21 USB Device Address A 0x10 R/W USB Device Address A 33 EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 35 EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 34 EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 35 EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 35 EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 35 EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 35 USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 32 Global Interrupt Enable 0x20 R/W Global Interrupt Enable 24 Endpoint Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 24 Interrupt Vector 0x23 R Pending Interrupt Vector Read/Clear 25 Timer (LSB) 0x24 R Lower 8 Bits of Free-running Timer (1 MHz) 20 Timer (MSB) 0x25 R Upper 4 Bits of Free-running Timer 20 WDT Clear 0x26 W Watch Dog Timer Clear 17 I2C Control & Status 0x28 R/W I2C Status and Control 22 I2C Data 0x29 R/W I2C Data 22 Reserved 0x30 Reserved Reserved 0x31 Reserved Reserved 0x32 Reserved Reserved 0x38-0x3F Reserved USB Device Address B 0x40 R/W USB Device Address B (not used in 5-endpoint mode) 33 EP B0 Counter Register 0x41 R/W USB Address B, Endpoint 0 Counter 35 EP B0 Mode Register 0x42 R/W USB Address B, Endpoint 0 Configuration, or USB Address A, Endpoint 3 in 5-endpoint mode 34 EP B1 Counter Register 0x43 R/W USB Address B, Endpoint 1 Counter 35 EP B1 Mode Register 0x44 R/W USB Address B, Endpoint 1 Configuration, or USB Address A, Endpoint 4 in 5-endpoint mode 35 Hub Port Connect Status 0x48 R/W Hub Downstream Port Connect Status 29 Hub Port Enable 0x49 R/W Hub Downstream Ports Enable 30 Hub Port Speed 0x4A R/W Hub Downstream Ports Speed 29 Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control (Ports [4:1]) 30 Hub Port Control (Ports [7:5]) 0x4C R/W Hub Downstream Ports Control (Ports [7:5]) 30 Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 31 Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 32 Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 31 Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 31 Hub Downstream Force Low 0x51 R/W Hub Downstream Ports Force LOW (Ports [1:4]) 31 Hub Downstream Force High 0x52 R/W Hub Downstream Ports Force HIGH (Ports [5:7]) 31 Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 23 10 CY7C65013 CY7C65013 CY7C65113 CY7C65113 4.3 Instruction Set Summary Refer to the CYASM Assembler User's Guide for more details. Table 4-3. Instruction Set Summary MNEMONIC operand HALT opcode cycles MNEMONIC 00 7 operand NOP opcode cycles 20 4 ADD A,expr data 01 4 INC A acc 21 4 ADD A,[expr] direct 02 6 INC X x 22 4 ADD A,[X+expr] index 03 7 INC [expr] direct 23 7 ADC A,expr data 04 4 INC [X+expr] index 24 8 ADC A,[expr] direct 05 6 DEC A acc 25 4 ADC A,[X+expr] index 06 7 DEC X x 26 4 SUB A,expr data 07 4 DEC [expr] direct 27 7 SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8 SUB A,[X+expr] index 09 7 IORD expr address 29 5 SBB A,expr data 0A 4 IOWR expr address 2A 5 SBB A,[expr] direct 0B 6 POP A 2B 4 SBB A,[X+expr] index 0C 7 POP X 2C 4 OR A,expr data 0D 4 PUSH A 2D 5 OR A,[expr] direct 0E 6 PUSH X 2E 5 OR A,[X+expr] index 0F 7 SWAP A,X 2F 5 AND A,expr data 10 4 SWAP A,DSP 30 5 AND A,[expr] direct 11 6 MOV [expr],A direct 31 5 AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6 XOR A,expr data 13 4 OR [expr],A direct 33 7 XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8 XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7 CMP A,expr data 16 5 AND [X+expr],A index 36 8 CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7 CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8 MOV A,expr data 19 4 IOWX [X+expr] index 39 6 MOV A,[expr] direct 1A 5 CPL 3A 4 MOV A,[X+expr] index 1B 6 ASL 3B 4 MOV X,expr data 1C 4 ASR 3C 4 MOV X,[expr] direct 1D 5 RLC 3D 4 RRC 3E 4 reserved 1E XPAGE 1F 4 RET 3F 8 MOV A,X 40 4 DI 70 4 MOV X,A 41 4 EI 72 4 MOV PSP,A 60 4 RETI 73 8 CALL addr 50 - 5F 10 JC addr C0-CF 5 JMP addr 80-8F 80-8F 5 JNC addr D0-DF 5 CALL addr 90-9F 90-9F 10 JACC addr E0-EF 7 JZ addr A0-AF 5 INDEX addr F0-FF 14 JNZ addr B0-BF 5 11 CY7C65013 CY7C65013 CY7C65113 CY7C65113 5.0 Programming Model 5.1 14-Bit Program Counter (PC) The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65x13 architecture. The top 32 bytes of the ROM in the 8K part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes the application (see Interrupt Vectors on page 24). The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte "page" of sequential code should be an XPAGE instruction. The assembler directive "XPAGEON" causes the assembler to insert XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE to execute correctly. The address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction. The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up. 12 CY7C65013 CY7C65013 CY7C65113 CY7C65113 5.1.1 Program Memory Organization after reset 14-bit PC Address 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128-µs timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 USB address A endpoint 0 interrupt vector 0x000A USB address A endpoint 1 interrupt vector 0x000C USB address A endpoint 2 interrupt vector 0x000E USB address B endpoint 0 interrupt vector 0x0010 USB address B endpoint 1 interrupt vector 0x0012 Hub interrupt vector 0x0014 Reserved 0x0016 GPIO interrupt vector 0x0018 I2C interrupt vector 0x001A Program Memory begins here 0x1FDF 8 KB (-32) PROM ends here (CY7C65013 CY7C65013, CY7C65113 CY7C65113) Figure 5-1. Program Memory Space with Interrupt Vector Table 13 CY7C65013 CY7C65013 CY7C65113 CY7C65113 5.2 8-Bit Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 5.3 8-Bit Temporary Register (X) The "X" register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the value in X. Refer to Section 5.6.3 for additional information. 5.4 8-Bit Program Stack Pointer (PSP) During a reset, the Program Stack Pointer (PSP) is set to 0x00 and "grows" upward from this address. The PSP may be set by firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control. The PSP is not readable by the firmware. During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the PSP, then the PSP is incremented. The second byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program counter and flags on the program "stack" and increment the PSP by two. The Return From Interrupt (RETI) instruction decrements the PSP, then restores the second byte from memory addressed by the PSP. The PSP is decremented again and the first byte is restored from memory addressed by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The overall effect is to restore the program counter and flags from the program stack, decrement the PSP by two, and re-enable interrupts. The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two. The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and decrements the PSP by two. 5.4.1 Data Memory Organization The CY7C65x13 microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program stack, user variables, data stack, and USB endpoint FIFOs. The following is one example of where the program stack, data stack, and user variables areas could be located. After reset 8-bit DSP 8-bit PSP Address 0x00 Program Stack Growth user selected Data Stack Growth (Move DSP[1]) 8-bit DSP User variables USB FIFO space for up to two Addresses and five endpoints[2] 0xFF Notes: 1. Refer to Section 5.5 for a description of DSP. 2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 17-1. 14 CY7C65013 CY7C65013 CY7C65113 CY7C65113 5.5 8-Bit Data Stack Pointer (DSP) The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP. During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB endpoint FIFOs. For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are described in Section 17.2. Example assembly instructions to do this with two device addresses (FIFOs begin at 0xD8) are shown below: MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register 5.6 Address Modes The CY7C65013 CY7C65013 and CY7C65113 CY7C65113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 Data (Immediate) "Data" address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xD8: · MOV A,0D8h This instruction requires two bytes of code where the first byte identifies the "MOV A" instruction with a data operand as the second byte. The second byte of the instruction is the constant "0xD8". A constant may be referred to by name if a prior "EQU" statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above: · DSPINIT: EQU 0D8h · MOV A,DSPINIT 5.6.2 Direct "Direct" address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10: · MOV A,[10h] Normally, variable names are assigned to variable addresses using "EQU" statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above: · buttons: EQU 10h · MOV A,[buttons] 5.6.3 Indexed "Indexed" address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the "X" register. Normally, the constant is the "base" address of an array of data and the X register contains an index that indicates which element of the array is actually addressed: · array: EQU 10h · MOV X,3 · MOV A,[X+array] This would have the effect of loading A with the fourth element of the SRAM "array" that begins at address 0x10. The fourth element would be at address 0x13. 15 CY7C65013 CY7C65013 CY7C65113 CY7C65113 6.0 Clocking XTALOUT (pin 1) XTALIN (pin 2) to internal PLL 30 pF 30 pF Figure 6-1. Clock Oscillator On-Chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than 2 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal PLL. The two internal 30-pF load caps appear in series to the external crystal and would be equivalent to a 15-pF load. Therefore, the crystal must have a required load capacitance of about 15­18 pF. A ceramic resonator does not allow the microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with these parts. An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground. 7.0 Reset The CY7C65x13 supports two resets: Power-On Reset (POR) and a Watch Dog Reset (WDR). Each of these resets causes: · all registers to be restored to their default states, · the USB Device Addresses to be set to 0, · all interrupts to be disabled, · the PSP and Data Stack Pointer (DSP) to be set to memory address 0x00. The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section 13.0. Bits 4 and 6 are used to record the occurrence of POR and WDR respectively. Firmware can interrogate these bits to determine the cause of a reset. Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware reset handler should configure the hardware before the "main" loop of code. Attempting to execute a RET or RETI in the firmware reset handler causes unpredictable execution results. 7.1 Power-On Reset (POR) When VCC is first applied to the chip, the Power-On Reset (POR) signal is asserted and the CY7C65x13 enters a "semi-suspend" state. During the semi-suspend state, which is different from the suspend state defined in the USB specification, the oscillator and all other blocks of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid VCC level is reached and that the internal PLL has time to stabilize before full operation begins. When the VCC has risen above approximately 2.5V, and the oscillator is stable, the POR is deasserted and the on-chip timer starts counting. The first 1 ms of suspend time is not interruptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a USB Bus Reset on the upstream port. The 95 ms provides time for V CC to stabilize at a valid operating voltage before the chip executes code. If a USB Bus Reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced until firmware sets the USB Bus Reset Interrupt Enable bit (bit 0 of register 0x20) and enables interrupts with the EI command. The POR signal is asserted whenever VCC drops below approximately 2.5V, and remains asserted until VCC rises above this level again. Behavior is the same as described above. 16 CY7C65013 CY7C65013 CY7C65113 CY7C65113 7.2 Watch Dog Reset (WDR) The Watch Dog Timer Reset (WDR) occurs when the internal Watch Dog timer rolls over. Writing any value to the write-only Watch Dog Restart Register at address 0x26 clears the timer. The timer rolls over and WDR occurs if it is not cleared within tWATCH (8 ms minimum) of the last clear. Bit 6 of the Processor Status and Control Register is set to record this event (the register contents are set to 010X0001 010X0001 by the WDR). A Watch Dog Timer Reset lasts for 2 ms, after which the microcontroller begins execution at ROM address 0x0000. 2 ms tWATCH Last write to Watch Dog Timer Register No write to WDT register, so WDR goes HIGH Execution begins at Reset Vector 0x0000 Figure 7-1. Watch Dog Reset (WDR) The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Registers are cleared (see Section 17.1). Otherwise, the USB Controller would respond to all address 0 transactions. It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. If a firmware interrogates the Processor Status and Control Register for a set condition on the WDR bit, the WDR bit should be ignored if the POR (bit 3 of register 0xFF) bit is set. 8.0 Suspend Mode The CY7C65xxx can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register. All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL, as well as the free-running and watch dog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle bus activity at a USB upstream or downstream port wakes the part out of suspend. The Run bit in the Processor Status and Control Register must be set to resume a part out of suspend. The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend mode before servicing any interrupt requests. The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at VCC or Gnd. Note: This also applies to internal port pins that may not be bonded in a particular package. Typical code for entering suspend is shown below: . . mov a, 09h iowr FFh nop . ; All GPIO set to low-power state (no floating pins) ; Enable GPIO interrupts if desired for wake-up ; Set suspend and run bits ; Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt) ; This executes before any ISR ; Remaining code for exiting suspend routine 17 CY7C65013 CY7C65013 CY7C65113 CY7C65113 9.0 General-Purpose I/O (GPIO) Ports VCC GPIO CFG mode 2-bits OE Control Q1 Data Out Latch Internal Data Bus Q2 14 k GPIO PIN Port Write Q3* Data In Latch Port Read Control Reg_Bit STRB (Latch is Transparent) Data Interrupt Latch Interrupt Enable Interrupt Controller *Port 0,1,2: Low Isink Port 3: High Isink Figure 9-1. Block Diagram of a GPIO Pin There are up to 32 GPIO pins (P0[7:0], P1[7:4,2:0], P2[7:3], and P3[1:0]) for the hardware interface. The number of GPIO pins changes based on the package type of the chip. Each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Port 3 offers a higher current drive, with typical current sink capability of 12 mA. The data for each GPIO port is accessible through the data registers. Port data registers are shown in Figure 9-2 through Figure 9-5, and are set to 1 on reset. 7 6 5 4 3 2 1 0 P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Figure 9-2. Port 0 Data 0x00 (read/write) 7 6 5 4 3 2 1 0 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] Figure 9-3. Port 1 Data 0x01 (read/write) 7 6 5 4 3 2 1 0 P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 9-4. Port 2 Data 0x02 (read/write) 7 6 5 4 3 2 1 0 P3[7] (see text) P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Figure 9-5. Port 3 Data 0x03 (read/write) 18 CY7C65013 CY7C65013 CY7C65113 CY7C65113 Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB Specifications. If a `1' is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a `0.' Notice that the CY7C65113 CY7C65113 always requires that P1[7:3], P2[7:0], and P3[7:0] be written with a `0'. When the CY7C65013 CY7C65013 is used, the P1[3], P2[2:0], and P3[7:2] should be written with a `0'. A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data Registers. During reset, all of the GPIO pins are set to a high-impedance input state (`1' in open drain mode). Writing a `0' to a GPIO pin drives the pin LOW. In this state, a `0' is always read on that GPIO pin unless an external source overdrives the internal pull-down device. 9.1 GPIO Configuration Port Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In addition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, a rising edge (`0' to `1') on an input pin causes an interrupt. With negative polarity, a falling edge (`1' to `0') on an input pin causes an interrupt. As shown in the table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. The GPIO Configuration Port register provides two bits per port to program these features. The possible port configurations are detailed in Table 9-1: Table 9-1. Port Configurations Port Configuration bits Pin Interrupt Bit Driver Mode Interrupt Polarity 11 0 Resistive Disabled 1 Resistive ­ 0 CMOS Output Disabled 1 Open Drain Disabled 0 Open Drain Disabled 1 Open Drain ­ 0 Open Drain Disabled (Default Condition) 1 Open Drain + 10 01 00 (Reset State) In "Resistive" mode, a 14-k pull-up resistor is conditionally enabled for all pins of a GPIO port. An I/O pin is driven HIGH through a 14-k pull-up resistor when a `1' has been written to the pin. The output pin is driven LOW with the pull-up disabled when a `0' has been written to the pin. An I/O pin that has been written as a `1' can be used as an input pin with the integrated 14-k pull-up resistor. Resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the GPIO interrupt enabled. In "CMOS" mode, all pins of the GPIO port are outputs that are actively driven. A CMOS port is not a possible source for interrupts. In "Open Drain" mode, the internal pull-up resistor and CMOS driver (HIGH) are both disabled. An open drain I/O pin that has been written as a `1' can be used as an input or an open drain output. An I/O pin that has been written as a `0' drives the output low. The interrupt polarity for an open drain GPIO port can be selected as positive (rising edge) or negative (falling edge). During reset, all of the bits in the GPIO Configuration Register are written with `0' to select Open Drain output for all GPIO ports as the default configuration. 7 6 5 4 3 2 1 0 Port 3 Config Bit 1 Port 3 Config Bit 0 Port 2 Config Bit 1 Port 2 Config Bit 0 Port 1 Config Bit 1 Port 1 Config Bit 0 Port 0 Config Bit 1 Port 0 Config Bit 0 Figure 9-6. GPIO Configuration Register 0x08 (read/write) 19 CY7C65013 CY7C65013 CY7C65113 CY7C65113 9.2 GPIO Interrupt Enable Ports Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0­3 Interrupt Enable registers provide this feature with an interrupt enable bit for each GPIO pin. During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a `1' to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in Section 14.7. 7 6 P0[7] P0[6] 5 4 3 2 1 0 P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Figure 9-7. Port 0 Interrupt Enable 0x04 (write only) 7 6 5 4 3 2 1 0 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] Figure 9-8. Port 1 Interrupt Enable 0x05 (write only) 7 6 5 4 3 2 1 0 P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 9-9. Port 2 Interrupt Enable 0x06 (write only) 7 6 5 4 3 2 1 0 reserved set to zero P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Figure 9-10. Port 3 Interrupt Enable 0x07 (write only) 10.0 12-Bit Free-Running Timer The 12-bit timer provides two interrupts (128-µs and 1.024-ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is accessing the count stored in the temporary register. The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time. 10.1 Timer (LSB) 7 6 5 4 3 2 1 0 Timer Bit 7 Timer Bit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0 Figure 10-1. Timer Register 0x24 (read only) 10.2 Timer (MSB) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Timer Bit 9 Timer Bit 8 Figure 10-2. Timer Register 0x25 (read only) 20 CY7C65013 CY7C65013 CY7C65113 CY7C65113 1.024-ms Interrupt 128-µs Interrupt 11 10 9 8 L3 L2 L1 L0 D3 D2 D1 7 D0 6 D7 5 D6 4 D5 3 D4 2 D3 1 D2 0 D1 1-MHz Clock D0 To Timer Register 8 Figure 10-3. Timer Block Diagram I2C Configuration Register 11.0 Internal hardware supports communication with external devices through an I2C interface. I2C function is discussed in detail in Section 12.0. Bit 7 of I2C Configuration Register selects I2C functionality on Port 1 or Port 2. This bit is cleared on reset. 7 6 5 4 Reserved Reserved 3 2 1 0 Reserved Reserved Reserved Reserved Reserved R/W 2 I C Position Figure 11-1. I2C Configuration Register 0x09 (read/write) Note: I2C must be separately enabled as described in Section 12.0. Table 11-1. I2C Port Configuration I2C Position Bit[7] I2C Position X 1 I2C on P2[1:0], 0:SCL, 1:SDA 0 0 I2C on P1[1:0], 0:SCL, 1:SDA 1 12.0 Port Width Bit[1] 0 I2C on P2[1:0], 0:SCL, 1:SDA I2C Controller The I2C block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-master modes of operation. The I2C block functions by handling the low-level signaling in hardware, and issuing interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the hardware keeps the I2C bus idle if necessary. The I2C generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in Section 14.8. The I2C interface consists of two registers, an I2C Data Register (Figure 12-1) and an I2C Status and Control Register (Figure 12-2). The Data Register is implemented as separate read and write registers. Generally, the I2C Status and Control Register should only be monitored after the I2C interrupt, as all bits are valid at that time. Polling this register at other times could read bit misleading bit status if a transaction is underway. The I2C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I2C SDA data is connected to bit 1 of GPIO port 1 or GPIO port 2. Refer to Section 11.0 for the bit definitions and functionality of the I2C Configuration Register, which is used to set the locations of the configurable I2C pins. Once the I2C functionality is enabled by setting bit 0 of the I2C Status & Control Register, the two LSB ([1:0]) of the corresponding GPIO port is placed in Open Drain mode, regardless of the settings of the GPIO 21 CY7C65013 CY7C65013 CY7C65113 CY7C65113 Configuration Register.The electrical characteristics of the I2C interface is the same as that of GPIO ports 1 and 2. Note that the IOL (max) is 2 mA @ VOL = 2.0 V for ports 1 and 2. All control of the I2C clock and data lines is performed by the I2C block. 7 6 2 I C Data 7 5 2 I C Data 6 4 2 I C Data 5 Figure 12-1. I2C 3 2 2 I C Data 4 2 I C Data 3 1 2 2 I C Data 2 I C Data 1 0 2 I C Data 0 Data Register 0x29 (separate read/write registers) 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W MSTR Mode Continue/ Busy Xmit Mode ACK Addr ARB Lost/ Restart Received Stop I2C Enable Figure 12-2. I2C Status and Control Register 0x28 (read/write) The I2C Status and Control register bits are defined in Table 12-1, with a more detailed description following. Table 12-1. I2C Status and Control Register Bit Definitions Bit Name 2 Description 2 0 I C Enable Write to 1 to enable I C function. When cleared, I2C GPIO pins operate normally. 1 Received Stop Reads 1 only in slave receive mode, when I2C Stop bit detected (unless firmware did not ACK the last transaction). 2 ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise. Write to 1 in master mode to perform a restart sequence (also set Continue bit). 3 Addr Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration. Reads 0 otherwise. This bit should always be written as 0. 4 ACK In receive mode, write 1 to generate ACK, 0 for no ACK. In transmit mode, reads 1 if ACK was received, 0 if no ACK received. 5 Xmit Mode Write to 1 for transmit mode, 0 for receive mode. 6 Continue/Busy Write 1 to indicate ready for next transaction. Reads 1 when I2C block is busy with a transaction, 0 when transaction is complete. 7 MSTR Mode Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration. Clearing from 1 to 0 generates Stop bit. MSTR Mode: Setting this bit causes the I2C to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes are initiated by setting the Continue bit, as described below. In master mode, the I2C block generates the clock (SCK), and drives the data line as required depending on transmit or receive state. The I2C block performs any required arbitration and clock synchronization. The loss of arbitration results in the clearing of this bit, the setting of the ARB Lost bit, and the generation of an interrupt to the microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the transaction from the external master is completed. When MSTR Mode is cleared from 1 to 0 by a firmware write, an I2C Stop bit is generated. Continue / Busy: This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. In other words, the bit has responded to an interrupt request and has completed the required update or read of the data register. During a read this bit indicates if the hardware is busy and is locking out additional writes to the I2C Status and Control register. This locking allows the hardware to complete certain operations that may require an extended period of time. Following an I2C interrupt, the I2C block does not return to the Busy state until firmware sets the Continue bit. This allows the firmware to make one control register write without the need to check the Busy bit. Xmit Mode: This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clear this bit for receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I2C address packet. The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases always cause transmit mode for the first byte. 22 CY7C65013 CY7C65013 CY7C65113 CY7C65113 ACK: This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal on the I2C bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I2C bus at the ACK bit time. During transmits (Xmit Mode = 1), this bit should be cleared. Addr: This bit is set by the I2C block during the first byte of a slave receive transaction, after an I2C start or restart. The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred. ARB Lost/Restart: This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the Continue and MSTR Mode bits) to perform an I2C restart sequence. The I2C target address for the restart must be written to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware during the restart sequence. Receive Stop: This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the firmware terminates the I2C transaction by not acknowledging the previous byte transmitted on the I2C bus, e.g. in receive mode if firmware sets the Continue bit and clears the ACK bit. I2C Enable: Set this bit to override GPIO definition with I2C function on the two I2C pins. When this bit is cleared, these pins are free to function as GPIOs. In I2C mode, the two pins operate in open drain mode, independent of the GPIO configuration setting. 13.0 Processor Status and Control Register 7 6 5 4 3 2 R R/W R/W R/W R/W R IRQ Pending Watch Dog Reset USB Bus Reset Interrupt Power-On Reset Suspend Interrupt Enable Sense 1 0 R/W reserved Run Figure 13-1. Processor Status and Control Register 0xFF The Run bit, bit 0, is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control Register are cleared to 0. Since the run bit is cleared, the processor stops at the end of the current instruction. The processor remains halted until an appropriate reset occurs (power-on or watch dog). This bit should normally be written as a `1.' Bit 1 is reserved and must be written as a zero. The Interrupt Enable Sense (bit 2) shows whether interrupts are enabled or disabled. Firmware has no direct control over this bit as writing a zero or one to this bit position has no effect on interrupts. A `0' indicates that interrupts are masked off and a `1' indicates that the interrupts are enabled. This bit is further gated with the bit settings of the Global Interrupt Enable Register (0x20) and USB End Point Interrupt Enable Register (0x21). Instructions DI, EI, and RETI manipulate the state of this bit. Writing a `1' to the Suspend bit (bit 3) halts the processor and cause the microcontroller to enter the suspend mode that significantly reduces power consumption. A pending, enabled interrupt or USB bus activity causes the device to come out of suspend. After coming out of suspend, the device resumes firmware execution at the instruction following the IOWR which put the part into suspend. An IOWR attempting to put the part into suspend is ignored if non-idle USB bus activity is present. See Section 8.0 for more details on suspend mode operation. The Power-On Reset (bit 4) is set to `1' during a power-on reset. The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power-on condition or a watch dog timeout. A POR event may be followed by a watch dog reset before firmware begins executing, as explained below. The USB Bus Reset Interrupt (bit 5) occurs when a USB Bus Reset is received on the upstream port. The USB Bus Reset is a single-ended zero (SE0) that lasts from 12 to 16 µs. An SE0 is defined as the condition in which both the D+ line and the D­ line are LOW at the same time. When the SIE detects that this SE0 condition is removed, the USB Bus Reset interrupt bit is set in the Processor Status and Control Register and a USB Bus Reset interrupt is generated. The Watch Dog Reset (bit 6) is set during a reset initiated by the Watch Dog Timer. This indicates the Watch Dog Timer went for more than tWATCH (8 ms minimum) between Watch Dog clears. This can occur with a POR event, as noted below. The IRQ pending (bit 7), when set, indicates that one or more of the interrupts has been recognized as active. An interrupt remains pending until its interrupt enable bit is set (registers 0x20 or 0x21) and interrupts are globally enabled. At that point, the internal interrupt handling sequence clears this bit until another interrupt is detected as pending. During power-up, the Processor Status and Control Register is set to 00010001, which indicates a POR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). During the 96 ms suspend at start-up (explained in Section 7.1), a Watch Dog Reset also occurs unless this suspend is aborted by an upstream SE0 before 8 ms. If a WDR occurs during the power-up suspend interval, firmware reads 01010001 from the Status and Control Register after power-up. Normally, the POR bit should be cleared so a subsequent WDR can be clearly identified. If an upstream bus reset is received before firmware examines this register, the Bus Reset bit may also be set. 23 CY7C65013 CY7C65013 CY7C65113 CY7C65113 During a Watch Dog Reset, the Processor Status and Control Register is set to 01XX0001 01XX0001, which indicates a Watch Dog Reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). The Watch Dog Reset does not effect the state of the POR and the Bus Reset Interrupt bits. 14.0 Interrupts Interrupts are generated by the GPIO pins, the internal timers, I2C operation, the internal USB hub, or on various USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a `1' to a bit position enables the interrupt associated with that bit position. During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts. 7 6 Reserved 5 R/W R/W I2C Interrupt Enable GPIO Interrupt Enable 4 3 1 0 R/W R/W R/W USB Hub Interrupt Enable Reserved 2 R/W 1.024-ms Interrupt Enable 128-µs Interrupt Enable USB Bus RST Interrupt Enable Figure 14-1. Global Interrupt Enable Register 0x20 (read/write) 7 6 Reserved Reserved 4 3 2 1 0 R/W Reserved 5 R/W R/W R/W R/W EPB1 Interrupt Enable EPB0 Interrupt Enable EPA2 Interrupt Enable EPA1 Interrupt Enable EPA0 Interrupt Enable Figure 14-2. USB Endpoint Interrupt Enable Register 0x21 (read/write) The interrupt controller contains a separate flip-flop for each interrupt. See Figure 14-3 for the logic block diagram of the interrupt controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction. When servicing an interrupt, the hardware first disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the Processor Status and Control Register). Second, the flip-flop of the current interrupt is cleared. This is followed by an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt Vector, see Section 14.1). The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited only by the available stack space. The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed. The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register). 14.1 Interrupt Vectors The Interrupt Vectors supported by the USB Controller are listed in Table 14-1. The lowest-numbered interrupt (USB Bus Reset interrupt) has the highest priority, and the highest-numbered interrupt (I2C interrupt) has the lowest priority. Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h-which corresponds to the first entry in the Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes. 24 CY7C65013 CY7C65013 CY7C65113 CY7C65113 USB Reset Clear CLR 1 Q D USB Reset Int Enable [0] (Reg 0x20) CLK CLR 1 Q D AddA ENP2 Int Enable [2] (Reg 0x21) CLK USB Reset IRQ 128-µs CLR 128-µs IRQ 1-ms CLR 1-ms IRQ AddA EP0 CLR AddA EP0 IRQ Interrupt Vector To CPU CPU IRQout IRQ AddA EP1 CLR AddA EP1 IRQ AddA EP2 CLR AddA EP2 IRQ AddB EP0 CLR AddB EP0 IRQ Global Interrupt Enable Bit AddB EP1 CLR AddB EP1 IRQ CLR Hub CLR Hub IRQ DAC CLR DAC IRQ IRQ Sense Int Enable Sense Controlled by DI, EI, and RETI Instructions Interrupt Acknowledge GPIO CLR GPIO IRQ I2C CLR CLR 1 I2C Int D Q Enable [6] (Reg 0x20) I2C IRQ Interrupt Priority Encoder CLK Figure 14-3. Interrupt Controller Functional Diagram Table 14-1. Interrupt Vector Assignments Interrupt Vector Number ROM Address Function Not Applicable 0x0000 Execution after Reset begins here 1 0x0002 USB Bus Reset interrupt 2 0x0004 128-µs timer interrupt 3 0x0006 1.024-ms timer interrupt 4 0x0008 USB Address A Endpoint 0 interrupt 5 0x000A USB Address A Endpoint 1 interrupt 6 0x000C USB Address A Endpoint 2 interrupt 7 0x000E USB Address B Endpoint 0 interrupt 8 0x0010 USB Address B Endpoint 1 interrupt 9 0x0012 USB Hub interrupt 10 0x0014 DAC interrupt 11 0x0016 GPIO interrupt 12 0x0018 I2C interrupt A pending address can be read from the Interrupt Vector Register (Figure 14-4). The value read from this register is only valid if the Global Interrupt bit has been disabled, by executing the DI instruction or in an Interrupt Service Routine before interrupts have been re-enabled. The value read from this register is the interrupt vector address; for example, a 0x12 indicates the hub interrupt is the highest priority pending interrupt. 25 CY7C65013 CY7C65013 CY7C65113 CY7C65113 7 6 Reserved Reserved 4 3 2 1 0 R Reserved 5 R R R R Interrupt Vector Bit 4 Interrupt Vector Bit 3 Interrupt Vector Bit 2 Interrupt Vector Bit 1 Reads `0' Figure 14-4. Interrupt Vector Register 0x23 (read only) 14.2 Interrupt Latency Interrupt latency can be calculated from the following equation: Interrupt latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) + (5 clock cycles for the JMP instruction) For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20 / 12 MHz = 1.667 µs. 14.3 USB Bus Reset Interrupt The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for 12­16 µs (the Reset may be recognized for an SE0 as short as 12 µs, but is always recognized for an SE0 longer than 16 µs). SE0 is defined as the condition in which both the D+ line and the D­ line are LOW. Bit 5 of the Status and Control Register is set to record this event. The interrupt is asserted at the end of the Bus Reset. If the USB reset occurs during the start-up delay following a POR, the delay is aborted as described in Section 7.1. The USB Bus Reset Interrupt is generated when the SE0 state is deasserted. A USB Bus Reset clears the following registers: SIE Section: Hub Section: USB Device Address Registers (0x10, 0x40) Hub Ports Connect Status (0x48) Hub Ports Enable (0x49) Hub Ports Speed (0x4A) Hub Ports Suspend (0x4D) Hub Ports Resume Status (0x4E) Hub Ports SE0 Status (0x4F) Hub Ports Data (0x50) Hub Downstream Force (0x51) 14.4 Timer Interrupt There are two periodic timer interrupts: the 128-µs interrupt and the 1.024-ms interrupt. The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend request first. 14.5 USB Endpoint Interrupts There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of the transaction (e.g., on the host's ACK during an IN, or on the device ACK during on OUT). If no ACK is received during an IN transaction, no interrupt is generated. 14.6 USB Hub Interrupt A USB hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by the USB repeater hardware. The babble and resume events are additionally gated by the corresponding bits of the Hub Port Enable Register (Figure 16-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive the port (i.e., the port is being forced). 26 CY7C65013 CY7C65013 CY7C65113 CY7C65113 14.7 GPIO Interrupt Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt logic is shown in Figure 14-5. Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts. If one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. Port Configuration Register OR Gate (1 input per GPIO pin) M U X GPIO Pin 1 = Enable 0 = Disable GPIO Interrupt Flip Flop 1 D Q CLR Interrupt Priority Encoder IRQout Interrupt Vector Port Interrupt Enable Register IRA 1 = Enable 0 = Disable Global GPIO Interrupt Enable (Bit 5, Register 0x20) Figure 14-5. GPIO Interrupt Structure I2C Interrupt 14.8 2 The I C interrupt occurs after various events on the I2C bus to signal the need for firmware interaction. This generally involves reading the I2C Status and Control Register (Figure 12-2) to determine the cause of the interrupt, loading/reading the I2C Data Register as appropriate, and finally writing the Status and Control Register to initiate the subsequent transaction. The interrupt indicates that status bits are stable and it is safe to read and write the I2C registers. Refer to Section 12.0 for details on the I2C registers. When enabled, the I2C state machines generate interrupts on completion of the following conditions. The referenced bits are in the I2C Status and Control Register. 1. In slave receive mode, after the slave receives a byte of data. The Addr bit is set if this is the first byte since a start or restart signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit Mode, and Continue bits appropriately for the next byte. 2. In slave receive mode, after a stop bit is detected. The Received Stop bit is set. If the stop bit follows a slave receive transaction where the ACK bit was cleared to 0, no stop bit detection occurs. 3. In slave transmit mode, after the slave transmits a byte of data. The ACK bit indicates if the master that requested the byte acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the Xmit Mode and Continue bits as required. 4. In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and set the Xmit Mode, MSTR Mode, and Continue/Busy bits appropriately. Clearing the MSTR Mode bit issues a stop signal to the I2C bus and return to the idle state. 5. In master receive mode, after the master receives a byte of data. Firmware should read the data and set the Ack and Continue/Busy bits appropriately for the next byte. Clearing the Master bit at the same time causes the master state machine to issue a stop signal to the I2C bus and leave the I2C hardware in the idle state. 6. When the master loses arbitration. This condition clears the Master bit and sets the Arbitration Lost bit immediately and then waits for a stop signal on the I2C bus to generate the interrupt. 27 CY7C65013 CY7C65013 CY7C65113 CY7C65113 The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written, firmware should configure the other control bits and set the Continue bit for subsequent transactions. Following an interrupt from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue bit, without checking the value of the Busy bit. The Busy bit may otherwise be active and I2C register contents may be changed by the hardware during the transaction, until the I2C interrupt occurs. 15.0 USB Overview The USB hardware includes a USB Hub repeater with one upstream and up to seven downstream ports. The USB Hub repeater interfaces to the microcontroller through a full-speed serial interface engine (SIE). An external series resistor of Rext must be placed in series with all upstream and downstream USB outputs in order to meet the USB driver requirements of the USB specification. The CY7C65x13 microcontroller can provide the functionality of a compound device consisting of a USB hub and permanently attached functions. 15.1 USB Serial Interface Engine (SIE) The SIE allows the CY7C65x13 microcontroller to communicate with the USB host through the USB repeater portion of the hub. The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller: · Bit stuffing/unstuffing · Checksum generation/checking · ACK/NAK/STALL · Token type identification · Address checking Firmware is required to handle the following USB interface tasks: · Coordinate enumeration by responding to SETUP packets · Fill and empty the FIFOs · Suspend/Resume coordination · Verify and select DATA toggle values 15.2 USB Enumeration The internal hub and any compound device function are enumerated under firmware control. The hub is enumerated first, followed by any integrated compound function. After the hub is enumerated, the USB host can read hub connection status to determine which (if any) of the downstream ports need to be enumerated. The following is a brief summary of the typical enumeration process of the CY7C65x13 by the USB host. For a detailed description of the enumeration process, refer to the USB specification. In this description, `Firmware' refers to embedded firmware in the CY7C65x13 controller. 1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor. 2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables. 3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB bus, via the on-chip FIFOs. 4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB address to the device. 5. Firmware stores the new address in its USB Device Address Register (for example, as Address B) after the no-data control sequence completes. 6. The host sends a request for the Device descriptor using the new USB address. 7. Firmware decodes the request and retrieves the Device descriptor from program memory tables. 8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus. 9. The host generates control reads from the device to request the Configuration and Report descriptors. 10.Once the device receives a Set Configuration request, its functions may now be used. 11.Following enumeration as a hub, Firmware can optionally indicate to the host that a compound device exists (for example, the keyboard in a keyboard/hub device). 12.The host carries out the enumeration process with this additional function as though it were attached downstream from the hub. 13.When the host assigns an address to this device, it is stored as the other USB address (for example, Address A). 28 CY7C65013 CY7C65013 CY7C65113 CY7C65113 16.0 USB Hub A USB hub is required to support: · Connectivity behavior: service connect/disconnect detection · Bus fault detection and recovery · Full-/Low-speed device support These features are mapped onto a hub repeater and a hub controller. The hub controller is supported by the processor integrated into the CY7C65x13 microcontrollers. The hardware in the hub repeater detects whether a USB device is connected to a downstream port and the interface speed of the downstream device. The connection to a downstream port is through a differential signal pair (D+ and D­). Each downstream port provided by the hub requires external RUDN resistors from each signal line to ground, so that when a downstream port has no device connected, the hub reads a LOW (zero) on both D+ and D­. This condition is used to identify the "no connect" state. The hub must have a resistor RUUP connected between its upstream D+ line and VREG to indicate it is a full speed USB device. The hub generates an EOP at EOF1, in accordance with the USB 1.1 Specification. 16.1 Connecting/Disconnecting a USB Device A low-speed (1.5 Mbps) USB device has a pull-up resistor on the D­ pin. At connect time, the bias resistors set the signal levels on the D+ and D­ lines. When a low-speed device is connected to a hub port, the hub sees a LOW on D+ and a HIGH on D­. This causes the hub repeater to set a connect bit in the Hub Ports Connect Status register for the downstream port. The hub repeater also sets a bit in the Hub Ports Speed register to indicate this port is low-speed (see Figure 16-1 and Figure 16-2). Then the hub repeater generates a Hub Interrupt to notify the microcontroller that there has been a change in the Hub downstream status. A full-speed (12 Mbps) USB device has a pull-up resistor from the D+ pin, so the hub sees a HIGH on D+ and a LOW on D­. In this case, the hub repeater sets a connect bit in the Hub Ports Connect Status register, clears a bit in the Hub Ports Speed register (for full-speed), and generates a Hub Interrupt to notify the microcontroller of the change in Hub status. Connects are recorded by the time a non-SE0 state lasts for more than 2.5 µs on a downstream port. When a USB device is disconnected from the Hub, the downstream signal pair eventually floats to a single-ended zero state. The hub repeater recognizes a disconnect once the SE0 state on a downstream port lasts from 2.0 to 2.5 µs. On a disconnect, the corresponding bit in the Hub Ports Connect Status register is cleared, and the Hub Interrupt is generated. 7 6 5 4 3 2 1 0 Reserved Port 7 Connect Status Port 6 Connect Status Port 5 Connect Status Port 4 Connect Status Port 3 Connect Status Port 2 Connect Status Port 1 Connect Status Figure 16-1. Hub Ports Connect Status 0x48 (read/write), 1 = Connect, 0 = Disconnect The Hub Ports Connect Status register is cleared to zero by reset or bus reset, then set to match the hardware configuration by the hub repeater hardware. The Reserved bit [7] should always read as `0' to indicate no connection. 7 6 5 4 3 2 1 0 Reserved Port 7 Speed Port 6 Speed Port 5 Speed Port 4 Speed Port 3 Speed Port 2 Speed Port 1 Speed Figure 16-2. Hub Ports Speed 0x4A (read/write), 1 = Low-Speed, 0 = Full-Speed The Hub Ports Speed register is cleared to zero by reset or bus reset, then set to match the hardware configuration whenever a connect occurs. Firmware may write this register if desired, to allow for firmware debouncing of the speed detection. The Reserved bit [7] should always read as `0.' 16.2 Enabling/Disabling a USB Device After a USB device connection has been detected, firmware must update status change bits in the hub status change data structure that is polled periodically by the USB host. The host responds by sending a packet that instructs the hub to reset and enable the downstream port. Firmware then sets the bit in the Hub Ports Enable register, Figure 16-3, for the downstream port. The hub repeater hardware responds to an enable bit in the Hub Ports Enable register by enabling the downstream port, so that USB traffic can flow to and from that port. 29 CY7C65013 CY7C65013 CY7C65113 CY7C65113 If a port is marked enabled and is not suspended, it receives all USB traffic from the upstream port, and USB traffic from the downstream port is passed to the upstream port (unless babble is detected). Low-speed ports do not receive full-speed traffic from the upstream port. When firmware writes to the Hub Ports Enable register to enable a port, the port is not enabled until the end of any packet currently being transmitted. If there is no USB traffic, the port is enabled immediately. When a USB device disconnection has been detected, firmware must update status bits in the hub change status data structure that is polled periodically by the USB host. In suspend, a connect or disconnect event generates an interrupt (if the hub interrupt is enabled) even if the port is disabled. 7 6 5 4 3 2 1 0 Reserved Port 7 Enable Port 6 Enable Port 5 Enable Port 4 Enable Port 3 Enable Port 2 Enable Port 1 Enable Figure 16-3. Hub Ports Enable Register 0x49 (read/write), 1 = Enabled, 0 = Disabled The Hub Ports Enable register is cleared to zero by reset or bus reset to disable all downstream ports as the default condition. A port is also disabled by internal hub hardware (enable bit cleared) if babble is detected on that downstream port. Babble is defined as: · Any non-idle downstream traffic on an enabled downstream port at EOF2 · Any downstream port with upstream connectivity established at EOF2 (i.e., no EOP received by EOF2) 16.3 Hub Downstream Ports Status and Control Data transfer on hub downstream ports is controlled according to the bit settings of the Hub Downstream Ports Control Register (Figure 16-4). Each downstream port is controlled by two bits, as defined in Table 16-1 below. The Hub Downstream Ports Control Register is cleared upon reset or bus reset, and the reset state is the state for normal USB traffic. Any downstream port being forced must be marked as disabled (Figure 16-3) for proper operation of the hub repeater. Firmware should use this register for driving bus reset and resume signaling to downstream ports. Controlling the port pins through this register uses standard USB edge rate control according to the speed of the port, set in the Hub Port Speed Register. The downstream USB ports are designed for connection of USB devices, but can also serve as output ports under firmware control. This allows unused USB ports to be used for functions such as driving LEDs or providing additional input signals. Pulling up these pins to voltages above V REF may cause current flow into the pin. This register is not reset by bus reset. These bits must be cleared before going into suspend. 7 6 5 4 3 2 1 0 Port 4 Control Bit 1 Port 4 Control Bit 0 Port 3 Control Bit 1 Port 3 Control Bit 0 Port 2 Control Bit 1 Port 2 Control Bit 0 Port 1 Control Bit 1 Port 1 Control Bit 0 Figure 16-4. Hub Downstream Ports Control Register 0x4B (read/write) Table 16-1. Control Bit Definition for Downstream Ports Control Bits: Bit1 Bit 0 Control Action 0 0 Not Forcing (Normal USB Function) 0 1 Force Differential `1' (D+ HIGH, D­ LOW) 1 0 Force Differential `0' (D+ LOW, D­ HIGH) 1 1 Force SE0 state An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register (Figure 16-5) and Hub Ports Force High Register (Figure 16-6). With these registers the pins of the downstream ports can be individually forced LOW, or left unforced. Unlike the Hub Downstream Ports Control Register, above, the Force Low Register does not produce standard USB edge rate control on the forced pins. However, this register allows downstream port pins to be held LOW in suspend. This register can be used to drive SE0 on all downstream ports when unconfigured, as required in the USB 1.1 specification. 30 CY7C65013 CY7C65013 CY7C65113 CY7C65113 7 6 5 4 3 2 1 0 Force Low DD4 D+ Force Low DD4 D­ Force Low DD3 D+ Force Low DD3 D­ Force Low DD2 D+ Force Low DD2 D­ Force Low DD1 D+ Force Low DD1 D­ Figure 16-5. Hub Ports Force Low Register (read/write) 0x51, 1 = Force Low, 0 = No Force 7 6 5 4 3 2 1 0 Reserved Reserved Force High DD7 D+ Force High DD7 D­ Force High DD6 D+ Force High DD6 D­ Force High DD5 D+ Force High DD5 D­ Figure 16-6. Hub Ports Force High Register (read/write) 0x52, 1=Force High, 0=No Force The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 16-7) and the Hub Ports Data Register (Figure 16-8). The data read from the Hub Ports Data Register is the differential data only and is not dependent on the settings of the Hub Ports Speed Register (Figure 16-2). When the SE0 condition is sensed on a downstream port, the corresponding bits of the Hub Ports Data Register hold the last differential data state before the SE0. Hub Ports SE0 Status Register and Hub Ports Data Register are cleared upon reset or bus reset. 7 6 5 4 3 2 1 0 Reserved Port 7 SE0 Status Port 6 SE0 Status Port 5 SE0 Status Port 4 SE0 Status Port 3 SE0 Status Port 2 SE0 Status Port 1 SE0 Status Figure 16-7. Hub Ports SE0 Status Register 0x4F (read only), 1 = SE0, 0 = Non-SE0 7 6 5 4 3 2 1 0 Reserved Port 7 Diff. Data Port 6 Diff. Data Port 5 Diff. Data Port 4 Diff. Data Port 3 Diff. Data Port 2 Diff. Data Port 1 Diff. Data Figure 16-8. Hub Ports Data Register 0x50 (read only), 1 = (D+ > D­), 0 = (D+ < D­) 16.4 Downstream Port Suspend and Resume The Hub Ports Suspend Register (Figure 16-9) and Hub Ports Resume Status Register (Figure 16-10) indicate the suspend and resume conditions on downstream ports. The suspend register must be set by firmware for any ports that are selectively suspended. Also, this register is only valid for ports that are selectively suspended. If a port is marked as selectively suspended, normal USB traffic is not sent to that port. Resume traffic is also prevented from going to that port, unless the Resume comes from the selectively suspended port. If a resume condition is detected on the port, hardware reflects a Resume back to the port, sets the Resume bit in the Hub Ports Resume Register, and generates a hub interrupt. If a disconnect occurs on a port marked as selectively suspended, the suspend bit is cleared. The Device Remote Wakeup bit (bit 7) of the Hub Ports Suspend Register controls whether or not the resume signal is propagated by the hub after a connect or a disconnect event. If the Device Remote Wakeup bit is set, the hub will automatically propagate the resume signal after a connect or a disconnect event. If the Device Remote Wakeup bit is cleared, the hub will not propagate the resume signal. The setting of the Device Remote Wakeup flag has no impact on the propagation of the resume signal after a downstream remote wakeup event. The hub will automatically propagate the resume signal after a remote wakeup event, regardless of the state of the Device Remote wakeup bit. The state of this bit has no impact on the generation of the hub interrupt. A resume bit is set automatically when hardware detects a resume condition on a selectively suspended downstream port. The resume condition is a differential `1' for a low-speed device and a differential `0' for a full-speed device. These registers are cleared on reset or bus reset. 7 6 5 4 3 2 1 0 Device Remote Wakeup Port 7 Selective Suspend Port 6 Selective Suspend Port 5 Selective Suspend Port 4 Selective Suspend Port 3 Selective Suspend Port 2 Selective Suspend Port 1 Selective Suspend Figure 16-9. Hub Ports Suspend Register 0x4D (read/write), 1 = Port is Selectively Suspended 31 CY7C65013 CY7C65013 CY7C65113 CY7C65113 7 6 5 4 3 2 1 0 Reserved Resume 7 Resume 6 Resume 5 Resume 4 Resume 3 Resume 2 Resume 1 Figure 16-10. Hub Ports Resume Status Register 0x4E (read only), 1 = Port is in Resume State Resume from a selectively suspended port, with the hub not in suspend, typically involves these actions: