CY7C53150 CY7C53120 CY7C53120E2 CY7C53120E4 10-KB 12-KB TMPN3150B1 MC143120E2 - Datasheet Archive
CY7C53120 PRELIMINARY Neuron® Chip Network Processor Features Functional Description · Three 8-bit pipelined
CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY Neuron® Chip Network Processor Features Functional Description · Three 8-bit pipelined processors for concurrent processing of application code and network traffic · 11-pin I/O port programmable in 34 modes for fast application program development · Two 16-bit timer/counters for measuring and generating I/O device waveforms · 5-pin communication port that supports direct connect and network transceiver interfaces · Programmable pull-ups on IO4IO7 and 20-mA sink current on IO0IO3 · Unique 48-bit ID number in every device to facilitate network installation and management · Low operating current. Sleep mode operation for reduced current consumption · 0.35 µm Flash process technology · 5.0V operation · On-chip LVD circuit to prevent non-volatile memory corruption during voltage drops · 2048 bytes of SRAM for buffering network data, system, and application data storage · 3072 bytes (CY7C53150 CY7C53150), 2048 bytes (CY7C53120E2 CY7C53120E2), 4096 bytes (CY7C53120E4 CY7C53120E4) of EEPROM memory with on-chip charge pump for flexible storage of configuration data and application code · Addresses up to 58 KB of external memory (CY7C53150 CY7C53150) · 10 KB (CY7C53120E2 CY7C53120E2), 12 KB (CY7C53120E4 CY7C53120E4) of ROM containing LonTalk® network protocol firmware · Maximum input clock operation of 20 MHz (CY7C53150 CY7C53150), 10 MHz (CY7C53120E2 CY7C53120E2), 40 MHz (CY7C53120E4 CY7C53120E4) over a 40 to 85×C temperature range · 64-pin TQFP package (CY7C53150 CY7C53150) · 32-pin SOIC or 44-pin TQFP package (CY7C53120 CY7C53120) The CY7C531x0 Neuron® Chip implements a node for LonWorks® distributed intelligent control networks. It incorporates, on a single chip, the necessary communication and control functions, both in hardware and firmware, that facilitate the design of a LonWorks node. The CY7C531x0 contains a very flexible 5-pin communication port, that can be configured to interface to a wide variety of media transceivers at a wide range of data rates. The most common transceiver types are: twisted-pair, powerline, RF, IR, fiber-optics, and coaxial. The CY7C531x0 is manufactured using the state-of-the-art 0.35-mm Flash technology, providing to the designers the most cost-effective Neuron Chip solution. Services at every layer of the OSI networking reference model are implemented in the LonTalk firmware-based protocol stored in the 10-KB 10-KB ROM (CY7C53120E2 CY7C53120E2), 12-KB 12-KB ROM (CY7C53120E4 CY7C53120E4), or off-chip memory (CY7C53150 CY7C53150). The firmware also contains 34 preprogrammed I/O drivers, greatly simplifying application programming. The application program is stored in the EEPROM memory (CY7C53120 CY7C53120), and/or off-chip memory (CY7C53150 CY7C53150), and may be updated by downloading over the network. The CY7C53150 CY7C53150 incorporates an external memory interface, which can address up to 64 KB, with 6 KB of the address space being mapped internally. LonWorks nodes that require large application programs can take advantage of this external memory capability. The CY7C53150 CY7C53150 Neuron Chip is an exact replacement for the Motorola MC143150Bx and Toshiba TMPN3150B1 TMPN3150B1 devices. The CY7C53120E2 CY7C53120E2 Neuron Chip is an exact replacement for the Motorola MC143120E2 MC143120E2 device, since it contains the same firmware in ROM. Logic Block Diagram Communications Port Network Processor Internal Data Bus (0:7) Application Processor IO10 IO0 2 Timer/ Counters Internal Address Bus (0:15) 2 KB RAM CP4 CP0 I/O Block Media Access Control Processor CLK1 CLK2 SERVICE RESET Oscillator, Clock, and Control EEPROM External Address/Data Bus (CY7C53150 CY7C53150) ROM (CY7C53120 CY7C53120) Echelon, LonWorks, LonTalk, and Neuron are registered trademarks of Echelon Corporation Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 October 6, 2000 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY . Pin Configurations Pin 1 Indicator  D7 D2 D3 D4 D5 D6 VDD VSS D0 D1 VDD Notes: 1. The larger dimple at the bottom left of the marking indicates pin 1. 2. NC (No Connect) - Should not be used. (These pins may be used for internal testing.) 2 IO10 A1 A0 Vss Vpp IO4 IO5 IO6 IO7 IO8 IO9 A4 A3 A2 IO2 IO3 RESET VDD A8 A7 A6 A5 IO0 IO1 A13 A12 A11 A10 A9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 CY7C53150-20AI CY7C53150-20AI 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC NC A14 A15 E R/W VDD NC  CY7C53150 CY7C53150 64-Lead Thin Quad Flat Pack CP4 CP3 CP2 CP1 CP0 NC VDD VSS CLK1 CLK2 VDD VSS VDD VSS NC SERVICE CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY Pin Configurations IO8 IO9 VDD NC* IO10 VSS CP4 31 30 29 28 27 26 25 NC IO7 32 CP3 NC 33 44-Lead QFP 23 24 NC 34 22 NC IO6 35 21 CP1 IO5 36 20 CP0 VSS 37 19 VDD VDD 38 18 CP2  39 17 NC RESET 40 16 VSS VDD 41 15 CLK1 IO4 42 14 CLK2 IO3 43 13 VSS  44 12 NC 8 9 Vpp VDD 11 7 VSS 10 6 NC VDD 5 NC* 4 IO0 SERVICE PIN 1 INDICATOR 3 NC 2 NC CY7C53120Ex-yyAI IO1 V DD VSS IO5 IO6 IO7 IO8 IO9 VDD IO10 VSS CP4 CP3 CP1 CP0 VDD CP2 IO2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC* RESET VDD IO4 IO3 IO2 IO1 IO0 SERVICE VSS Vpp VDD VDD VSS CLK2 CLK1 VSS CY 7C53120E 7C53120E x-yyS I 32-Lead SOIC also be downloaded and updated over the LonTalk network from an external network management tool. Memory Usage All Neuron Chips require system firmware to be present when they are powered up. In the case of the CY7C53120 CY7C53120 family, this firmware is pre-programmed in the factory in an on-board ROM. In the case of the CY7C53150 CY7C53150, the system firmware must be present in the first 16KB of an off-board non-volatile memory such as flash, EPROM, EEPROM, or NVRAM. These devices must be programmed in a device programmer before board assembly. Because the system firmware implements the network protocol, it cannot itself be downloaded over the network. EEPROM Retention and Endurance Data and code stored in EEPROM is guaranteed to be retained for at least 10 years after being written. If it is desired to extend the guaranteed retention time, EEPROM contents may be periodically refreshed. The system firmware supports EEPROM refreshing under software control and also by an external network management tool. EEPROM may be written up to 10,000 times with no data loss. An erase/write cycle takes 20 msec. The system firmware extends the effective endurance of EEPROM in two ways. If the data being written to a byte of EEPROM is the same as the data already present in that byte, the firmware does not perform the physical write. So for example, an application that sets its own address in EEPROM after every reset will not use up any write cycles if the address has not changed. In addition, system firmware version 12 or higher is able to aggregate writes to 8 successive address locations into a single write. So for example, if 4 KB of code is downloaded over the network, the firmware would execute only 512 writes rather than 4,096. For the CY7C53120 CY7C53120 family, the user application program is stored in on-board EEPROM memory. It may be programmed using a device programmer before board assembly, or may be downloaded and updated over the LonTalk network from an external network management tool. For the CY7C53150 CY7C53150, the user application program is stored in on-board EEPROM and also in off-chip memory. The user program may initially be programmed into the off-chip memory device using a device programmer. If the external memory device is writeable (e.g. flash), the user application program may 3 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY . Pin Descriptions Pin Name CY7C53150 CY7C53150 TQFP-64 TQFP-64 Pin No. CY7C53120xx SOIC-32 SOIC-32 Pin No. CY7C53120xx TQFP-44 TQFP-44 Pin No. I/O Pin Function CLK1 Input Oscillator connection or external clock input. 24 15 15 CLK2 Output Oscillator connection. Leave open when external clock is input to CLK1. One Load. 23 14 14 RESET I/O (Built-In Pull-up) Reset pin (active LOW). 6 1 40 SERVICE I/O (Built-In Configurable Pull-up) Service pin (active LOW). Alternates between input and output at a 76 Hz rate. 17 8 5 IO0IO3 I/O Large current-sink capacity (20 mA). General I/O port. The output of timer/counter 1 may be routed to IO0. The output of timer/counter 2 may be routed to IO1. 2, 3, 4, 5 7, 6, 5, 4 4, 3, 2, 43 IO4IO7 I/O (Built-In Configurable Pull-ups) General I/O port. The input to timer/counter 1 may be derived from one of IO4IO7. The input to timer/counter 2 may be derived from IO4. 10, 11, 12, 13 3, 30, 29, 28 42, 36, 35, 32 IO8IO10 I/O General I/O port. May be used for serial communication under firmware control. 14, 15, 16 27, 26, 24 31, 30, 27 D0D7 I/O Bi-directional memory data bus. 43, 42, 38, 37, 36, 35, 34, 33 N/A N/A R/W Output Read/write control output for external memory. 45 N/A N/A E Output Enable clock control output for external memory. 46 N/A N/A A0A15 Output Memory address output port. 47, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 N/A N/A 7, 20, 22, 26, 40, 41, 44 2, 11, 12, 18, 25, 32 9, 10, 19, 29, 38, 41 VDD Input Power input (5 V nom). All VDD pins must be connected together externally. VSS Input Power input (0 V, GND). All VSS pins must be connected together externally. Vpp Input In-circuit test mode control. If Vpp is high when RESET is asserted, the I/O, address and data buses become Hi-Z. 9 10 8 Communication Network Interface Bidirectional port supporting communications in three modes. 28, 29, 30, 31, 32 19, 20, 17, 21, 22 20, 21, 18, 24, 25 - No connect. Must not be connected on the user's PC board, since they may be connected internal to the chip. 1, 18, 27, 48, 49 N/A 1, 6, 11, 12, 17, 22, 23, 28, 33, 34, 39, 44 CP0CP4 NC 4 8,19, 21, 25, 39 9, 13, 16, 23, 31 7,13, 16, 26, 37 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY Electrical Characteristics (VDD = 4.55.5V) Parameter Description Min. Typ. Max. VIL Input Low Voltage IO0IO10, CP0, CP3, CP4, SERVICE, D0-D7 CP0, CP1 (Differential) RESET - - - - - - 0.8 Programmable 0.3 VDD VIH Input High Voltage IO0IO10, CP0, CP3, CP4, SERVICE, D0-D7 CP0, CP1 (Differential) RESET 2.0 Programmable VDD 0.7 - - - - - - VOL Low-Level Output Voltage Iout < 20 µA Standard Outputs (IOL = 1.4 mA) High Sink (IO0IO3), SERVICE, RESET (IOL = 20 mA) High Sink (IO0IO3), SERVICE, RESET (IOL = 10 mA) Maximum Sink (CP2, CP3) (IOL = 40 mA) Maximum Sink (CP2, CP3) (IOL = 15 mA) - - - - - - - - - - - - 0.1 0.4 0.8 0.4 1.0 0.4 VOH High-Level Output Voltage Iout < 20 µA Standard Outputs (IOH = 1.4 mA) High Sink (IO0 IO3), SERVICE (IOH = 1.4 mA) Maximum Source (CP2, CP3) (IOH = 40 mA) Maximum Source (CP2, CP3) (IOH = 15 mA) - - - - - - - - - - Vhys Hysteresis (Excluding CLK1, RESET) Iin Input Current (Excluding Pull-Ups) (VSS to VDD) Unit Ipu V V V VDD VDD VDD VDD VDD Operating Mode Supply Current IDDsleep Sleep Mode Supply Current[5, 6] - mV - ±10 µA 70 - 210 µA - - TBD TBD 55 30 mA - 40 MHz Clock 20 MHz Clock - - Pull-Up Source Current (Vout = 0 V, Output = High-Z) IDD 0.1 0.4 0.4 1.0 0.4 175  [5, 6] V TBD 100 µA Notes: 3. FStandard outputs are IO4IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < 15 pF load.) For CY7C53150 CY7C53150, standard outputs also include A0-A15 A0-A15, D0-D7, E, and R/W. 4. IO4IO7 and SERVICE have configurable pull-ups. RESET has a permanent pull-up. 5. Supply current measurement conditions: all outputs under no-load conditions, all inputs < 0.2V or > (VDD 0.2V), configurable pull-ups off, crystal oscillator clock input, differential receiver disabled. The differential receiver adds approximately 200 µA typical and 600 µA maximum when enabled. It is enabled on either of the following conditions: · Neuron Chip in Operating mode and Comm Port in Differential mode. · Neuron Chip in Sleep mode and Comm Port in Differential mode and Comm Port Wake Up not masked. 6. Typical values are at midpoint of supply voltage range and 25°C only. 5 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY LVI Trip Point (VDD) Part Number Min. Max. Unit 3.8 CY7C53120E2 CY7C53120E2, CY7C53120E4 CY7C53120E4, and CY7C53150 CY7C53150 Typ. 4.1 4.4 V External Memory Interface Timing - CY7C53150 CY7C53150, VDD ± 10% (VDD = 4.5 to 5.5 V, TA = 40 to+ 85°C) Parameter Description Min.  tcyc Memory Cycle Time (System Clock Period) PWEH Pulse Width, E High PWEL Pulse Width, E Low tAD Delay, E High to Address Valid Max. Unit 100 ns tcyc/2 + 5 ns tcyc/2 5 tcyc/2 + 5 ns -  3200 tcyc/2 5 24 ns tAH Address Hold Time After E High  10 - ns tRD Delay, E High to R/W Valid Read - 14 ns tRH R/W Hold Time Read After E High 10 - ns tWR Delay, E High to R/W Valid Write - 14 ns tWH R/W Hold Time Write After E High 10 - ns tDSR Read Data Setup Time to E High - 6 ns tDHR Data Hold Time Read After E High 0 - ns 10 - ns [9, 10] tDHW Data Hold Time Write After E High tDDW Delay, E Low to Data Valid - 12 ns tDHZ Data Three State Hold Time After E Low 6 - ns - 10 ns - 70 ns  tDDZ Delay, E High to Data Three-State tacc External Memory Access Time (tacc = tcyc tAD tDSR) at 20-MHz input clock Notes: 7. t cyc = 2²1/f, where f is the input clock (CLK1) frequency (20, 10, 5, 2.5, 1.25, or 0.625 MHz). 8. Refer to Figure 3 for detailed measurement information. 9. The data hold parameter, t DHW, is measured to the disable levels shown in Figure 7, rather than to the traditional data invalid levels. 10. Refer to Figure 6 and Figure 7 for detailed measurement information. 11. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information. 12. Loading on A0-A15 A0-A15, D0-D7, and R/W is 30pF. Loading on E is 20pF. 6 tcyc E 20 pF Load PWEL tAD tAD tAD Address tAD Address tAH Address PRELIMINARY 7 Figure 1. External Memory Interface Timing Diagram Address (A0 A15) 30 pF Load PWEH Address tAH tAH tAH tWR tRD R/W 30 pF Load tRH tDSR tDSR Data (In) (D0 D7) tWH Data In Data In tDHR Data (Out) (D0 D7) 30 pF Load tDHR tDDZ tDDW tDHZ tDDW tDHW tDHW Data Out Memory READ Memory READ Memory WRITE tDDZ tDHZ Data Out Memory WRITE CY7C53150 CY7C53150 CY7C53120 CY7C53120 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY TEST SIGNAL CL = 20 pF for E CL = 30 pF for A0-A15 A0-A15, D0-D7, and R/W CL CL = 50 pF for all other signals Figure 2. Signal Loading for Timing Specifications Unless Otherwise Specified PWEH PWEL 2.0V 2.0V 0.8V Figure 3. Test Point Levels for E Pulse Width Measurements DRIVE TO 2.4V 2.0V 0.8V DRIVE TO 0.4V A B 2.0V 0.8V A - Signal valid-to-signal valid specification (maximum or minimum) B - Signal valid-to-signal invalid specification (maximum or minimum) Figure 4. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified Pin under test in High-Z and pulled to VDD VDD 0.5V Pin under test in High-Z and pulled to VSS VSS + 0.5 Pin under test driving to a LOW state Pin under test driving to a HIGH state Figure 5. Test Point Levels for Three-State-to-Driven Time Measurements VDD/2 TEST SIGNAL ILOAD = 1.4 mA CL = 50 pF Figure 6. Signal Loading for Driven-to-Three-State Time Measurements VOH 0.5 V VOL + 0.5 V VOH Measured high output drive level VOL Measured low output drive level Figure 7. Test Point Levels for Driven-to-Three-State Time Measurements 8 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY Communications Port Programmable Glitch Filter Values (Receiver The Neuron Chip includes a versatile 5-pin communications port that can be configured in three different ways. In Single-Ended Mode, pin CP0 is used for receiving serial data, pin CP1 for transmitting serial data, and pin CPU2 enables an external transceiver. Data is communicated using Differential Manchester encoding. (end-to-end) filter values expressed as transient pulse suppression times) Filter (F) 10 75 140 ns 410 700 ns 2 240 800 1350 ns 480 1500 2600 ns 3 Receiver 0.027 VDD Filter (F) Max (tPLH tPHL ) Unit 0 35 ns 1 150 ns 2 250 ns 3 400 ns 0.035 VDD 1 0.040 VDD 0.054 VDD 0.068 VDD 2 0.061 VDD 0.081 VDD 0.101 VDD 3 0.081 VDD 0.108 VDD 0.135 VDD 4 0.101 VDD 0.135 VDD 0.169 VDD 5 0.121 VDD 0.162 VDD 0.203 VDD 6 0.142 VDD 0.189 VDD 0.236 VDD 7 0.162 VDD 0.216 VDD (End-to-End) Absolute Asymmetry Vhys Max. 0.019 VDD  (Worst case across hysteresis) ferential peak-to-peak voltages in terms of VDD) 0 Unit 120 Programmable Hysteresis Values (Expressed as difVhys Typ. Max. 1 In Differential Mode, pins CP0 and CP1 form a differential receiver with built-in programmable hysteresis and low-pass filtering. Pins CP2 and CP3 form a differential driver. Serial data is communicated using Differential Manchester encoding. The following tables describe the communications port when used in Differential Mode. Vhys Min. Typ. 0 In Special Purpose Mode, pin CP0 is used for receiving serial data, pin CP1 for transmitting serial data, pin CP2 transmits a bit clock,and pin CP4 transmits a frame clock for use by an external intelligent transceiver. In this mode, the external transceiver is responsible for encoding and decoding the data stream. Hysteresis Min. 0.270 VDD CP0 CP1 Vhys + 200 mV CP0 VDD /2 CP1 3 ns Figure 8. Receiver Input Waveform Differential Receiver (End-to-End) Absolute Symmetry[16, 17] Filter (F) Hysteresis (H) Max (tPLH tPHL) Unit 0 0 24 ns Notes: 13. Hysteresis values are under the conditions that the inout signal swing is 200 mV greater than the programmed value. 14. Must be disabled if data rate is 1.25 Mbps or greater. 15. Receiver inout, VD = VCP0 VCP1, at least 200 mV greater than hysteresis levels. See Figure 8. 16. CP0 and CP1 inputs each 0.60 Vp p, 1.25 MHz sine wave 180° out of phase with each other as shown in Figure 9. VDD = 5.00 V + 5%. 17. tPLH: Time from input switching states from low to high to output switching states. tPHL: Time from input switching states from high to low to output switching states. 9 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY 5 4 V (C P 0 ) 3 Vcm V (C P 1 ) 2 V (C P 0 )-V (C P 1 ) 1 T im e V t rip + Vh V t rip -1 5V N e u ro n C h ip 's In te rn a l C o m p a ra t o r 0V C o m m o n -M o d e v o lt a g e : V c m = ( V (C P 0 ) + V (C P 1 ) ) / 2 H y s te re s is V o lta g e : V h = [ V trip + ] - [V trip -] Figure 9. Differential Receiver Input Hysteresis Voltage Measurement Waveforms Differential Transceiver Electrical Characteristics Characteristic Min.  Receiver Common Mode Voltage Range to maintain hysteresis Receiver Common Mode Range to operate with unspecified hysteresis Max. Unit 1.2 VDD 2.2 V 0.9 VDD 1.75 V 0.05V hys 35 0.05Vhys + 35 mV Propagation Delay (F = 0, VID = Vhys/2 + 200 mV) Input Resistance - 230 ns ns 5 - M Wake-Up Time - 10 µs Input Offset Voltage 18. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs. 10 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY CY7C53150 CY7C53150 Pad Layout CY7C53150 CY7C53150 64-Lead Thin Quad Flat Pack 0.5 mm WIDTH 0.8 mm PITCH 1.7 mm 14.0 mm ± 0.1 mm 17.7 mm ± 0.1 mm 11 CY7C53150 CY7C53150 CY7C53120 CY7C53120 PRELIMINARY CY7C53120 CY7C53120 Pad Layout CY7C53120 CY7C53120 PAD LAYOUTS SOIC-32 SOIC-32 32-Lead SOIC TQFP-44 TQFP-44 44-Lead Thin Quad Flat Pack 0.5 mm 0.8 mm WIDTH PITCH 11.3 mm ± 0.1 mm 15.1 mm 1.8 mm 0.6 mm WIDTH 21.1 mm ± 0.1 mm 10 mm ± 0.1 1.27 mm PITCH 14.5 mm ± 0.1 mm 1.75 mm Ordering Information  EEPROM (kB) Part Number ROM (kB) Firmware Version Max. Input Clock (MHz) Package Type CY7C53150-20AI CY7C53150-20AI 3 0 N/A A65 64-Lead Thin Plastic Quad Flat Pack CY7C53120E2-10SI CY7C53120E2-10SI 2 10 6 10 S34 32-Lead (450 mil) Molded SOIC CY7C53120E4-40SI CY7C53120E4-40SI 4 12 12 40 S34 32-Lead (450 mil) Molded SOIC CY7C53120E2-10AI CY7C53120E2-10AI 2 10 6 10 A44 44-Lead Thin Plastic Quad Flat Pack  4 12 12 40 A44 44-Lead Thin Plastic Quad Flat Pack CY7C53120E4-40AI CY7C53120E4-40AI 20  Package Name Notes: 19. All parts contain 2KB of SRAM. 20. CY7C53120E2 CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 MC143120E2 firmware 21. CY7C53150 CY7C53150 may be used with 20 MHz input clock only if the firmware in external memory is version 12 or later 22. CY7C53120E4 CY7C53120E4 requires upgraded LonBuilder and NodeBuilder software Document #: 3800891B 12 PRELIMINARY CY7C53150 CY7C53150 CY7C53120 CY7C53120 D Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 51-85046-B 51-85046-B 13 PRELIMINARY CY7C53150 CY7C53150 CY7C53120 CY7C53120 Package Diagrams (continued) 32-Lead (450 MIL) Molded SOIC S34 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.