7C372 CY7C372 CY7C371 FLASH370 22V10 I/O8-I/O15 I/O24-I/O31 I/O16-I/O23 - Datasheet Archive
Revision: October 19, 1995 CY7C372 UltraLogict 64Macrocell Flash CPLD Features D D D D D D D D Functional Description 64
7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 UltraLogict 64Macrocell Flash CPLD Features D D D D D D D D Functional Description 64 macrocells in four logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins No hidden delays High speed fMAX = 125 MHz tPD = 10 ns tS = 5.5 ns tCO = 6.5 ns Electrically alterable Flash technology Available in 44pin PLCC and CLCC packages Pin compatible with the CY7C371 CY7C371 (PIM). The PIM brings flexibility, rout ability, speed, and a uniform delay to the interconnect. The CY7C372 CY7C372 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370t family of high density, highspeed CPLDs. Like all mem bers of the FLASH370 FLASH370 family, the CY7C372 CY7C372 is designed to bring the ease of use and high performance of the 22V10 22V10 to high density CPLDs. Like all members of the FLASH370 FLASH370 family, the CY7C372 CY7C372 is rich in I/O resources. Ev ery two macrocells in the device feature an associated I/O pin, resulting in 32 I/O pins on the CY7C372 CY7C372. In addition, there are four dedicated inputs and two input/clock pins. The 64 macrocells in the CY7C372 CY7C372 are di vided between four logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. Finally, the CY7C372 CY7C372 features a very sim ple timing model. Unlike other highdensi ty CPLD architectures, there are no hid den speed delays such as fanout effects, in terconnect delays, or expander delays. Re gardless of the number of resources used. or the type of application, the timing pa rameters on the CY7C372 CY7C372 remain the same. The logic blocks in the FLASH370 FLASH370 architec ture are connected with an extremely fast and predictable routing resourcethe Programmable Interconnect Matrix Logic Block Diagram INPUTS CLOCK INPUTS 4 2 INPUT/CLOCK INPUT MACROCELLS MACROCELLS 2 8 I/Os 2 LOGIC I/O0-I/O7 36 PIM D 16 16 LOGIC 8 I/Os LOGIC 36 BLOCK I/O8-I/O15 I/O8-I/O15 I/O24-I/O31 I/O24-I/O31 BLOCK A 8 I/Os 8 I/Os LOGIC 36 BLOCK 36 BLOCK B I/O16-I/O23 I/O16-I/O23 C 16 16 16 16 7c3721 Selection Guide 7C372-125 7C372-125 7C372-100 7C372-100 7C372-83 7C372-83 7C372-66 7C372-66 7C372L-66 7C372L-66 Maximum Propagation Delay, tPD (ns) 10 12 15 20 20 Minimum Setup, tS (ns) 5.5 6.0 8 10 10 Maximum Clock to Output, tCO (ns) 6.5 6.5 8 10 10 Maximum Supply Current, Current ICC (mA) 280 250 250 250 125 300 300 Commercial Military/Industrial Shaded area contains preliminary information. Cypress Semiconductor Corporation D 3901 North First Street 1 D San Jose D CA 95134 D 408-943-2600 December 1992 - Revised October 1995 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 28 29 30 31 term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are com mon to more than one output can be implemented in a single prod uct term. Product term steering and product term sharing help to increase the effective density of the FLASH370 FLASH370 PLDs. Note that product term allocation is handled by software and is invisible to the user. I/O I/O I/O CC I/O 1 0 GND 2 V I/O 3 2 I/O 4 1 I/O 5 3 I/O 6 4 I/O Pin Configuration 44 43 42 41 40 I/O5 7 39 I/O27 I/O27 I/O6 8 38 I/O26 I/O26 I/O Macrocell I/O7 9 37 I/O25 I/O25 10 36 I/O24 I/O24 11 Half of the macrocells on the CY7C372 CY7C372 have separate I/O pins associated with them. In other words, each I/O pin is shared by two macrocells. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has po larity control, and two global clocks to trigger the register. The I/O macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. I0 I1 35 CLK1/I5 12 34 GND CLK0/I2 13 33 I4 I/O8 14 32 I3 I/O9 15 31 I/O23 I/O23 I/O10 I/O10 16 30 I/O22 I/O22 I/O11 I/O11 17 29 I/O21 I/O21 GND I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 CC GND V I/O 15 I/O 13 I/O 14 I/O 12 18 19 20 21 22 23 24 25 26 27 28 Buried Macrocell 7c3722 The buried macrocell is very similar to the I/O macrocell. Again, it includes a register that can be configured as combinatorial, as a D flipflop, a T flipflop, or a latch. The clock for this register has the same options as described for the I/O macrocell. One difference on the buried macrocell is the addition of input register capability. The user can program the buried macrocell to act as an input regis ter (Dtype or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its config uration. Functional Description (continued) Logic Block The number of logic blocks distinguishes the members of the FLASH370 FLASH370 family. The CY7C372 CY7C372 includes four logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Programmable Interconnect Matrix Product T erm Array The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C372 CY7C372 to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. The product term array in the FLASH370 FLASH370 logic block includes 36 in puts from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex func tions to be implemented in a single pass through the device. Development Tools Development software for the CY7C372 CY7C372 is available from Cy press's Warp2t and Warp3t software packages. Both of these products are based on the IEEE standard VHDL language. Cy press also supports thirdparty vendors such as ABELt, CUPLt, and LOG/iCt. Please contact your local Cypress representative for further information. Product T erm Allocator The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be as signed to any of the logic block macrocells (this is called product Maximum Ratings LatchUp Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature . . . . . . . . . . . . . . . . . . . -65_C to +150_C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C Supply Voltage to Ground Potential . . . . . . . . . -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Program Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5V Output Current into Outputs . . . . . . . . . . . . . . . . . . . . . . 16 mA Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V (per MILSTD883 MILSTD883, Method 3015) Ambient Temperature 0_C to +70_C 5V ± 5% Industrial -40_C to +85_C 5V ± 10% Military -55_C to +125_C 5V ± 10% Range Commercial Note: 1. 2 TA is the instant on" case temperature. VCC 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 Electrical Characteristics Parameter Over the Operating Range Description VOH Test Conditions Output HIGH Voltage VCC = Min. Min. Max. 2.4 IOH = -3.2 mA (Com'l/Ind) V IOH = -2.0 mA (Mil) VOL Output LOW Voltage VCC = Min. V 0.5 IOL = 16 mA (Com'l/Ind) IOL = 12 mA (Mil) VIH Input HIGH Voltage Unit V V Guaranteed Input Logical HIGH Voltage for all Inputs 2.0 7.0 V -0.5 Inputs 0.8 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all IIX Input Load Current GND < VI < VCC -10 +10 mA IOZ Output Leakage Current GND < VO < VCC, Output Disabled -50 +50 mA IOS Output Short Circuit Current[4, 5] VCC = Max., VOUT = 0.5V -30 -90 mA ICC Power Supply Current VCC = Max., IOUT = 0 mA, f = 1 mHz, VIN = GND, VCC mHz GND Com'l 250 mA Com'l L " -66 125 mA Com'l -125 280 mA Mil/ Industrial 300 mA Shaded area contains preliminary information.  Capacitance Parameter Description Test Conditions Max. Unit CIN Input Capacitance VIN = 5.0V at f=1 MHz 10 pF COUT Output Capacitance VOUT = 5.0V at f = 1 MHz 12 pF Endurance Characteristics Parameter N  Description Minimum Reprogramming Cycles Parameter VX tER (-) 1.5V tER (+) 2.6V tEA (+) 1.5V tEA (-) Vthc Test Conditions Min. Normal Programming Conditions 100 Max. Unit Cycles Output WaveformMeasurement Level VOH VOL VX VX VX 0.5V 0.5V VX 0.5V VOH VOL 0.5V (a) Test Waveforms Notes: 2. 3. 4. See the last page of this specification for Group A subgroup testing in formation. These are absolute values with respect to device ground. All over shoots due to system or tester noise are included. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been cho sen to avoid test problems caused by tester ground degradation. 5. 6. 3 Tested initially and after any design or process changes that may affect these parameters. Meaured with 16bit counter programmed into each logic block. 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 AC Test Loads and Waveforms W W 5V W W 238 (com'l) (mil) (mil) 5V OUTPUT W W W W OUTPUT 170 170 (com'l) 236 35 pF (com'l) 236 (mil) (mil) 5 pF INCLUDING INCLUDING 7c3723 JIG AND JIG AND SCOPE (com'l) 319 238 319 SCOPE (a) (b) ALL INPUT PULSES Equivalent to: 3.0V THÉVENIN EQUIVALENT W W 99 136 90% (com'l) (mil) OUTPUT 90% 10% 10% 2.08V (com'l) GND 2.13V (mil) < 2 ns < 2 ns 7c3724 Switching Characteristics Over the Operating Range 7C372-66 7C372-66 7C372-125 7C372-125 Parameter Min. Description 7C372-100 7C372-100 Min. Max. Max. 7C372-83 7C372-83 Min. Max. 7C372L-66 7C372L-66 Min. Max. Unit Combinatorial Mode Parameters tPD Input to Combinatorial Output 10 12 15 20 ns tPDL Input to Output Through Transparent Input or Output Latch 13 15 18 22 ns tPDLL Input to Output Through Transparent Input and Output Latches 15 16 19 24 ns tEA Input to Output Enable 14 16 19 24 ns tER Input to Output Disable 14 16 19 24 ns Input Registered/Latched Mode Parameters tWL Clock or Latch Enable Input LOW Time 3  3 4 5 ns tWH Clock or Latch Enable Input HIGH Time 3 3 4 5 ns tIS Input Register or Latch SetUp Time 2 2 3 4 ns tIH Input Register or Latch Hold Time 2 2 3 4 ns tICO Input Register Clock or Latch Enable to Combinatorial Output 14 16 19 24 ns tICOL Input Register Clock or Latch Enable to Output Through Transparent Output Latch 16 18 21 26 ns 6.5 6.5 8 10 ns Output Registered/Latched Mode Parameters tCO Clock or Latch Enable to Output tS SetUp Time from Input to Clock or Latch Enable tH Register or Latch Data Hold Time tCO2 Output Clock or Latch Enable to Output Delay (Through Memory Array) tSCS Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) tSL tHL 5.5 6 8 10 ns 0 0 0 0 ns 14 16 19 24 ns 8 10 12 15 ns SetUp Time from Input Through Transparent Latch to Output Register Clock or Latch Enable 10 12 15 20 ns Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable 0 0 0 0 ns Shaded area contains preliminary information. 4 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 Switching Characteristics Parameter Over the Operating Range (continued) 7C372-66 7C372-66 7C372-125 7C372-125 7C372-100 7C372-100 7C372-83 7C372-83 7C372L-66 7C372L-66 Min. Max. Min. Max. Min. Max. Min. Max. Unit Description fMAX1 Maximum Frequency with Internal Feedback in Output Registered Mode (Least of 1/tSCS, 1/(tS + tH), or 1/tCO) 125 100 83 66 MHz fMAX2 Maximum Frequency Data Path in Output Regis tered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) 153.8 153.8 125 100 MHz fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH) 83.3 80 62.5 50 MHz tOH-tIH 37x Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[5, 8] 0 0 0 0 ns tICS Input Register Clock to Output Register Clock 8 10 12 15 ns fMAX4 Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 125 100 83.3 66.6 MHz Pipelined Mode Parameters Reset/Preset Parameters tRW Asynchronous Reset Width 10 12 15 20 ns tRR Asynchronous Reset Recovery Time 12 14 17 22 ns tRO Asynchronous Reset to Output tPW Asynchronous Preset Width tPR Asynchronous Preset Recovery Time tPO 16 10  Asynchronous Preset to Output tPOR PowerOn Reset 18 12 12 21 15 14 26 20 17 ns ns 22 ns 16 21 26 ns 1  18 1 1 1 ms Shaded area contains preliminary information. Note: 7. All AC parameters are measured with 16 outputs switching. 8. This specification is intended to guarantee interface compatibility of the other members of the CY7C370 CY7C370 family with the CY7C372 CY7C372. This specification is met for the devices operating at the same ambient tem perature and at the same power supply voltage. Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT 7c3725 5 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 Switching Waveforms (continued) Registered Input REGISTERED INPUT tIS tIH INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWH tWL CLOCK 7c3726 Registered Output INPUT tS tH CLOCK tCO REGISTERED OUTPUT tWH tWL CLOCK 7c3727 Latched Output INPUT tS tH LATCH ENABLE tPDL tCO LATCHED OUTPUT 7c3728 6 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 Switching Waveforms (continued) Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL tHL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tWH tWL LATCH ENABLE 7c3729 Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK tICS tSCS OUTPUT REGISTER CLOCK 7c37210 Latched Input LATCHED INPUT tIS tIH LATCH ENABLE tPDL tICO COMBINATORIAL OUTPUT tWH tWL LATCH ENABLE 7c37211 7 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 Switching Waveforms (continued) Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK 7c37212 Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK 7c37213 PowerUp Reset Waveform POWER 10% VCC 90% SUPPLY VOLTAGE tPOR REGISTERED ACTIVE LOW OUTPUTS tS CLOCK tPOR MAX = 1 ms tWL 7c37214 Output Enable/Disable INPUT tER tEA OUTPUTS 7c37215 8 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 Ordering Information Speed (MHz) 125 100 83 66 Ordering Code CY7C372-125JC CY7C372-125JC CY7C372-100JC CY7C372-100JC CY7C372-83JC CY7C372-83JC CY7C372-83JI CY7C372-83JI CY7C372-83YMB CY7C372-83YMB CY7C372-66JC CY7C372-66JC CY7C372-66YMB CY7C372-66YMB CY7C372-66JI CY7C372-66JI CY7C372L-66JC CY7C372L-66JC Package Name J67 J67 J67 J67 Y67 J67 Y67 J67 J67 Shaded areas contain preliminary information. Package Type 44Lead Plastic Leaded Chip Carrier 44Lead Plastic Leaded Chip Carrier 44Lead Plastic Leaded Chip Carrier 44Lead Plastic Leaded Chip Carrier 44Lead Ceramic Leaded Chip Carrier 44Lead Plastic Leaded Chip Carrier 44Lead Ceramic Leaded Chip Carrier 44Lead Ceramic Leaded Chip Carrier 44Lead Ceramic Leaded Chip Carrier MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Operating Range Commercial Commercial Commercial Industrial Military Commercial Military Industrial Commercial Switching Characteristics Subgroups Parameter tPD tCO tICO tS tH tIS tIH tICS VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Document #: 38-00213-C 38-00213-C Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Warp2, Warp2+, Warp3 , UltraLogic, and FLASH370 FLASH370 are trademarks of Cypress Semiconductor Corporation. ABEL is a trademark of Data I/O Corporation. LOG/iC is a trademark of Isdata Corporation. CUPL is a trademark of Logical Devices Incorporated. 9 7C372 7C372: Wednesday, September 23, 1992 Revision: October 19, 1995 CY7C372 CY7C372 Package Diagrams 44Lead Plastic Leaded Chip Carrier J67 44Pin Ceramic Leaded Chip Carrier Y67 E Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure of the product may reasonably be expected to result in significant 10 injury to the user. The inclusion of Cypress Semiconductor products in lifesupport systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.