CY7C371 CY7C372 FLASH370 22V10 7C371-100 7C371-83 7C371-66 7C371-50 MIL-STD-883 - Datasheet Archive

 

CYPRESS bSE D SSSTbbS 0�1�S3� Ob4 aCYP PRELIMINARY CY7C371 SEMICONDUCTOR 32-Macrocell Flash PLD Features

 

CYPRESS SEMICONDUCTOR CYPRESS bSE D SSSTbbS 0Ã�1Ã�S3Ã� Ob4 aCYP PRELIMINARY CY7C371 CY7C371 SEMICONDUCTOR 32-Macrocell Flash PLD Features â�¢ 32 macrocells in two logic blocks â�¢ 32 I/O pins â�¢ 6 dedicated inputs including 2 clock pins â�¢ No hidden delays â�¢ High speed - fMAX = 100MHz - tpj>= 10 ns - ts = 7.5 ns - tco = 7.5 ns â�¢ Electrically alterable Flash technology â�¢ Available in 44-pin PLCC, CLCC, and LCC packages â�¢ Pin compatible with the CY7C372 CY7C372 Functional Description The CY7C371 CY7C371 is a Flash Erasable Programmable Logic Device (EPLD) and is part of the FLASH370 FLASH370 family of high-den-sity, high-speed PLDs. Like all members of the FLASH370 FLASH370 family, the CY7C371 CY7C371 is designed to bring the ease of use and high performance of the 22V10 22V10 to high-density PLDs. The 32 macrocells in the CY7C371 CY7C371 are divided between two logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 FLASH370 architecture are connected with an extremely fast and predictable routing resource-the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, rout-ability, speed, and a uniform delay to the interconnect. Like all members of the FLASH370 FLASH370 family, the CY7C371 CY7C371 is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371 CY7C371. In addition, there are four dedicated inputs and two input/clock pins. Finally, the CY7C371 CY7C371 features a very simple timing model. Unlike other high-densi-ty PLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C371 CY7C371 remain the Logic Block Diagram Selection Guide 7C371-100 7C371-100 7C371-83 7C371-83 7C371-66 7C371-66 7C371-50 7C371-50 Maximum Propagation Delay, tpn (ns) 10 12 15 20 Maximum Operating Current, Icc2 (mA) Commercial 240 240 240 Military 260 260 260 Maximum Standby Current, Icci (mA) Commercial 200 200 200 Military 220 220 220 Shaded area contains advanced information. 4-224 CYPRESS SEMICONDUCTOR bSE » 550^2 QDlDSaT TTQ «CYP CfPFESS SEMICCWDUCTOR PRELIMINARY CY7C371 CY7C371 Pin Configuration ^â- cocit-OQ O M to CU CM gçgggg Ã�QQ 35 Logic Block The number of logic blocks distinguishes the members of the FLASH370 FLASH370 family. The CY7C371 CY7C371 includes two logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array The product term array in the FLASH370 FLASH370 logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negativepolarity, making the overall array size72x86. This large array in each logic block allows for very complex functions to be implemented in a single pass through the device. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature. - 65°C to +150°C Ambient Temperature with Power Applied . - 55°Cto+125°C Supply Voltage to Ground Potential. - 0.5V to +7.0V DC Voltage Applied to Outputs in High Z State. - 0.5V to +7.0V DC Input Voltage. - 0.5 V to +7.0V DC Program Voltage.12.5V Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370 FLASH370 PLDs. Note that product term allocation is handled by software and is invisible to the user. HO Macrocell Each of the macrocells on the CY7C371 CY7C371 has a separate associated I/O pin. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The macro-cell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the two logic blocks on the CY7C371 CY7C371 to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Design Tools Development software for the CY7C371 CY7C371 is available from Cypress's \Varp2â�¢ and Warp3~' software packages. Both of thse products are based on the IEEE-standard VHDL language. Cypress also actively supports third-party design tools such as ABEL"", CUPL~", MINC, and LOG/iC". Please contact your local Cypress representative for further information. Output Current into Outputs (LOW) Static Discharge Voltage. (per MIL-STD-883 MIL-STD-883, Method 3015) Latch-Up Current . Operating Range Range Ambient Temperature Vcc Commercial 0°C to +70°C 5V ± 5% Military!1! -55°Cto+125°C 5V ± 10% O . 16 mA >2001V >200 mA Electrical Characteristics Over the Operating RangePl Parameter Description Test Conditions Min. Max. Unit VoH Output HIGH Voltage Vcc = Min. Ioh = -3.2 mA (Com'I/Ind) 2.4 V I0l= -2.0 mA (Mil) V Vol Output LOW Voltage Vcc = Min. Ioh = 16 mA (Com'I/Ind) 0.5 V Iol = 12 mA (Mil) V Vih Input HIGH Voltage 2.0 7.0 V VlL Input LOW Voltage -0.5 0.8 V 4-225 CYPRESS SEMICONDUCTOR bSE D - ESflTbbS IjDIDSMG 71E -CYP r#CTPREss PRELIMINARY CY7C371 CY7C371 -_S? SEMICONDUCTOR Electrical Characteristics Over the Operating Range!2! (continued) Parameter Description Test Conditions Min. Max. Unit Iix Input Load Current GND < Vi< Vcc -10 +10 HA loz Output Leakage Current GND < V0 < Vcc, Output Disabled -50 +50 HA los Output Short Circuit Current!3! Vcc = Max., Vqut = 0.5V -30 -90 mA Icca Power Supply Current Vi = Vcc or GND, f = 40 MHz Cora'l 240 mA Mil 260 Icci Power Supply Current (Standby) Vcc = Max., Iout = 0 mA, f = 0 mHz, V!N = GND, Vcc Com'l 200 mA Mil 220 Capacitance!4! Parameter Description Test Conditions Max. Unit Qn Input Capacitance VIN = 2.0V at f=l MHz 10 pF CqUT Output Capacitance Vqut = 2.0V at f = 1 MHz 12 pF Notes: 1. Ta is the "instant on" case temperature. 2. See the last page of this specification for Group Asubgroup testing information. 3. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. Vout - 0.5 V has been chosen to avoid test problems caused by tester ground degradation. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms 5V O OUTPUT O 238Q (COM'L) 319Q (MIL) 5V O 238Q (COM'L) 319Q (MIL) 35 pFy INCLUDING JIG AND SCOPE (a) OUTPUT O 170Q (COM'L) F 236Q (MIL) 0 pr T INCLUDING - JIG AND SCOPE (b) Equivalent to: THEVENIN EQUIVALENT 99Q (COM'L) 136Q (MIL) 2.08V (COM'L) OUTPUT O-WV-O 2.13V (MIL) 3.0V â-  170Q (COM'L) 236Ã�2 (MIL) GND ALL INPUT PULSES ^¿10' c r V -*PDL - EXX - tco - EXX Parameter Description 7C371-100 7C371-100 7C371-83 7C371-83 7C371-66 7C371-66 7C371-50 7C371-50 Unit Min. Max. Min. Max. Min. Max. Min. Max. Reset/Preset Parameters tRW Asynchronous Reset Width 10 12 15 20 ns tRR Asynchronous Reset Recovery Time 12 14 17 22 ns tRO Asynchronous Reset to Output 16 18 21 26 ns tpw Asynchronous Preset Width 10 12 15 20 ns tpR Asynchronous Preset Recovery Time 12 14 17 22 ns tpo Asynchronous Preset to Output 16 18 21 26 ns -* â�¢WL S s / / 7C371-6 7C371-6 4-228 CYPRESS SEMICONDUCTOR bSE » â-  HSÃ�^bbS 0010543 421 WkC\ £ CYPRESS " SEMICONDUCTOR Switching Waveforms (continued) Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT X -tis- PRELIMINARY X «IH â-  t|co " XXX CY7C371 CY7C371 CLOCK r ' lWH " X -twL" X Input Clock to Output Clock REGISTERED INPUT X INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK " ties â-  Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT X -tis- -tpDL - X -tiH * X X - '[CO - LATCH ENABLE " twH " X - tWL " jr 4-229 CYPRESS SEMICONDUCTOR