CY7C199 7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45 - Datasheet Archive

 

1CY 7C19 9 CY7C199 32K x 8 Static RAM Features · High speed - 10 ns · Fast tDOE · CMOS for optimum

 

fax id: 1030 1CY 7C19 9 CY7C199 CY7C199 32K x 8 Static RAM Features · High speed - 10 ns · Fast tDOE · CMOS for optimum speed/power · Low active power - 467 mW (max, 12 ns "L" version) · Low standby power - 0.275 mW (max, "L" version) · 2V data retention ("L" version only) · Easy memory expansion with CE and OE features · TTL-compatible inputs and outputs · Automatic power-down when deselected Functional Description provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199 CY7C199 is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to improve alpha immunity. The CY7C199 CY7C199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is Logic Block Diagram Pin Configurations DIP / SOJ / SOIC Top View INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1024 x 32 x 8 ARRAY I/O4 I/O6 POWER DOWN COLUMN DECODER I/O7 C199­1 A 14 A 12 A 13 A 11 OE A 10 A7 A6 A5 VCC WE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 3 2 1 28 27 4 26 A4 5 25 A3 6 24 A2 7 23 A1 8 22 OE 9 21 A0 10 20 CE 11 19 I/O 7 18 I/O 6 12 1314151617 C199­3 C199­2 I/O3 I/O5 CE WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/O2 GND I/O3 I/O4 I/O5 I/O0 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND LCC Top View OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 14 A 13 A 12 C199­4 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) L Maximum CMOS Standby Current (mA) 7C199-8 7C199-8 8 120 0.5 L Cypress Semiconductor Corporation 7C199-10 7C199-10 10 110 85 0.5 0.05 · 7C199-12 7C199-12 7C199-15 7C199-15 7C199-20 7C199-20 12 15 20 160 155 150 85 100 90 10 10 10 0.05 0.05 0.05 3901 North First Street · San Jose 7C199-25 7C199-25 25 150 80 10 0.05 7C199-35 7C199-35 7C199-45 7C199-45 35 45 140 140 70 10 10 0.05 · CA 95134 · 408-943-2600 February 1988 ­ Revised July 24, 1997 CY7C199 CY7C199 Maximum Ratings Output Current into Outputs (LOW). 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage . >2001V (per MIL-STD-883 MIL-STD-883, Method 3015) Storage Temperature . ­65°C to +150°C Latch-Up Current . >200 mA Ambient Temperature with Power Applied. ­55°C to +125°C Operating Range Supply Voltage to Ground Potential (Pin 28 to Pin 14) . ­0.5V to +7.0V Range Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% ­40°C to +85°C 5V ± 10% ­55°C to +125°C 5V ± 10% Commercial DC Voltage Applied to Outputs in High Z State[1] .­0.5V to VCC + 0.5V Industrial [1] DC Input Voltage .­0.5V to VCC + 0.5V Military Electrical Characteristics Over the Operating Range[3] 7C199-8 7C199-8 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Output HIGH Voltage VCC=Min., IOH=­4.0 mA VOL Output LOW Voltage VCC=Min., IOL=8.0 mA VIH Input HIGH Voltage 2.2 VCC +0.3V 2.2 VCC +0.3V 2.2 VCC +0.3V VIL Input LOW Voltage ­0.5 0.8 ­0.5 0.8 ­0.5 IIX Input Load Current GND < VI < VCC ­5 +5 ­5 +5 IOZ Output Leakage Current GND < VO < V CC, Output Disabled ­5 +5 ­5 +5 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB2 2.4 7C199-12 7C199-12 VOH ISB1 2.4 7C199-10 7C199-10 0.4 Com'l 120 2.4 0.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC +0.3V V 0.8 ­0.5 0.8 V ­5 +5 ­5 +5 µA ­5 +5 ­5 +5 µA 110 160 155 mA 85 100 mA 180 mA Mil Max. VCC, CE > Com'l VIH, L VIN > VIH or VIN < VIL, f = fMAX Automatic CE Power-Down Current- CMOS Inputs Min. 85 L Automatic CE Power-Down Current- TTL Inputs 7C199-15 7C199-15 5 Max. VCC, Com'l CE > V CC ­ 0.3V L VIN > VCC ­ 0.3V or V IN < 0.3V, f = 0 Mil 5 30 30 mA 5 5 5 mA 0.5 0.5 10 10 mA 0.05 0.05 0.05 0.05 mA 15 mA Notes: 1. VIL (min.) = ­2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 2 CY7C199 CY7C199 Electrical Characteristics Over the Operating Range[3] (continued) 7C199-20 7C199-20 Parameter Description Test Conditions Min. Max. 2.4 7C199-25 7C199-25 Min. Max. 2.4 7C199-35 7C199-35 Min. Max. VOH Output HIGH Voltage VCC=Min., IOH=­4.0 mA 2.4 VOL Output LOW Voltage VCC=Min., IOL=8.0 mA VIH Input HIGH Voltage 2.2 VCC +0.3V 2.2 VCC +0.3V 2.2 VCC +0.3V VIL Input LOW Voltage ­0.5 0.8 ­3.0 0.8 ­3.0 IIX Input Load Current GND < VI < VCC ­5 +5 ­5 +5 IOZ Output Leakage Current GND < VI < VCC, Output Disabled ­5 +5 ­5 +5 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 0.4 Com'l 0.4 150 150 7C199-45 7C199-45 Min. Max. Unit 2.4 0.4 V 0.4 V 2.2 VCC +0.3V V 0.8 ­3.0 0.8 V ­5 +5 ­5 +5 µA ­5 +5 ­5 +5 µA 140 mA 140 L 90 80 70 70 mA Mil 170 150 150 150 mA Automatic CE Power-Down Current- TTL Inputs ISB2 Max. VCC, CE > VIH, Com'l VIN > VIH L or VIN < VIL, f = fMAX 30 30 25 25 mA 5 5 5 5 mA Automatic CE Power-Down Current- CMOS Inputs ISB1 Max. VCC, Com'l CE > VCC ­ 0.3V L VIN > VCC ­ 0.3V or VIN < 0.3V, f=0 Mil 10 10 10 10 mA 0.05 0.05 0.05 0.05 µA 15 15 15 15 mA Capacitance[4] Parameter Description Input Capacitance Output Capacitance CIN COUT Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF ] AC Test Loads and Waveforms[5] R1 481 R1 481 5V 5V OUTPUT ALL INPUT PULSES OUTPUT R2 255 30 pF 3.0V INCLUDING JIGAND SCOPE INCLUDING JIGAND SCOPE (a) Equivalent to: R2 255 5 pF C199­5 (b) THÉVENIN EQUIVALENT 167 OUTPUT 1.73V 3 10% GND tr 90% 90% 10% tr C199­6 CY7C199 CY7C199 Data Retention Characteristics Over the Operating Range (L version only) Parameter Conditions[6] Description VDR VCC for Data Retention ICCDR Data Retention Current Min. Max. 2.0 tCDR[4] VCC = VDR = 2.0V, CE > VCC ­ 0.3V, Com'l L VIN > VCC ­ 0.3V or Chip Deselect to Data Retention Time VIN < 0.3V tR[5] Operation Recovery Time Unit V µA Com'l 10 µA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V VDR > 2V 3.0V tR tCDR CE C199­7 Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. tR < 3 ns for the -12 and -15 speeds. tR < 5 ns for the -20 and slower speeds. 6. No input may exceed V CC + 0.5V. 4 CY7C199 CY7C199 Switching Characteristics Over the Operating Range[3, 7] 7C199-8 7C199-8 Parameter Description Min. Max. 7C199-10 7C199-10 Min. Max. 7C199-12 7C199-12 Min. Max. 7C199-15 7C199-15 Min. Max. Unit 15 ns READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 8 tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Low Z[8] tHZOE 3 3 OE HIGH to High Z[8, 9] CE LOW to Low tLZCE Z[8] CE HIGH to High tPU CE LOW to Power-Up 3 4 0 5 5 8 7 0 3 0 7 5 ns ns ns 7 0 12 ns ns 3 0 10 ns 15 5 0 5 ns 3 12 5 3 CE HIGH to Power-Down tPD 3 0 5 15 12 10 4.5 0 Z[8,9] tHZCE 12 10 8 OE LOW to Data Valid tLZOE 10 8 ns ns 15 ns [10, 11] WRITE CYCLE tWC Write Cycle Time 8 10 12 15 ns tSCE CE LOW to Write End 7 7 9 10 ns tAW Address Set-Up to Write End 7 7 9 10 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 7 7 8 9 ns tSD Data Set-Up to Write End 5 5 8 9 ns tHD Data Hold from Write End 0 0 0 0 ns Z[9] tHZWE WE LOW to High tLZWE WE HIGH to Low Z[8] 5 3 6 3 7 3 7 3 ns ns Notes: 7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 CY7C199 CY7C199 Switching Characteristics Over the Operating Range[3,7] (continued) 7C199 7C199­20 Parameter Description Min. Max. 7C199 7C199­25 Min. Max. 7C199 7C199­35 Min. Max. 7C199 7C199­45 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[8] tHZOE tLZCE OE HIGH to High 20 20 9 CE HIGH to High tPU tPD WRITE CYCLE 3 9 CE HIGH to Power-Down 0 20 ns 16 15 ns ns 15 3 15 0 20 ns 3 3 ns 45 16 11 0 3 3 11 ns 45 35 10 3 CE LOW to Power-Up 3 3 9 45 35 25 0 Z[8,9] tHZCE 3 20 [8] 35 25 3 Z[8,9] CE LOW to Low Z 25 ns 15 0 20 ns ns ns 25 ns [10,11] tWC Write Cycle Time 20 25 35 45 ns tSCE CE LOW to Write End 15 18 22 22 ns tAW Address Set-Up to Write End 15 20 30 40 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 15 18 22 22 ns tSD Data Set-Up to Write End 10 10 15 15 ns tHD Data Hold from Write End 0 0 0 0 ns Z[9] tHZWE WE LOW to High tLZWE WE HIGH to Low Z[8] 10 11 3 3 15 3 15 3 ns ns Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID C199­8 Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 6 CY7C199 CY7C199 Switching Waveforms (continued) Read Cycle No. 2 [13, 14] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C199­9 Write Cycle No. 1 (WE Controlled)[10, 15, 16] tWC ADDRESS CE tAW WE tHA tSA tPWE OE tSD tHD DATAIN VALID DATA I/O tHZOE C199­10 Write Cycle No. 2 (CE Controlled)[10, 15, 16] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID C199­11 Notes: 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 7 CY7C199 CY7C199 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled OE LOW)[11, 16] tWC ADDRESS CE tAW tHA tSA WE tHD tSD DATA I/O DATAIN VALID tLZWE tHZWE C199­12 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC,I SB 1.2 ICC 1.0 0.8 0.6 VIN =5.0V TA =25°C 0.4 0.2 1.2 1.0 0.8 0.6 VCC =5.0V VIN =5.0V 0.4 0.2 ISB 0.0 4.0 ICC 4.5 5.0 5.5 ISB 0.0 ­55 6.0 1.6 1.4 NORMALIZED t AA 1.3 1.2 1.1 TA =25°C 1.0 1.4 1.2 1.0 VCC =5.0V 0.8 0.9 4.5 5.0 5.5 SUPPLY VOLTAGE(V) 120 100 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 6.0 0.6 ­55 25 125 AMBIENT TEMPERATURE(°C) 8 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE NORMALIZED t AA 125 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE(V) 0.8 4.0 25 OUTPUT SINK CURRENT (mA) NORMALIZED ICC,I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 VCC =5.0V TA =25°C 40 20 0 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE(V) 4.0 CY7C199 CY7C199 Typical DC and AC Characteristics (continued) TYPICAL POWER­ON CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 25.0 2.0 1.5 1.0 20.0 15.0 VCC =4.5V TA =25°C 10.0 NORMALIZED I CC 2.5 NORMALIZED I CC vs. CYCLE TIME 1.25 30.0 DELTA t AA (ns) NORMALIZED I PO 3.0 VCC =5.0V TA =25°C VIN =0.5V 1.00 0.75 5.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 0.0 0 SUPPLY VOLTAGE(V) 200 400 600 800 1000 CAPACITANCE(pF) 0.50 10 20 Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power-Down Standby (ISB) L H L Data Out Read L L X Data In Write Active (ICC) Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) 8 10 12 Ordering Code CY7C199-8VC CY7C199-8VC CY7C199-8ZC CY7C199-8ZC CY7C199L-8VC CY7C199L-8VC CY7C199L-8ZC CY7C199L-8ZC CY7C199-10VC CY7C199-10VC CY7C199-10ZC CY7C199-10ZC CY7C199L-10VC CY7C199L-10VC CY7C199L-10ZC CY7C199L-10ZC CY7C199-10VI CY7C199-10VI CY7C199-10ZI CY7C199-10ZI CY7C199L-10VI CY7C199L-10VI CY7C199L-10ZI CY7C199L-10ZI CY7C199-12PC CY7C199-12PC CY7C199-12VC CY7C199-12VC CY7C199-12ZC CY7C199-12ZC CY7C199L-12PC CY7C199L-12PC CY7C199L-12VC CY7C199L-12VC CY7C199L-12ZC CY7C199L-12ZC CY7C199-12VI CY7C199-12VI CY7C199-12ZI CY7C199-12ZI CY7C199L-12VI CY7C199L-12VI CY7C199L-12ZI CY7C199L-12ZI Package Name V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 P21 V21 Z28 P21 V21 Z28 V21 Z28 V21 Z28 Package Type 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 9 30 CYCLE FREQUENCY(MHz) Operating Range Commercial Commercial Industrial Commercial Industrial 40 CY7C199 CY7C199 Ordering Information (continued) Speed (ns) 15 20 25 35 45 Ordering Code CY7C199-15PC CY7C199-15PC CY7C199-15VC CY7C199-15VC CY7C199-15ZC CY7C199-15ZC CY7C199L-15PC CY7C199L-15PC CY7C199L-15VC CY7C199L-15VC CY7C199L-15ZC CY7C199L-15ZC CY7C199-15VI CY7C199-15VI CY7C199-15ZI CY7C199-15ZI CY7C199-15DMB CY7C199-15DMB CY7C199-15LMB CY7C199-15LMB CY7C199L-15DMB CY7C199L-15DMB CY7C199L-15LMB CY7C199L-15LMB CY7C199-20PC CY7C199-20PC CY7C199-20VC CY7C199-20VC CY7C199-20ZC CY7C199-20ZC CY7C199L-20PC CY7C199L-20PC CY7C199L-20VC CY7C199L-20VC CY7C199L-20ZC CY7C199L-20ZC CY7C199-20VI CY7C199-20VI CY7C199-20ZI CY7C199-20ZI CY7C199-20DMB CY7C199-20DMB CY7C199-20LMB CY7C199-20LMB CY7C199L-20DMB CY7C199L-20DMB CY7C199L-20LMB CY7C199L-20LMB CY7C199-25PC CY7C199-25PC CY7C199-25SC CY7C199-25SC CY7C199-25VC CY7C199-25VC CY7C199-25ZC CY7C199-25ZC CY7C199L-25ZI CY7C199L-25ZI CY7C199-25DMB CY7C199-25DMB CY7C199-25LMB CY7C199-25LMB CY7C199-35PC CY7C199-35PC CY7C199-35SC CY7C199-35SC CY7C199-35VC CY7C199-35VC CY7C199-35ZC CY7C199-35ZC CY7C199-35DMB CY7C199-35DMB CY7C199-35LMB CY7C199-35LMB CY7C199-45DMB CY7C199-45DMB CY7C199-45LMB CY7C199-45LMB Package Name P21 V21 Z28 P21 V21 Z28 V21 Z28 D22 L54 D22 L54 P21 V21 Z28 P21 V21 Z28 V21 Z28 D22 L54 D22 L54 P21 S21 V21 Z28 Z28 D22 L54 P21 S21 V21 Z28 D22 L54 D22 L54 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier Operating Range Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Commercial Military Military Shaded area contains preliminary information. Contact your Cypress sales representative for availability 10 CY7C199 CY7C199 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 Switching Characteristics Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Parameter READ CYCLE tRC tAA tOHA tACE tDOE WRITE CYCLE tWC tAA tAW tHA tSA tPWE tSD tHD Document #: 38­00239­D Subgroups 7, 8, 7, 8, 7, 8, 7, 8, 7, 8, 9, 9, 9, 9, 9, 10, 11 10, 11 10, 11 10, 11 10, 11 7, 8, 7, 8, 7, 8, 7, 8, 7, 8, 7, 8, 7, 8, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL­STD­1835 28-Pin Rectangular Leadless Chip Carrier L54 D­15Config.A MIL­STD­1835 C­11A 11 CY7C199 CY7C199 Package Diagrams (continued) 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Molded SOIC S21 12 CY7C199 CY7C199 Package Diagrams (continued) 28-Lead (300-Mil) Molded SOJ V21 28-Lead Thin Small Outline Package Z28 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.