CY7C1399V C1399V-2 C1399V-1 7C1399V-12 7C1399V-15 7C1399V-20 7C1399V-25 - Datasheet Archive

 

CY7C1399V 32K x 8 3.0V Static RAM Features · Single 3.0V power supply · Ideal for low-voltage cache memory

 

1CY 7C13 99 V CY7C1399V CY7C1399V 32K x 8 3.0V Static RAM Features · Single 3.0V power supply · Ideal for low-voltage cache memory applications · High speed - 12/15 ns · Low active power - 198 mW (max.) · Low CMOS standby power (L) - 165 mW (max.), f=fMAX · 2.0V data retention (L) - 40 mW (max.) · Low-power alpha immune 6T cell · Plastic SOJ and TSOP packaging Functional Description pansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. The CY7C1399V CY7C1399V is available in standard 300-mil-wide SOJ and 28-pin TSOP type I packages. The CY7C1399V CY7C1399V is a high-performance 3.0V CMOS static RAM organized as 32,768 words by 8 bits. Easy memory ex- Logic Block Diagram Pin Configurations SOJ Top View I/O0 INPUTBUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND I/O1 I/O2 I/O3 32K x 8 ARRA Y 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O4 C1399V-2 C1399V-2 I/O5 I/O6 POWER DOWN COLUMN DECODER I/O7 OE C1399V-1 C1399V-1 Selection Guide 7C1399V-12 7C1399V-12 7C1399V-15 7C1399V-15 7C1399V-20 7C1399V-20 7C1399V-25 7C1399V-25 7C1399V-35 7C1399V-35 Maximum Access Time (ns) 12 15 20 25 35 Maximum Operating Current (mA) 60 55 50 45 40 500 500 500 500 500 50 50 50 50 50 Maximum CMOS Standby Current (µA) Maximum CMOS Standby Current (µA) L Shaded area contains advanced information. Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 January 1996 ­ Revised June 1996 CY7C1399V CY7C1399V Pin Configurations (continued) TSOP Top View OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 21 22 23 20 19 18 17 16 15 14 13 12 11 10 9 8 24 25 26 27 28 1 2 3 4 5 6 7 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A 14 A 13 A 12 C1399V-3 C1399V-3 Maximum Ratings Output Current into Outputs (LOW). 20 mA Static Discharge Voltage . >2001V (per MIL-STD-883 MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature . -65°C to +150°C Latch-Up Current . >200 mA Ambient Temperature with Power Applied. -55°C to +125°C Operating Range Range Supply Voltage on VCC to Relative GND[1] .-0.5V to +4.6V DC Input Voltage VCC 0°C to +70°C 3.0V ±300 mV -40°C to +85°C 3.0V ±300 mV Commercial DC Voltage Applied to Outputs in High Z State[1] . -0.5V to VCC + 0.5V [1] . -0.5V Ambient Temperature Industrial to VCC + 0.5V Electrical Characteristics Over the Operating Range[2] 7C1399V-12 7C1399V-12 7C1399V-15 7C1399V-15 7C1399V-20 7C1399V-20 Parameter Description Test Conditions Min. VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 4.0 mA Max. Max. Max. Output LOW Voltage VIH Input HIGH Voltage 2.2 VCC +0.3V 2.2 VCC +0.3V VIL Input LOW Voltage[2] -0.3 0.8 -0.3 IIX Input Load Current -1 +1 -1 IOZ Output Leakage Current GND < VI < VCC,Output Disabled +5 -5 +5 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND -300 -300 -300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 60 55 50 mA ISB1 Automatic CE Power-Down Current - TTL Inputs Max. VCC, CE > VIH, VIN > VIH, or VIN < VIL, f = fMAX 5 5 5 mA L 3 3 3 Automatic CE Power-Down Current - CMOS Inputs[4] Max. VCC, CE > VCC-0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, WE>VCC-0.3V or WE< 0.3V, f=fMAX 500 500 500 L 50 50 50 2 0.4 -5 2.4 Unit VOL Shaded area contains advanced information. Notes: 1. Minimum voltage is equal to -2.0V for pulse durations of less than 20 ns. 2. See the last page of this specification for Group A subgroup testing information. 2.4 Min. Output HIGH Voltage ISB2 2.4 Min. VOH 0.4 V 0.4 V 2.2 VCC +0.3V V 0.8 -0.3 0.8 V +1 -1 +1 µA +5 -5 µA CY7C1399V CY7C1399V Electrical Characteristics Over the Operating Range[2] (continued) 7C1399V-25 7C1399V-25 Parameter Description Test Conditions Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = -2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA VIH Input HIGH Voltage 2.0 Input LOW Voltage[2] -0.3 IIX Input Load Current -1 IOZ Output Leakage Current GND < VI < VCC, Output Disabled IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND ICC VCC Operating Supply Current ISB1 Min. VCC +0.3V VIL 7C1399V-35 7C1399V-35 2.4 Max. V 0.4 0.4 V 2.0 VCC +0.3V V 0.8 -0.3 0.8 V +1 -1 +1 µA +5 -5 +5 µA -300 -300 mA VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 45 40 mA Automatic CE Power-Down Current - TTL Inputs Max. VCC, CE > VIH, VIN > VIH, or VIN < VIL, f = fMAX 5 5 mA L 3 3 mA Automatic CE Power-Down Current - CMOS Inputs[4] ISB2 -5 Unit 2.4 Max. VCC, CE > VCC-0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, WE>VCC-0.3V or WE< 0.3V, f=fMAX 500 500 µA L 50 50 µA Capacitance[5] Parameter Description CIN: Addresses Input Capacitance CIN: Controls COUT Test Conditions Max. pF 6 pF 6 Output Capacitance Unit 5 TA = 25°C, f = 1 MHz, VCC = 3.0V pF AC Test Loads and Waveforms R1 577 3.0V ALL INPUT PULSES OUTPUT 3.0V 10% R2 790 CL GND < 3 ns INCLUDING JIG AND SCOPE Equivalent to: 90% < 3 ns C1399V-4 C1399V-4 THÉVENIN EQUIVALENT 333 OUTPUT 90% 10% 1.73V Notes: 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Device draws low standby current regardless of switching on the addresses. 5. Tested initially and after any design or process changes that may affect these parameters. 3 CY7C1399V CY7C1399V Switching Characteristics Over the Operating Range[2, 6] 7C1399V-12 7C1399V-12 Parameter 7C1399V-20 7C1399V-20 7C1399V-25 7C1399V-25 7C1399V-35 7C1399V-35 Min. Description 7C1399V-15 7C1399V-15 Min. Min. Min. Min. Max. Max. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 12 tOHA Data Hold from Address Change tACE CE LOW to Data Valid 12 15 20 25 35 ns tDOE OE LOW to Data Valid 5 6 7 8 10 ns [7] tLZOE OE LOW to Low Z OE HIGH to High tLZCE 3 0 CE LOW to Low Z[7] 5 tHZCE CE HIGH to High tPU CE LOW to Power-Up 6 tPD CE HIGH to Power-Down 0 12 7 3 ns ns 7 ns 3 7 15 ns 0 6 0 ns 35 3 0 3 7 0 35 25 3 0 3 6 25 20 3 0 3 Z[7, 8] 20 15 3 Z[7, 8] tHZOE 15 12 8 0 ns 8 ns 0 20 25 ns 35 ns WRITE CYCLE[9, 10] tWC Write Cycle Time 12 15 20 25 35 ns tSCE CE LOW to Write End 8 10 12 15 20 ns tAW Address Set-Up to Write End 8 10 12 15 20 ns tHA Address Hold from Write End 0 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 0 ns tPWE WE Pulse Width 8 10 12 15 20 ns tSD Data Set-Up to Write End 6 9 10 11 12 ns tHD Data Hold from Write End 0 0 0 0 0 ns tLZWE WE LOW to High WE HIGH to Low tHZWE Z[8] Z[7] 7 7 3 3 7 3 7 3 7 ns 3 ns Shaded area contains advanced information. Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Conditions Data Retention Current Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR[5] Min. Max. 2.0 L VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Operation Recovery Time Unit V 200 µA 20 µA 0 ns tRC ns Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 4 CY7C1399V CY7C1399V Data Retention Waveform DATA RETENTION MODE 2.7V VCC 2.7V VDR > 2V t CDR tR CE C1399V-5 C1399V-5 Switching Waveforms Read Cycle No. 1 [11,12] tRC ADDRESS t OHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID C1399V-6 C1399V-6 ReadCycle No. 2 [12,13] t RC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C1399V-7 C1399V-7 Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. 5 CY7C1399V CY7C1399V Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [9,14,15] t WC ADDRESS CE t AW t HA t SA WE t PWE OE tSD DATA I/O NOTE 16 t HD DATA IN VALID tHZOE C1399V C1399V­8 Write Cycle No. 2 (CEControlled) [9,14,15] tWC ADDRESS tSCE CE tSA tAW tHA WE t SD DATA I/O t HD DATA IN VALID C1399V C1399V­9 Write Cycle No.3 (WE Controlled, OE LOW) [10,15] t WC ADDRESS CE tAW WE t HA t SA tSD DATA I/O NOTE 16 t HD DATA IN VALID tLZWE t HZWE C1399V-10 C1399V-10 Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in the output state and input signals shold not be applied. 6 CY7C1399V CY7C1399V Truth Table CE WE OE H X X High Z Input/Output Deselect/Power-Down Mode Standby (ISB) Power L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) 12 Ordering Code Package Name Package Type 28-Lead Molded SOJ Z28 28-Lead Thin Small Outline Package Z28 28-Lead Thin Small Outline Package CY7C1399V-15VC CY7C1399V-15VC V21 28-Lead Molded SOJ CY7C1399VL-15VC CY7C1399VL-15VC V21 28-Lead Molded SOJ CY7C1399V-15ZC CY7C1399V-15ZC Z28 28-Lead Thin Small Outline Package CY7C1399VL-15ZC CY7C1399VL-15ZC Z28 28-Lead Thin Small Outline Package CY7C1399V-15ZI CY7C1399V-15ZI Z28 28-Lead Thin Small Outline Package CY7C1399VL-15ZI CY7C1399VL-15ZI Z28 28-Lead Thin Small Outline Package CY7C1399V-20VC CY7C1399V-20VC V21 28-Lead Molded SOJ CY7C1399VL-20VC CY7C1399VL-20VC V21 28-Lead Molded SOJ CY7C1399V-20ZC CY7C1399V-20ZC Z28 28-Lead Thin Small Outline Package CY7C1399VL-20ZC CY7C1399VL-20ZC Z28 28-Lead Thin Small Outline Package CY7C1399V-25VC CY7C1399V-25VC V21 28-Lead Molded SOJ CY7C1399VL-25VC CY7C1399VL-25VC V21 28-Lead Molded SOJ CY7C1399V-25ZC CY7C1399V-25ZC Z28 28-Lead Thin Small Outline Package CY7C1399VL-25ZC CY7C1399VL-25ZC Z28 28-Lead Thin Small Outline Package CY7C1399V-35VC CY7C1399V-35VC V21 28-Lead Molded SOJ CY7C1399VL-35VC CY7C1399VL-35VC V21 28-Lead Molded SOJ CY7C1399V-35ZC CY7C1399V-35ZC Z28 28-Lead Thin Small Outline Package CY7C1399VL-35ZC CY7C1399VL-35ZC 35 V21 CY7C1399VL-12ZC CY7C1399VL-12ZC 25 28-Lead Molded SOJ CY7C1399V-12ZC CY7C1399V-12ZC 20 V21 CY7C1399VL-12VC CY7C1399VL-12VC 15 CY7C1399V-12VC CY7C1399V-12VC Z28 28-Lead Thin Small Outline Package Operating Range Shaded area contains advanced information. Document #: 38-00507-A 7 Commercial Commercial Industrial Commercial Commercial Commercial CY7C1399V CY7C1399V Package Diagrams 28-Lead Molded SOJ V21 28-Lead Thin Small Outline Package Z28 © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.